1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2018, Joyent, Inc.
24 */
25
26 #ifndef _SYS_CONTROLREGS_H
27 #define _SYS_CONTROLREGS_H
28
29 #ifndef _ASM
30 #include <sys/types.h>
31 #endif
32
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36
37 /*
38 * This file describes the x86 architecture control registers which
39 * are part of the privileged architecture.
40 *
41 * Many of these definitions are shared between IA-32-style and
42 * AMD64-style processors.
43 */
44
45 /* CR0 Register */
46
47 #define CR0_PG 0x80000000 /* paging enabled */
48 #define CR0_CD 0x40000000 /* cache disable */
49 #define CR0_NW 0x20000000 /* not writethrough */
50 #define CR0_AM 0x00040000 /* alignment mask */
51 #define CR0_WP 0x00010000 /* write protect */
52 #define CR0_NE 0x00000020 /* numeric error */
53 #define CR0_ET 0x00000010 /* extension type */
54 #define CR0_TS 0x00000008 /* task switch */
55 #define CR0_EM 0x00000004 /* emulation */
56 #define CR0_MP 0x00000002 /* monitor coprocessor */
57 #define CR0_PE 0x00000001 /* protection enabled */
58
59 /* XX64 eliminate these compatibility defines */
60
61 #define CR0_CE CR0_CD
62 #define CR0_WT CR0_NW
63
64 #define FMT_CR0 \
65 "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe"
66
67 /*
68 * Set the FPU-related control bits to explain to the processor that
69 * we're managing FPU state:
70 * - set monitor coprocessor (allow TS bit to control FPU)
71 * - set numeric exception (disable IGNNE# mechanism)
72 * - set task switch (#nm on first fp instruction)
73 * - clear emulate math bit (cause we're not emulating!)
74 */
75 #define CR0_ENABLE_FPU_FLAGS(cr) \
76 (((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM)
77
78 /*
79 * Set the FPU-related control bits to explain to the processor that
80 * we're -not- managing FPU state:
81 * - set emulate (all fp instructions cause #nm)
82 * - clear monitor coprocessor (so fwait/wait doesn't #nm)
83 */
84 #define CR0_DISABLE_FPU_FLAGS(cr) \
85 (((cr) | CR0_EM) & (uint32_t)~CR0_MP)
86
87 /* CR3 Register */
88
89 #define CR3_PCD 0x00000010 /* cache disable */
90 #define CR3_PWT 0x00000008 /* write through */
91 #if defined(_ASM)
92 #define CR3_NOINVL_BIT 0x8000000000000000
93 #else
94 #define CR3_NOINVL_BIT 0x8000000000000000ULL /* no invalidation */
95 #endif
96 #define PCID_NONE 0x000 /* generic PCID */
97 #define PCID_KERNEL 0x000 /* kernel's PCID */
98 #define PCID_USER 0x001 /* user-space PCID */
99
100 /* CR4 Register */
101
102 #define CR4_VME 0x0001 /* virtual-8086 mode extensions */
103 #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */
104 #define CR4_TSD 0x0004 /* time stamp disable */
105 #define CR4_DE 0x0008 /* debugging extensions */
106 #define CR4_PSE 0x0010 /* page size extensions */
107 #define CR4_PAE 0x0020 /* physical address extension */
108 #define CR4_MCE 0x0040 /* machine check enable */
109 #define CR4_PGE 0x0080 /* page global enable */
110 #define CR4_PCE 0x0100 /* perf-monitoring counter enable */
111 #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */
112 #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */
113 /* 0x0800 reserved */
114 /* 0x1000 reserved */
115 #define CR4_VMXE 0x2000
116 #define CR4_SMXE 0x4000
117 #define CR4_PCIDE 0x20000 /* PCID enable */
118 #define CR4_OSXSAVE 0x40000 /* OS xsave/xrestore support */
119 #define CR4_SMEP 0x100000 /* NX for user pages in kernel */
120 #define CR4_SMAP 0x200000 /* kernel can't access user pages */
121
122 #define FMT_CR4 \
123 "\20\26smap\25smep\23osxsav\22pcide" \
124 "\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge" \
125 "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
126
127 /*
128 * Enable the SSE-related control bits to explain to the processor that
129 * we're managing XMM state and exceptions
130 */
131 #define CR4_ENABLE_SSE_FLAGS(cr) \
132 ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT)
133
134 /*
135 * Disable the SSE-related control bits to explain to the processor
136 * that we're NOT managing XMM state
137 */
138 #define CR4_DISABLE_SSE_FLAGS(cr) \
139 ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT))
140
141 /* Intel's SYSENTER configuration registers */
142
143 #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */
144 #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */
145 #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */
146
147 /* Intel's microcode registers */
148 #define MSR_INTC_UCODE_WRITE 0x79 /* microcode write */
149 #define MSR_INTC_UCODE_REV 0x8b /* microcode revision */
150 #define INTC_UCODE_REV_SHIFT 32 /* Bits 63:32 */
151
152 /* Intel's platform identification */
153 #define MSR_INTC_PLATFORM_ID 0x17
154 #define INTC_PLATFORM_ID_SHIFT 50 /* Bit 52:50 */
155 #define INTC_PLATFORM_ID_MASK 0x7
156
157 /* AMD's EFER register */
158
159 #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */
160
161 #define AMD_EFER_FFXSR 0x4000 /* fast fxsave/fxrstor */
162 #define AMD_EFER_SVME 0x1000 /* svm enable */
163 #define AMD_EFER_NXE 0x0800 /* no-execute enable */
164 #define AMD_EFER_LMA 0x0400 /* long mode active (read-only) */
165 #define AMD_EFER_LME 0x0100 /* long mode enable */
166 #define AMD_EFER_SCE 0x0001 /* system call extensions */
167
168 #define FMT_AMD_EFER \
169 "\20\17ffxsr\15svme\14nxe\13lma\11lme\1sce"
170
171 /* AMD's SYSCFG register */
172
173 #define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */
174
175 #define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */
176 #define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */
177 #define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */
178 #define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */
179
180 #define FMT_AMD_SYSCFG \
181 "\20\26tom2\25mvdm\24mfdm\23mfde"
182
183 /* AMD's syscall/sysret MSRs */
184
185 #define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */
186 #define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */
187 #define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */
188 #define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */
189
190 /* AMD's FS.base and GS.base MSRs */
191
192 #define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */
193 #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */
194 #define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */
195 #define MSR_AMD_TSCAUX 0xc0000103 /* %ecx value on rdtscp insn */
196
197 /* AMD's configuration MSRs, weakly documented in the revision guide */
198
199 #define MSR_AMD_DC_CFG 0xc0011022
200
201 #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3)
202 #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10)
203
204 /* AMD's HWCR MSR */
205
206 #define MSR_AMD_HWCR 0xc0010015
207
208 #define AMD_HWCR_TLBCACHEDIS (UINT64_C(1) << 3)
209 #define AMD_HWCR_FFDIS 0x00040 /* disable TLB Flush Filter */
210 #define AMD_HWCR_MCI_STATUS_WREN 0x40000 /* enable write of MCi_STATUS */
211
212 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
213
214 #define MSR_AMD_NB_CFG 0xc001001f
215
216 #define AMD_NB_CFG_SRQ_HEARTBEAT (UINT64_C(1) << 20)
217 #define AMD_NB_CFG_SRQ_SPR (UINT64_C(1) << 32)
218
219 #define MSR_AMD_BU_CFG 0xc0011023
220
221 #define AMD_BU_CFG_E298 (UINT64_C(1) << 1)
222
223 #define MSR_AMD_DE_CFG 0xc0011029
224
225 #define AMD_DE_CFG_E721 (UINT64_C(1))
226
227 /* AMD's osvw MSRs */
228 #define MSR_AMD_OSVW_ID_LEN 0xc0010140
229 #define MSR_AMD_OSVW_STATUS 0xc0010141
230
231
232 #define OSVW_ID_LEN_MASK 0xffffULL
233 #define OSVW_ID_CNT_PER_MSR 64
234
235 /*
236 * Enable PCI Extended Configuration Space (ECS) on Greyhound
237 */
238 #define AMD_GH_NB_CFG_EN_ECS (UINT64_C(1) << 46)
239
240 /* AMD microcode patch loader */
241 #define MSR_AMD_PATCHLEVEL 0x8b
242 #define MSR_AMD_PATCHLOADER 0xc0010020
243
244 #ifdef __cplusplus
245 }
246 #endif
247
248 #endif /* !_SYS_CONTROLREGS_H */