4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 #ifndef _VM_HAT_PTE_H
27 #define _VM_HAT_PTE_H
28
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32
33 #include <sys/types.h>
34 #include <sys/mach_mmu.h>
35
36 /*
37 * macros to get/set/clear the PTE fields
38 */
39 #define PTE_SET(p, f) ((p) |= (f))
40 #define PTE_CLR(p, f) ((p) &= ~(x86pte_t)(f))
41 #define PTE_GET(p, f) ((p) & (f))
42
43 /*
121 * AMD/INTEL name Level #
122 * ---------------------- -------
123 * Page Map Level 4 3
124 * Page Directory Pointer 2
125 * Page Directory 1
126 * Page Table 0
127 *
128 * The numbering scheme is such that the values of 0 and 1 can correspond to
129 * the pagesize codes used for MPSS support. For now the Maximum level at
130 * which you can have a large page is a constant, that may change in
131 * future processors.
132 *
133 * The type of "level_t" is signed so that it can be used like:
134 * level_t l;
135 * ...
136 * while (--l >= 0)
137 * ...
138 */
139 #define MAX_NUM_LEVEL 4
140 #define MAX_PAGE_LEVEL 2
141 typedef int8_t level_t;
142 #define LEVEL_SHIFT(l) (mmu.level_shift[l])
143 #define LEVEL_SIZE(l) (mmu.level_size[l])
144 #define LEVEL_OFFSET(l) (mmu.level_offset[l])
145 #define LEVEL_MASK(l) (mmu.level_mask[l])
146
147 /*
148 * Macros to:
149 * Check for a PFN above 4Gig and 64Gig for 32 bit PAE support
150 */
151 #define PFN_4G (4ull * (1024 * 1024 * 1024 / MMU_PAGESIZE))
152 #define PFN_64G (64ull * (1024 * 1024 * 1024 / MMU_PAGESIZE))
153 #define PFN_ABOVE4G(pfn) ((pfn) >= PFN_4G)
154 #define PFN_ABOVE64G(pfn) ((pfn) >= PFN_64G)
155
156 /*
157 * The CR3 register holds the physical address of the top level page table.
158 */
159 #define MAKECR3(pfn) mmu_ptob(pfn)
160
161 /*
162 * HAT/MMU parameters that depend on kernel mode and/or processor type
163 */
164 struct htable;
165 struct hat_mmu_info {
166 x86pte_t pt_nx; /* either 0 or PT_NX */
167 x86pte_t pt_global; /* either 0 or PT_GLOBAL */
168
169 pfn_t highest_pfn;
170
171 uint_t num_level; /* number of page table levels in use */
172 uint_t max_level; /* just num_level - 1 */
173 uint_t max_page_level; /* maximum level at which we can map a page */
174 uint_t umax_page_level; /* max user page map level */
175 uint_t ptes_per_table; /* # of entries in lower level page tables */
176 uint_t top_level_count; /* # of entries in top most level page table */
177
178 uint_t hash_cnt; /* cnt of entries in htable_hash_cache */
179 uint_t vlp_hash_cnt; /* cnt of entries in vlp htable_hash_cache */
180
181 uint_t pae_hat; /* either 0 or 1 */
182
183 uintptr_t hole_start; /* start of VA hole (or -1 if none) */
184 uintptr_t hole_end; /* end of VA hole (or 0 if none) */
185
186 struct htable **kmap_htables; /* htables for segmap + 32 bit heap */
187 x86pte_t *kmap_ptes; /* mapping of pagetables that map kmap */
188 uintptr_t kmap_addr; /* start addr of kmap */
189 uintptr_t kmap_eaddr; /* end addr of kmap */
190
191 uint_t pte_size; /* either 4 or 8 */
192 uint_t pte_size_shift; /* either 2 or 3 */
193 x86pte_t ptp_bits[MAX_NUM_LEVEL]; /* bits set for interior PTP */
194 x86pte_t pte_bits[MAX_NUM_LEVEL]; /* bits set for leaf PTE */
195
196 /*
197 * A range of VA used to window pages in the i86pc/vm code.
198 * See PWIN_XXX macros.
199 */
|
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 * Copyright 2018 Joyent, Inc.
25 */
26
27 #ifndef _VM_HAT_PTE_H
28 #define _VM_HAT_PTE_H
29
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33
34 #include <sys/types.h>
35 #include <sys/mach_mmu.h>
36
37 /*
38 * macros to get/set/clear the PTE fields
39 */
40 #define PTE_SET(p, f) ((p) |= (f))
41 #define PTE_CLR(p, f) ((p) &= ~(x86pte_t)(f))
42 #define PTE_GET(p, f) ((p) & (f))
43
44 /*
122 * AMD/INTEL name Level #
123 * ---------------------- -------
124 * Page Map Level 4 3
125 * Page Directory Pointer 2
126 * Page Directory 1
127 * Page Table 0
128 *
129 * The numbering scheme is such that the values of 0 and 1 can correspond to
130 * the pagesize codes used for MPSS support. For now the Maximum level at
131 * which you can have a large page is a constant, that may change in
132 * future processors.
133 *
134 * The type of "level_t" is signed so that it can be used like:
135 * level_t l;
136 * ...
137 * while (--l >= 0)
138 * ...
139 */
140 #define MAX_NUM_LEVEL 4
141 #define MAX_PAGE_LEVEL 2
142 #define MIN_PAGE_LEVEL 0
143 typedef int8_t level_t;
144 #define LEVEL_SHIFT(l) (mmu.level_shift[l])
145 #define LEVEL_SIZE(l) (mmu.level_size[l])
146 #define LEVEL_OFFSET(l) (mmu.level_offset[l])
147 #define LEVEL_MASK(l) (mmu.level_mask[l])
148
149 /*
150 * Macros to:
151 * Check for a PFN above 4Gig and 64Gig for 32 bit PAE support
152 */
153 #define PFN_4G (4ull * (1024 * 1024 * 1024 / MMU_PAGESIZE))
154 #define PFN_64G (64ull * (1024 * 1024 * 1024 / MMU_PAGESIZE))
155 #define PFN_ABOVE4G(pfn) ((pfn) >= PFN_4G)
156 #define PFN_ABOVE64G(pfn) ((pfn) >= PFN_64G)
157
158 /*
159 * The CR3 register holds the physical address of the top level page table,
160 * along with the current PCID if any.
161 */
162 #define MAKECR3(pfn, pcid) (mmu_ptob(pfn) | pcid)
163
164 /*
165 * HAT/MMU parameters that depend on kernel mode and/or processor type
166 */
167 struct htable;
168 struct hat_mmu_info {
169 x86pte_t pt_nx; /* either 0 or PT_NX */
170 x86pte_t pt_global; /* either 0 or PT_GLOBAL */
171
172 pfn_t highest_pfn;
173
174 uint_t num_level; /* number of page table levels in use */
175 uint_t max_level; /* just num_level - 1 */
176 uint_t max_page_level; /* maximum level at which we can map a page */
177 uint_t umax_page_level; /* max user page map level */
178 uint_t ptes_per_table; /* # of entries in lower level page tables */
179 uint_t top_level_count; /* # of entries in top-level page table */
180 uint_t top_level_uslots; /* # of user slots in top-level page table */
181 uint_t num_copied_ents; /* # of PCP-copied PTEs to create */
182 /* 32-bit versions of values */
183 uint_t top_level_uslots32;
184 uint_t max_level32;
185 uint_t num_copied_ents32;
186
187 uint_t hash_cnt; /* cnt of entries in htable_hash_cache */
188 uint_t hat32_hash_cnt; /* cnt of entries in 32-bit htable_hash_cache */
189
190 uint_t pae_hat; /* either 0 or 1 */
191
192 uintptr_t hole_start; /* start of VA hole (or -1 if none) */
193 uintptr_t hole_end; /* end of VA hole (or 0 if none) */
194
195 struct htable **kmap_htables; /* htables for segmap + 32 bit heap */
196 x86pte_t *kmap_ptes; /* mapping of pagetables that map kmap */
197 uintptr_t kmap_addr; /* start addr of kmap */
198 uintptr_t kmap_eaddr; /* end addr of kmap */
199
200 uint_t pte_size; /* either 4 or 8 */
201 uint_t pte_size_shift; /* either 2 or 3 */
202 x86pte_t ptp_bits[MAX_NUM_LEVEL]; /* bits set for interior PTP */
203 x86pte_t pte_bits[MAX_NUM_LEVEL]; /* bits set for leaf PTE */
204
205 /*
206 * A range of VA used to window pages in the i86pc/vm code.
207 * See PWIN_XXX macros.
208 */
|