Print this page
8956 Implement KPTI
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/i86pc/sys/rm_platter.h
+++ new/usr/src/uts/i86pc/sys/rm_platter.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
|
↓ open down ↓ |
18 lines elided |
↑ open up ↑ |
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24 /*
25 25 * Copyright (c) 2010, Intel Corporation.
26 26 * All rights reserved.
27 27 */
28 28 /*
29 - * Copyright 2011 Joyent, Inc. All rights reserved.
29 + * Copyright 2018 Joyent, Inc.
30 30 */
31 31
32 32 #ifndef _SYS_RM_PLATTER_H
33 33 #define _SYS_RM_PLATTER_H
34 34
35 35 #include <sys/types.h>
36 36 #include <sys/tss.h>
37 37 #include <sys/segments.h>
38 38
39 39 #ifdef __cplusplus
40 40 extern "C" {
41 41 #endif
42 42
43 43 #define RM_PLATTER_CODE_SIZE 0x400
44 44 #define RM_PLATTER_CPU_HALT_CODE_SIZE 0x100
45 45
46 46 typedef struct rm_platter {
47 47 char rm_code[RM_PLATTER_CODE_SIZE];
48 48 char rm_cpu_halt_code[RM_PLATTER_CPU_HALT_CODE_SIZE];
49 49 #if defined(__amd64)
50 50 /*
51 51 * The compiler will want to 64-bit align the 64-bit rm_gdt_base
52 52 * pointer, so we need to add an extra four bytes of padding here to
53 53 * make sure rm_gdt_lim and rm_gdt_base will align to create a proper
54 54 * ten byte GDT pseudo-descriptor.
55 55 */
56 56 uint32_t rm_gdt_pad;
57 57 #endif /* __amd64 */
58 58 ushort_t rm_debug;
59 59 ushort_t rm_gdt_lim; /* stuff for lgdt */
60 60 user_desc_t *rm_gdt_base;
61 61 #if defined(__amd64)
62 62 /*
63 63 * The compiler will want to 64-bit align the 64-bit rm_idt_base
64 64 * pointer, so we need to add an extra four bytes of padding here to
65 65 * make sure rm_idt_lim and rm_idt_base will align to create a proper
66 66 * ten byte IDT pseudo-descriptor.
67 67 */
68 68 uint32_t rm_idt_pad;
69 69 #endif /* __amd64 */
70 70 ushort_t rm_cpu_halted; /* non-zero if CPU has been halted */
71 71 ushort_t rm_idt_lim; /* stuff for lidt */
72 72 gate_desc_t *rm_idt_base;
73 73 uint_t rm_pdbr; /* cr3 value */
74 74 uint_t rm_cpu; /* easy way to know which CPU we are */
75 75 uint_t rm_filler3;
76 76 uint_t rm_cr4; /* cr4 value on cpu0 */
77 77 #if defined(__amd64)
78 78 /*
79 79 * Temporary GDT for the brief transition from real mode to protected
80 80 * mode before a CPU continues on into long mode.
81 81 *
82 82 * Putting it here assures it will be located in identity mapped memory
83 83 * (va == pa, 1:1).
84 84 *
85 85 * rm_temp_gdt is sized to hold only a null descriptor in slot zero
86 86 * and a 64-bit code descriptor in slot one.
87 87 *
88 88 * rm_temp_[gi]dt_lim and rm_temp_[gi]dt_base are the pseudo-descriptors
89 89 * for the temporary GDT and IDT, respectively.
90 90 */
91 91 uint64_t rm_temp_gdt[2];
92 92 ushort_t rm_temp_gdtdesc_pad; /* filler to align GDT desc */
93 93 ushort_t rm_temp_gdt_lim;
94 94 uint32_t rm_temp_gdt_base;
95 95 ushort_t rm_temp_idtdesc_pad; /* filler to align IDT desc */
96 96 ushort_t rm_temp_idt_lim;
97 97 uint32_t rm_temp_idt_base;
98 98
99 99 /*
100 100 * The code executing in the rm_platter needs the offset into the
101 101 * platter at which the 64-bit code starts, so have mp_startup
102 102 * calculate it and store it here.
103 103 */
104 104 uint32_t rm_longmode64_addr;
105 105 #endif /* __amd64 */
|
↓ open down ↓ |
66 lines elided |
↑ open up ↑ |
106 106 } rm_platter_t;
107 107
108 108 /*
109 109 * cpu tables put within a single structure two of the tables which need to be
110 110 * allocated when a CPU starts up.
111 111 *
112 112 * Note: the tss should be 16 byte aligned for best performance on amd64
113 113 * Since DEFAULTSTKSIZE is a multiple of PAGESIZE tss will be aligned.
114 114 */
115 115 struct cpu_tables {
116 - char ct_stack[DEFAULTSTKSZ];
116 + /* IST stacks */
117 + char ct_stack1[DEFAULTSTKSZ]; /* dblfault */
118 +#if !defined(__xpv)
119 + char ct_stack2[DEFAULTSTKSZ]; /* nmi */
120 + char ct_stack3[DEFAULTSTKSZ]; /* mce */
121 +#endif
117 122 tss_t ct_tss;
118 123 };
119 124
120 125 /*
121 126 * gdt entries are 8 bytes long, ensure that we have an even no. of them.
122 127 */
123 128 #if ((NGDT / 2) * 2 != NGDT)
124 129 #error "rm_platter.h: tss not properly aligned"
125 130 #endif
126 131
127 132 #ifdef __cplusplus
128 133 }
129 134 #endif
130 135
131 136 #endif /* _SYS_RM_PLATTER_H */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX