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8956 Implement KPTI
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Robert Mustacchi <rm@joyent.com>
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--- old/usr/src/uts/i86pc/os/mp_startup.c
+++ new/usr/src/uts/i86pc/os/mp_startup.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
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20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 - * Copyright 2016 Joyent, Inc.
30 + * Copyright 2018 Joyent, Inc.
31 31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
32 32 */
33 33
34 34 #include <sys/types.h>
35 35 #include <sys/thread.h>
36 36 #include <sys/cpuvar.h>
37 37 #include <sys/cpu.h>
38 38 #include <sys/t_lock.h>
39 39 #include <sys/param.h>
40 40 #include <sys/proc.h>
41 41 #include <sys/disp.h>
42 42 #include <sys/class.h>
43 43 #include <sys/cmn_err.h>
44 44 #include <sys/debug.h>
45 45 #include <sys/note.h>
46 46 #include <sys/asm_linkage.h>
47 47 #include <sys/x_call.h>
48 48 #include <sys/systm.h>
49 49 #include <sys/var.h>
50 50 #include <sys/vtrace.h>
51 51 #include <vm/hat.h>
52 52 #include <vm/as.h>
53 53 #include <vm/seg_kmem.h>
54 54 #include <vm/seg_kp.h>
55 55 #include <sys/segments.h>
56 56 #include <sys/kmem.h>
57 57 #include <sys/stack.h>
58 58 #include <sys/smp_impldefs.h>
59 59 #include <sys/x86_archext.h>
60 60 #include <sys/machsystm.h>
61 61 #include <sys/traptrace.h>
62 62 #include <sys/clock.h>
63 63 #include <sys/cpc_impl.h>
64 64 #include <sys/pg.h>
65 65 #include <sys/cmt.h>
66 66 #include <sys/dtrace.h>
67 67 #include <sys/archsystm.h>
68 68 #include <sys/fp.h>
69 69 #include <sys/reboot.h>
70 70 #include <sys/kdi_machimpl.h>
71 71 #include <vm/hat_i86.h>
72 72 #include <vm/vm_dep.h>
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73 73 #include <sys/memnode.h>
74 74 #include <sys/pci_cfgspace.h>
75 75 #include <sys/mach_mmu.h>
76 76 #include <sys/sysmacros.h>
77 77 #if defined(__xpv)
78 78 #include <sys/hypervisor.h>
79 79 #endif
80 80 #include <sys/cpu_module.h>
81 81 #include <sys/ontrap.h>
82 82
83 -struct cpu cpus[1]; /* CPU data */
84 -struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */
85 -struct cpu *cpu_free_list; /* list for released CPUs */
86 -cpu_core_t cpu_core[NCPU]; /* cpu_core structures */
83 +struct cpu cpus[1] __aligned(MMU_PAGESIZE);
84 +struct cpu *cpu[NCPU] = {&cpus[0]};
85 +struct cpu *cpu_free_list;
86 +cpu_core_t cpu_core[NCPU];
87 87
88 88 #define cpu_next_free cpu_prev
89 89
90 90 /*
91 91 * Useful for disabling MP bring-up on a MP capable system.
92 92 */
93 93 int use_mp = 1;
94 94
95 95 /*
96 96 * to be set by a PSM to indicate what cpus
97 97 * are sitting around on the system.
98 98 */
99 99 cpuset_t mp_cpus;
100 100
101 101 /*
102 102 * This variable is used by the hat layer to decide whether or not
103 103 * critical sections are needed to prevent race conditions. For sun4m,
104 104 * this variable is set once enough MP initialization has been done in
105 105 * order to allow cross calls.
106 106 */
107 107 int flushes_require_xcalls;
108 108
109 109 cpuset_t cpu_ready_set; /* initialized in startup() */
110 110
111 111 static void mp_startup_boot(void);
112 112 static void mp_startup_hotplug(void);
113 113
114 114 static void cpu_sep_enable(void);
115 115 static void cpu_sep_disable(void);
116 116 static void cpu_asysc_enable(void);
117 117 static void cpu_asysc_disable(void);
118 118
119 119 /*
120 120 * Init CPU info - get CPU type info for processor_info system call.
121 121 */
122 122 void
123 123 init_cpu_info(struct cpu *cp)
124 124 {
125 125 processor_info_t *pi = &cp->cpu_type_info;
126 126
127 127 /*
128 128 * Get clock-frequency property for the CPU.
129 129 */
130 130 pi->pi_clock = cpu_freq;
131 131
132 132 /*
133 133 * Current frequency in Hz.
134 134 */
135 135 cp->cpu_curr_clock = cpu_freq_hz;
136 136
137 137 /*
138 138 * Supported frequencies.
139 139 */
140 140 if (cp->cpu_supp_freqs == NULL) {
141 141 cpu_set_supp_freqs(cp, NULL);
142 142 }
143 143
144 144 (void) strcpy(pi->pi_processor_type, "i386");
145 145 if (fpu_exists)
146 146 (void) strcpy(pi->pi_fputypes, "i387 compatible");
147 147
148 148 cp->cpu_idstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
149 149 cp->cpu_brandstr = kmem_zalloc(CPU_IDSTRLEN, KM_SLEEP);
150 150
151 151 /*
152 152 * If called for the BSP, cp is equal to current CPU.
153 153 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
154 154 * of current CPU as default values for cpu_idstr and cpu_brandstr.
155 155 * They will be corrected in mp_startup_common() after cpuid_pass1()
156 156 * has been invoked on target CPU.
157 157 */
158 158 (void) cpuid_getidstr(CPU, cp->cpu_idstr, CPU_IDSTRLEN);
159 159 (void) cpuid_getbrandstr(CPU, cp->cpu_brandstr, CPU_IDSTRLEN);
160 160 }
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161 161
162 162 /*
163 163 * Configure syscall support on this CPU.
164 164 */
165 165 /*ARGSUSED*/
166 166 void
167 167 init_cpu_syscall(struct cpu *cp)
168 168 {
169 169 kpreempt_disable();
170 170
171 -#if defined(__amd64)
172 171 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
173 172 is_x86_feature(x86_featureset, X86FSET_ASYSC)) {
174 173 uint64_t flags;
175 174
176 -#if !defined(__lint)
175 +#if !defined(__xpv)
177 176 /*
178 177 * The syscall instruction imposes a certain ordering on
179 178 * segment selectors, so we double-check that ordering
180 179 * here.
181 180 */
182 - ASSERT(KDS_SEL == KCS_SEL + 8);
183 - ASSERT(UDS_SEL == U32CS_SEL + 8);
184 - ASSERT(UCS_SEL == U32CS_SEL + 16);
181 + CTASSERT(KDS_SEL == KCS_SEL + 8);
182 + CTASSERT(UDS_SEL == U32CS_SEL + 8);
183 + CTASSERT(UCS_SEL == U32CS_SEL + 16);
185 184 #endif
185 +
186 186 /*
187 187 * Turn syscall/sysret extensions on.
188 188 */
189 189 cpu_asysc_enable();
190 190
191 191 /*
192 192 * Program the magic registers ..
193 193 */
194 194 wrmsr(MSR_AMD_STAR,
195 195 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32);
196 - wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall);
197 - wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32);
196 + if (kpti_enable == 1) {
197 + wrmsr(MSR_AMD_LSTAR,
198 + (uint64_t)(uintptr_t)tr_sys_syscall);
199 + wrmsr(MSR_AMD_CSTAR,
200 + (uint64_t)(uintptr_t)tr_sys_syscall32);
201 + } else {
202 + wrmsr(MSR_AMD_LSTAR,
203 + (uint64_t)(uintptr_t)sys_syscall);
204 + wrmsr(MSR_AMD_CSTAR,
205 + (uint64_t)(uintptr_t)sys_syscall32);
206 + }
198 207
199 208 /*
200 209 * This list of flags is masked off the incoming
201 210 * %rfl when we enter the kernel.
202 211 */
203 212 flags = PS_IE | PS_T;
204 213 if (is_x86_feature(x86_featureset, X86FSET_SMAP) == B_TRUE)
205 214 flags |= PS_ACHK;
206 215 wrmsr(MSR_AMD_SFMASK, flags);
207 216 }
208 -#endif
209 217
210 218 /*
211 - * On 32-bit kernels, we use sysenter/sysexit because it's too
212 - * hard to use syscall/sysret, and it is more portable anyway.
213 - *
214 219 * On 64-bit kernels on Nocona machines, the 32-bit syscall
215 220 * variant isn't available to 32-bit applications, but sysenter is.
216 221 */
217 222 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
218 223 is_x86_feature(x86_featureset, X86FSET_SEP)) {
219 224
220 -#if !defined(__lint)
225 +#if !defined(__xpv)
221 226 /*
222 227 * The sysenter instruction imposes a certain ordering on
223 228 * segment selectors, so we double-check that ordering
224 229 * here. See "sysenter" in Intel document 245471-012, "IA-32
225 230 * Intel Architecture Software Developer's Manual Volume 2:
226 231 * Instruction Set Reference"
227 232 */
228 - ASSERT(KDS_SEL == KCS_SEL + 8);
233 + CTASSERT(KDS_SEL == KCS_SEL + 8);
229 234
230 - ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3));
231 - ASSERT32(UDS_SEL == UCS_SEL + 8);
232 -
233 - ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3));
234 - ASSERT64(UDS_SEL == U32CS_SEL + 8);
235 + CTASSERT(U32CS_SEL == ((KCS_SEL + 16) | 3));
236 + CTASSERT(UDS_SEL == U32CS_SEL + 8);
235 237 #endif
236 238
237 239 cpu_sep_enable();
238 240
239 241 /*
240 242 * resume() sets this value to the base of the threads stack
241 243 * via a context handler.
242 244 */
243 245 wrmsr(MSR_INTC_SEP_ESP, 0);
244 - wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter);
246 +
247 + if (kpti_enable == 1) {
248 + wrmsr(MSR_INTC_SEP_EIP,
249 + (uint64_t)(uintptr_t)tr_sys_sysenter);
250 + } else {
251 + wrmsr(MSR_INTC_SEP_EIP,
252 + (uint64_t)(uintptr_t)sys_sysenter);
253 + }
245 254 }
246 255
247 256 kpreempt_enable();
248 257 }
249 258
250 259 #if !defined(__xpv)
251 260 /*
252 261 * Configure per-cpu ID GDT
253 262 */
254 263 static void
255 264 init_cpu_id_gdt(struct cpu *cp)
256 265 {
257 266 /* Write cpu_id into limit field of GDT for usermode retrieval */
258 267 #if defined(__amd64)
259 268 set_usegd(&cp->cpu_gdt[GDT_CPUID], SDP_SHORT, NULL, cp->cpu_id,
260 269 SDT_MEMRODA, SEL_UPL, SDP_BYTES, SDP_OP32);
261 270 #elif defined(__i386)
262 271 set_usegd(&cp->cpu_gdt[GDT_CPUID], NULL, cp->cpu_id, SDT_MEMRODA,
263 272 SEL_UPL, SDP_BYTES, SDP_OP32);
264 273 #endif
265 274 }
266 275 #endif /* !defined(__xpv) */
267 276
268 277 /*
269 278 * Multiprocessor initialization.
270 279 *
271 280 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
272 281 * startup and idle threads for the specified CPU.
273 282 * Parameter boot is true for boot time operations and is false for CPU
274 283 * DR operations.
275 284 */
276 285 static struct cpu *
277 286 mp_cpu_configure_common(int cpun, boolean_t boot)
278 287 {
279 288 struct cpu *cp;
280 289 kthread_id_t tp;
281 290 caddr_t sp;
282 291 proc_t *procp;
283 292 #if !defined(__xpv)
284 293 extern int idle_cpu_prefer_mwait;
285 294 extern void cpu_idle_mwait();
286 295 #endif
287 296 extern void idle();
288 297 extern void cpu_idle();
289 298
290 299 #ifdef TRAPTRACE
291 300 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun];
292 301 #endif
293 302
294 303 ASSERT(MUTEX_HELD(&cpu_lock));
295 304 ASSERT(cpun < NCPU && cpu[cpun] == NULL);
296 305
297 306 if (cpu_free_list == NULL) {
298 307 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP);
299 308 } else {
300 309 cp = cpu_free_list;
301 310 cpu_free_list = cp->cpu_next_free;
302 311 }
303 312
304 313 cp->cpu_m.mcpu_istamp = cpun << 16;
305 314
306 315 /* Create per CPU specific threads in the process p0. */
307 316 procp = &p0;
308 317
309 318 /*
310 319 * Initialize the dispatcher first.
311 320 */
312 321 disp_cpu_init(cp);
313 322
314 323 cpu_vm_data_init(cp);
315 324
316 325 /*
317 326 * Allocate and initialize the startup thread for this CPU.
318 327 * Interrupt and process switch stacks get allocated later
319 328 * when the CPU starts running.
320 329 */
321 330 tp = thread_create(NULL, 0, NULL, NULL, 0, procp,
322 331 TS_STOPPED, maxclsyspri);
323 332
324 333 /*
325 334 * Set state to TS_ONPROC since this thread will start running
326 335 * as soon as the CPU comes online.
327 336 *
328 337 * All the other fields of the thread structure are setup by
329 338 * thread_create().
330 339 */
331 340 THREAD_ONPROC(tp, cp);
332 341 tp->t_preempt = 1;
333 342 tp->t_bound_cpu = cp;
334 343 tp->t_affinitycnt = 1;
335 344 tp->t_cpu = cp;
336 345 tp->t_disp_queue = cp->cpu_disp;
337 346
338 347 /*
339 348 * Setup thread to start in mp_startup_common.
340 349 */
341 350 sp = tp->t_stk;
342 351 tp->t_sp = (uintptr_t)(sp - MINFRAME);
343 352 #if defined(__amd64)
344 353 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */
345 354 #endif
346 355 /*
347 356 * Setup thread start entry point for boot or hotplug.
348 357 */
349 358 if (boot) {
350 359 tp->t_pc = (uintptr_t)mp_startup_boot;
351 360 } else {
352 361 tp->t_pc = (uintptr_t)mp_startup_hotplug;
353 362 }
354 363
355 364 cp->cpu_id = cpun;
356 365 cp->cpu_self = cp;
357 366 cp->cpu_thread = tp;
358 367 cp->cpu_lwp = NULL;
359 368 cp->cpu_dispthread = tp;
360 369 cp->cpu_dispatch_pri = DISP_PRIO(tp);
361 370
362 371 /*
363 372 * cpu_base_spl must be set explicitly here to prevent any blocking
364 373 * operations in mp_startup_common from causing the spl of the cpu
365 374 * to drop to 0 (allowing device interrupts before we're ready) in
366 375 * resume().
367 376 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
368 377 * As an extra bit of security on DEBUG kernels, this is enforced with
369 378 * an assertion in mp_startup_common() -- before cpu_base_spl is set
370 379 * to its proper value.
371 380 */
372 381 cp->cpu_base_spl = ipltospl(LOCK_LEVEL);
373 382
374 383 /*
375 384 * Now, initialize per-CPU idle thread for this CPU.
376 385 */
377 386 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1);
378 387
379 388 cp->cpu_idle_thread = tp;
380 389
381 390 tp->t_preempt = 1;
382 391 tp->t_bound_cpu = cp;
383 392 tp->t_affinitycnt = 1;
384 393 tp->t_cpu = cp;
385 394 tp->t_disp_queue = cp->cpu_disp;
386 395
387 396 /*
388 397 * Bootstrap the CPU's PG data
389 398 */
390 399 pg_cpu_bootstrap(cp);
391 400
392 401 /*
393 402 * Perform CPC initialization on the new CPU.
394 403 */
395 404 kcpc_hw_init(cp);
396 405
397 406 /*
398 407 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
399 408 * for each CPU.
400 409 */
401 410 setup_vaddr_for_ppcopy(cp);
402 411
403 412 /*
404 413 * Allocate page for new GDT and initialize from current GDT.
405 414 */
406 415 #if !defined(__lint)
407 416 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE);
408 417 #endif
409 418 cp->cpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP);
410 419 bcopy(CPU->cpu_gdt, cp->cpu_gdt, (sizeof (*cp->cpu_gdt) * NGDT));
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411 420
412 421 #if defined(__i386)
413 422 /*
414 423 * setup kernel %gs.
415 424 */
416 425 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA,
417 426 SEL_KPL, 0, 1);
418 427 #endif
419 428
420 429 /*
421 - * If we have more than one node, each cpu gets a copy of IDT
422 - * local to its node. If this is a Pentium box, we use cpu 0's
423 - * IDT. cpu 0's IDT has been made read-only to workaround the
424 - * cmpxchgl register bug
430 + * Allocate pages for the CPU LDT.
425 431 */
426 - if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) {
432 + cp->cpu_m.mcpu_ldt = kmem_zalloc(LDT_CPU_SIZE, KM_SLEEP);
433 + cp->cpu_m.mcpu_ldt_len = 0;
434 +
435 + /*
436 + * Allocate a per-CPU IDT and initialize the new IDT to the currently
437 + * runing CPU.
438 + */
427 439 #if !defined(__lint)
428 - ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
440 + ASSERT((sizeof (*CPU->cpu_idt) * NIDT) <= PAGESIZE);
429 441 #endif
430 - cp->cpu_idt = kmem_zalloc(PAGESIZE, KM_SLEEP);
431 - bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
432 - } else {
433 - cp->cpu_idt = CPU->cpu_idt;
434 - }
442 + cp->cpu_idt = kmem_alloc(PAGESIZE, KM_SLEEP);
443 + bcopy(CPU->cpu_idt, cp->cpu_idt, PAGESIZE);
435 444
436 445 /*
437 446 * alloc space for cpuid info
438 447 */
439 448 cpuid_alloc_space(cp);
440 449 #if !defined(__xpv)
441 450 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) &&
442 451 idle_cpu_prefer_mwait) {
443 452 cp->cpu_m.mcpu_mwait = cpuid_mwait_alloc(cp);
444 453 cp->cpu_m.mcpu_idle_cpu = cpu_idle_mwait;
445 454 } else
446 455 #endif
447 456 cp->cpu_m.mcpu_idle_cpu = cpu_idle;
448 457
449 458 init_cpu_info(cp);
450 459
451 460 #if !defined(__xpv)
452 461 init_cpu_id_gdt(cp);
453 462 #endif
454 463
455 464 /*
456 465 * alloc space for ucode_info
457 466 */
458 467 ucode_alloc_space(cp);
459 468 xc_init_cpu(cp);
460 469 hat_cpu_online(cp);
461 470
462 471 #ifdef TRAPTRACE
463 472 /*
464 473 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
465 474 */
466 475 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP);
467 476 ttc->ttc_next = ttc->ttc_first;
468 477 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize;
469 478 #endif
470 479
471 480 /*
472 481 * Record that we have another CPU.
473 482 */
474 483 /*
475 484 * Initialize the interrupt threads for this CPU
476 485 */
477 486 cpu_intr_alloc(cp, NINTR_THREADS);
478 487
479 488 cp->cpu_flags = CPU_OFFLINE | CPU_QUIESCED | CPU_POWEROFF;
480 489 cpu_set_state(cp);
481 490
482 491 /*
483 492 * Add CPU to list of available CPUs. It'll be on the active list
484 493 * after mp_startup_common().
485 494 */
486 495 cpu_add_unit(cp);
487 496
488 497 return (cp);
489 498 }
490 499
491 500 /*
492 501 * Undo what was done in mp_cpu_configure_common
493 502 */
494 503 static void
495 504 mp_cpu_unconfigure_common(struct cpu *cp, int error)
496 505 {
497 506 ASSERT(MUTEX_HELD(&cpu_lock));
498 507
499 508 /*
500 509 * Remove the CPU from the list of available CPUs.
501 510 */
502 511 cpu_del_unit(cp->cpu_id);
503 512
504 513 if (error == ETIMEDOUT) {
505 514 /*
506 515 * The cpu was started, but never *seemed* to run any
507 516 * code in the kernel; it's probably off spinning in its
508 517 * own private world, though with potential references to
509 518 * our kmem-allocated IDTs and GDTs (for example).
510 519 *
511 520 * Worse still, it may actually wake up some time later,
512 521 * so rather than guess what it might or might not do, we
513 522 * leave the fundamental data structures intact.
514 523 */
515 524 cp->cpu_flags = 0;
516 525 return;
517 526 }
518 527
519 528 /*
520 529 * At this point, the only threads bound to this CPU should
521 530 * special per-cpu threads: it's idle thread, it's pause threads,
522 531 * and it's interrupt threads. Clean these up.
523 532 */
524 533 cpu_destroy_bound_threads(cp);
525 534 cp->cpu_idle_thread = NULL;
526 535
527 536 /*
528 537 * Free the interrupt stack.
529 538 */
530 539 segkp_release(segkp,
531 540 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME)));
532 541 cp->cpu_intr_stack = NULL;
533 542
534 543 #ifdef TRAPTRACE
535 544 /*
536 545 * Discard the trap trace buffer
537 546 */
538 547 {
539 548 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id];
540 549
541 550 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize);
542 551 ttc->ttc_first = NULL;
543 552 }
544 553 #endif
545 554
546 555 hat_cpu_offline(cp);
547 556
548 557 ucode_free_space(cp);
549 558
550 559 /* Free CPU ID string and brand string. */
551 560 if (cp->cpu_idstr) {
552 561 kmem_free(cp->cpu_idstr, CPU_IDSTRLEN);
553 562 cp->cpu_idstr = NULL;
554 563 }
555 564 if (cp->cpu_brandstr) {
556 565 kmem_free(cp->cpu_brandstr, CPU_IDSTRLEN);
557 566 cp->cpu_brandstr = NULL;
558 567 }
559 568
560 569 #if !defined(__xpv)
561 570 if (cp->cpu_m.mcpu_mwait != NULL) {
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562 571 cpuid_mwait_free(cp);
563 572 cp->cpu_m.mcpu_mwait = NULL;
564 573 }
565 574 #endif
566 575 cpuid_free_space(cp);
567 576
568 577 if (cp->cpu_idt != CPU->cpu_idt)
569 578 kmem_free(cp->cpu_idt, PAGESIZE);
570 579 cp->cpu_idt = NULL;
571 580
581 + kmem_free(cp->cpu_m.mcpu_ldt, LDT_CPU_SIZE);
582 + cp->cpu_m.mcpu_ldt = NULL;
583 + cp->cpu_m.mcpu_ldt_len = 0;
584 +
572 585 kmem_free(cp->cpu_gdt, PAGESIZE);
573 586 cp->cpu_gdt = NULL;
574 587
575 588 if (cp->cpu_supp_freqs != NULL) {
576 589 size_t len = strlen(cp->cpu_supp_freqs) + 1;
577 590 kmem_free(cp->cpu_supp_freqs, len);
578 591 cp->cpu_supp_freqs = NULL;
579 592 }
580 593
581 594 teardown_vaddr_for_ppcopy(cp);
582 595
583 596 kcpc_hw_fini(cp);
584 597
585 598 cp->cpu_dispthread = NULL;
586 599 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */
587 600
588 601 cpu_vm_data_destroy(cp);
589 602
590 603 xc_fini_cpu(cp);
591 604 disp_cpu_fini(cp);
592 605
593 606 ASSERT(cp != CPU0);
594 607 bzero(cp, sizeof (*cp));
595 608 cp->cpu_next_free = cpu_free_list;
596 609 cpu_free_list = cp;
597 610 }
598 611
599 612 /*
600 613 * Apply workarounds for known errata, and warn about those that are absent.
601 614 *
602 615 * System vendors occasionally create configurations which contain different
603 616 * revisions of the CPUs that are almost but not exactly the same. At the
604 617 * time of writing, this meant that their clock rates were the same, their
605 618 * feature sets were the same, but the required workaround were -not-
606 619 * necessarily the same. So, this routine is invoked on -every- CPU soon
607 620 * after starting to make sure that the resulting system contains the most
608 621 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
609 622 * system.
610 623 *
611 624 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
612 625 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
613 626 * prior to acknowledging their readiness to the master, so this routine will
614 627 * never be executed by multiple CPUs in parallel, thus making updates to
615 628 * global data safe.
616 629 *
617 630 * These workarounds are based on Rev 3.57 of the Revision Guide for
618 631 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
619 632 */
620 633
621 634 #if defined(OPTERON_ERRATUM_88)
622 635 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */
623 636 #endif
624 637
625 638 #if defined(OPTERON_ERRATUM_91)
626 639 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */
627 640 #endif
628 641
629 642 #if defined(OPTERON_ERRATUM_93)
630 643 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */
631 644 #endif
632 645
633 646 #if defined(OPTERON_ERRATUM_95)
634 647 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */
635 648 #endif
636 649
637 650 #if defined(OPTERON_ERRATUM_100)
638 651 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */
639 652 #endif
640 653
641 654 #if defined(OPTERON_ERRATUM_108)
642 655 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */
643 656 #endif
644 657
645 658 #if defined(OPTERON_ERRATUM_109)
646 659 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */
647 660 #endif
648 661
649 662 #if defined(OPTERON_ERRATUM_121)
650 663 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */
651 664 #endif
652 665
653 666 #if defined(OPTERON_ERRATUM_122)
654 667 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */
655 668 #endif
656 669
657 670 #if defined(OPTERON_ERRATUM_123)
658 671 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */
659 672 #endif
660 673
661 674 #if defined(OPTERON_ERRATUM_131)
662 675 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */
663 676 #endif
664 677
665 678 #if defined(OPTERON_WORKAROUND_6336786)
666 679 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */
667 680 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */
668 681 #endif
669 682
670 683 #if defined(OPTERON_WORKAROUND_6323525)
671 684 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */
672 685 #endif
673 686
674 687 #if defined(OPTERON_ERRATUM_298)
675 688 int opteron_erratum_298;
676 689 #endif
677 690
678 691 #if defined(OPTERON_ERRATUM_721)
679 692 int opteron_erratum_721;
680 693 #endif
681 694
682 695 static void
683 696 workaround_warning(cpu_t *cp, uint_t erratum)
684 697 {
685 698 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u",
686 699 cp->cpu_id, erratum);
687 700 }
688 701
689 702 static void
690 703 workaround_applied(uint_t erratum)
691 704 {
692 705 if (erratum > 1000000)
693 706 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n",
694 707 erratum);
695 708 else
696 709 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n",
697 710 erratum);
698 711 }
699 712
700 713 static void
701 714 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error)
702 715 {
703 716 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d",
704 717 cp->cpu_id, rw, msr, error);
705 718 }
706 719
707 720 /*
708 721 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
709 722 * system.
710 723 */
711 724 static uint_t
712 725 opteron_get_nnodes(void)
713 726 {
714 727 static uint_t nnodes = 0;
715 728
716 729 if (nnodes == 0) {
717 730 #ifdef DEBUG
718 731 uint_t family;
719 732
720 733 /*
721 734 * This routine uses a PCI config space based mechanism
722 735 * for retrieving the number of nodes in the system.
723 736 * Device 24, function 0, offset 0x60 as used here is not
724 737 * AMD processor architectural, and may not work on processor
725 738 * families other than those listed below.
726 739 *
727 740 * Callers of this routine must ensure that we're running on
728 741 * a processor which supports this mechanism.
729 742 * The assertion below is meant to catch calls on unsupported
730 743 * processors.
731 744 */
732 745 family = cpuid_getfamily(CPU);
733 746 ASSERT(family == 0xf || family == 0x10 || family == 0x11);
734 747 #endif /* DEBUG */
735 748
736 749 /*
737 750 * Obtain the number of nodes in the system from
738 751 * bits [6:4] of the Node ID register on node 0.
739 752 *
740 753 * The actual node count is NodeID[6:4] + 1
741 754 *
742 755 * The Node ID register is accessed via function 0,
743 756 * offset 0x60. Node 0 is device 24.
744 757 */
745 758 nnodes = ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
746 759 }
747 760 return (nnodes);
748 761 }
749 762
750 763 uint_t
751 764 do_erratum_298(struct cpu *cpu)
752 765 {
753 766 static int osvwrc = -3;
754 767 extern int osvw_opteron_erratum(cpu_t *, uint_t);
755 768
756 769 /*
757 770 * L2 Eviction May Occur During Processor Operation To Set
758 771 * Accessed or Dirty Bit.
759 772 */
760 773 if (osvwrc == -3) {
761 774 osvwrc = osvw_opteron_erratum(cpu, 298);
762 775 } else {
763 776 /* osvw return codes should be consistent for all cpus */
764 777 ASSERT(osvwrc == osvw_opteron_erratum(cpu, 298));
765 778 }
766 779
767 780 switch (osvwrc) {
768 781 case 0: /* erratum is not present: do nothing */
769 782 break;
770 783 case 1: /* erratum is present: BIOS workaround applied */
771 784 /*
772 785 * check if workaround is actually in place and issue warning
773 786 * if not.
774 787 */
775 788 if (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
776 789 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0)) {
777 790 #if defined(OPTERON_ERRATUM_298)
778 791 opteron_erratum_298++;
779 792 #else
780 793 workaround_warning(cpu, 298);
781 794 return (1);
782 795 #endif
783 796 }
784 797 break;
785 798 case -1: /* cannot determine via osvw: check cpuid */
786 799 if ((cpuid_opteron_erratum(cpu, 298) > 0) &&
787 800 (((rdmsr(MSR_AMD_HWCR) & AMD_HWCR_TLBCACHEDIS) == 0) ||
788 801 ((rdmsr(MSR_AMD_BU_CFG) & AMD_BU_CFG_E298) == 0))) {
789 802 #if defined(OPTERON_ERRATUM_298)
790 803 opteron_erratum_298++;
791 804 #else
792 805 workaround_warning(cpu, 298);
793 806 return (1);
794 807 #endif
795 808 }
796 809 break;
797 810 }
798 811 return (0);
799 812 }
800 813
801 814 uint_t
802 815 workaround_errata(struct cpu *cpu)
803 816 {
804 817 uint_t missing = 0;
805 818
806 819 ASSERT(cpu == CPU);
807 820
808 821 /*LINTED*/
809 822 if (cpuid_opteron_erratum(cpu, 88) > 0) {
810 823 /*
811 824 * SWAPGS May Fail To Read Correct GS Base
812 825 */
813 826 #if defined(OPTERON_ERRATUM_88)
814 827 /*
815 828 * The workaround is an mfence in the relevant assembler code
816 829 */
817 830 opteron_erratum_88++;
818 831 #else
819 832 workaround_warning(cpu, 88);
820 833 missing++;
821 834 #endif
822 835 }
823 836
824 837 if (cpuid_opteron_erratum(cpu, 91) > 0) {
825 838 /*
826 839 * Software Prefetches May Report A Page Fault
827 840 */
828 841 #if defined(OPTERON_ERRATUM_91)
829 842 /*
830 843 * fix is in trap.c
831 844 */
832 845 opteron_erratum_91++;
833 846 #else
834 847 workaround_warning(cpu, 91);
835 848 missing++;
836 849 #endif
837 850 }
838 851
839 852 if (cpuid_opteron_erratum(cpu, 93) > 0) {
840 853 /*
841 854 * RSM Auto-Halt Restart Returns to Incorrect RIP
842 855 */
843 856 #if defined(OPTERON_ERRATUM_93)
844 857 /*
845 858 * fix is in trap.c
846 859 */
847 860 opteron_erratum_93++;
848 861 #else
849 862 workaround_warning(cpu, 93);
850 863 missing++;
851 864 #endif
852 865 }
853 866
854 867 /*LINTED*/
855 868 if (cpuid_opteron_erratum(cpu, 95) > 0) {
856 869 /*
857 870 * RET Instruction May Return to Incorrect EIP
858 871 */
859 872 #if defined(OPTERON_ERRATUM_95)
860 873 #if defined(_LP64)
861 874 /*
862 875 * Workaround this by ensuring that 32-bit user code and
863 876 * 64-bit kernel code never occupy the same address
864 877 * range mod 4G.
865 878 */
866 879 if (_userlimit32 > 0xc0000000ul)
867 880 *(uintptr_t *)&_userlimit32 = 0xc0000000ul;
868 881
869 882 /*LINTED*/
870 883 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u);
871 884 opteron_erratum_95++;
872 885 #endif /* _LP64 */
873 886 #else
874 887 workaround_warning(cpu, 95);
875 888 missing++;
876 889 #endif
877 890 }
878 891
879 892 if (cpuid_opteron_erratum(cpu, 100) > 0) {
880 893 /*
881 894 * Compatibility Mode Branches Transfer to Illegal Address
882 895 */
883 896 #if defined(OPTERON_ERRATUM_100)
884 897 /*
885 898 * fix is in trap.c
886 899 */
887 900 opteron_erratum_100++;
888 901 #else
889 902 workaround_warning(cpu, 100);
890 903 missing++;
891 904 #endif
892 905 }
893 906
894 907 /*LINTED*/
895 908 if (cpuid_opteron_erratum(cpu, 108) > 0) {
896 909 /*
897 910 * CPUID Instruction May Return Incorrect Model Number In
898 911 * Some Processors
899 912 */
900 913 #if defined(OPTERON_ERRATUM_108)
901 914 /*
902 915 * (Our cpuid-handling code corrects the model number on
903 916 * those processors)
904 917 */
905 918 #else
906 919 workaround_warning(cpu, 108);
907 920 missing++;
908 921 #endif
909 922 }
910 923
911 924 /*LINTED*/
912 925 if (cpuid_opteron_erratum(cpu, 109) > 0) do {
913 926 /*
914 927 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
915 928 */
916 929 #if defined(OPTERON_ERRATUM_109)
917 930 /*
918 931 * The "workaround" is to print a warning to upgrade the BIOS
919 932 */
920 933 uint64_t value;
921 934 const uint_t msr = MSR_AMD_PATCHLEVEL;
922 935 int err;
923 936
924 937 if ((err = checked_rdmsr(msr, &value)) != 0) {
925 938 msr_warning(cpu, "rd", msr, err);
926 939 workaround_warning(cpu, 109);
927 940 missing++;
928 941 }
929 942 if (value == 0)
930 943 opteron_erratum_109++;
931 944 #else
932 945 workaround_warning(cpu, 109);
933 946 missing++;
934 947 #endif
935 948 /*CONSTANTCONDITION*/
936 949 } while (0);
937 950
938 951 /*LINTED*/
939 952 if (cpuid_opteron_erratum(cpu, 121) > 0) {
940 953 /*
941 954 * Sequential Execution Across Non_Canonical Boundary Caused
942 955 * Processor Hang
943 956 */
944 957 #if defined(OPTERON_ERRATUM_121)
945 958 #if defined(_LP64)
946 959 /*
947 960 * Erratum 121 is only present in long (64 bit) mode.
948 961 * Workaround is to include the page immediately before the
949 962 * va hole to eliminate the possibility of system hangs due to
950 963 * sequential execution across the va hole boundary.
951 964 */
952 965 if (opteron_erratum_121)
953 966 opteron_erratum_121++;
954 967 else {
955 968 if (hole_start) {
956 969 hole_start -= PAGESIZE;
957 970 } else {
958 971 /*
959 972 * hole_start not yet initialized by
960 973 * mmu_init. Initialize hole_start
961 974 * with value to be subtracted.
962 975 */
963 976 hole_start = PAGESIZE;
964 977 }
965 978 opteron_erratum_121++;
966 979 }
967 980 #endif /* _LP64 */
968 981 #else
969 982 workaround_warning(cpu, 121);
970 983 missing++;
971 984 #endif
972 985 }
973 986
974 987 /*LINTED*/
975 988 if (cpuid_opteron_erratum(cpu, 122) > 0) do {
976 989 /*
977 990 * TLB Flush Filter May Cause Coherency Problem in
978 991 * Multiprocessor Systems
979 992 */
980 993 #if defined(OPTERON_ERRATUM_122)
981 994 uint64_t value;
982 995 const uint_t msr = MSR_AMD_HWCR;
983 996 int error;
984 997
985 998 /*
986 999 * Erratum 122 is only present in MP configurations (multi-core
987 1000 * or multi-processor).
988 1001 */
989 1002 #if defined(__xpv)
990 1003 if (!DOMAIN_IS_INITDOMAIN(xen_info))
991 1004 break;
992 1005 if (!opteron_erratum_122 && xpv_nr_phys_cpus() == 1)
993 1006 break;
994 1007 #else
995 1008 if (!opteron_erratum_122 && opteron_get_nnodes() == 1 &&
996 1009 cpuid_get_ncpu_per_chip(cpu) == 1)
997 1010 break;
998 1011 #endif
999 1012 /* disable TLB Flush Filter */
1000 1013
1001 1014 if ((error = checked_rdmsr(msr, &value)) != 0) {
1002 1015 msr_warning(cpu, "rd", msr, error);
1003 1016 workaround_warning(cpu, 122);
1004 1017 missing++;
1005 1018 } else {
1006 1019 value |= (uint64_t)AMD_HWCR_FFDIS;
1007 1020 if ((error = checked_wrmsr(msr, value)) != 0) {
1008 1021 msr_warning(cpu, "wr", msr, error);
1009 1022 workaround_warning(cpu, 122);
1010 1023 missing++;
1011 1024 }
1012 1025 }
1013 1026 opteron_erratum_122++;
1014 1027 #else
1015 1028 workaround_warning(cpu, 122);
1016 1029 missing++;
1017 1030 #endif
1018 1031 /*CONSTANTCONDITION*/
1019 1032 } while (0);
1020 1033
1021 1034 /*LINTED*/
1022 1035 if (cpuid_opteron_erratum(cpu, 123) > 0) do {
1023 1036 /*
1024 1037 * Bypassed Reads May Cause Data Corruption of System Hang in
1025 1038 * Dual Core Processors
1026 1039 */
1027 1040 #if defined(OPTERON_ERRATUM_123)
1028 1041 uint64_t value;
1029 1042 const uint_t msr = MSR_AMD_PATCHLEVEL;
1030 1043 int err;
1031 1044
1032 1045 /*
1033 1046 * Erratum 123 applies only to multi-core cpus.
1034 1047 */
1035 1048 if (cpuid_get_ncpu_per_chip(cpu) < 2)
1036 1049 break;
1037 1050 #if defined(__xpv)
1038 1051 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1039 1052 break;
1040 1053 #endif
1041 1054 /*
1042 1055 * The "workaround" is to print a warning to upgrade the BIOS
1043 1056 */
1044 1057 if ((err = checked_rdmsr(msr, &value)) != 0) {
1045 1058 msr_warning(cpu, "rd", msr, err);
1046 1059 workaround_warning(cpu, 123);
1047 1060 missing++;
1048 1061 }
1049 1062 if (value == 0)
1050 1063 opteron_erratum_123++;
1051 1064 #else
1052 1065 workaround_warning(cpu, 123);
1053 1066 missing++;
1054 1067
1055 1068 #endif
1056 1069 /*CONSTANTCONDITION*/
1057 1070 } while (0);
1058 1071
1059 1072 /*LINTED*/
1060 1073 if (cpuid_opteron_erratum(cpu, 131) > 0) do {
1061 1074 /*
1062 1075 * Multiprocessor Systems with Four or More Cores May Deadlock
1063 1076 * Waiting for a Probe Response
1064 1077 */
1065 1078 #if defined(OPTERON_ERRATUM_131)
1066 1079 uint64_t nbcfg;
1067 1080 const uint_t msr = MSR_AMD_NB_CFG;
1068 1081 const uint64_t wabits =
1069 1082 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR;
1070 1083 int error;
1071 1084
1072 1085 /*
1073 1086 * Erratum 131 applies to any system with four or more cores.
1074 1087 */
1075 1088 if (opteron_erratum_131)
1076 1089 break;
1077 1090 #if defined(__xpv)
1078 1091 if (!DOMAIN_IS_INITDOMAIN(xen_info))
1079 1092 break;
1080 1093 if (xpv_nr_phys_cpus() < 4)
1081 1094 break;
1082 1095 #else
1083 1096 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu) < 4)
1084 1097 break;
1085 1098 #endif
1086 1099 /*
1087 1100 * Print a warning if neither of the workarounds for
1088 1101 * erratum 131 is present.
1089 1102 */
1090 1103 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) {
1091 1104 msr_warning(cpu, "rd", msr, error);
1092 1105 workaround_warning(cpu, 131);
1093 1106 missing++;
1094 1107 } else if ((nbcfg & wabits) == 0) {
1095 1108 opteron_erratum_131++;
1096 1109 } else {
1097 1110 /* cannot have both workarounds set */
1098 1111 ASSERT((nbcfg & wabits) != wabits);
1099 1112 }
1100 1113 #else
1101 1114 workaround_warning(cpu, 131);
1102 1115 missing++;
1103 1116 #endif
1104 1117 /*CONSTANTCONDITION*/
1105 1118 } while (0);
1106 1119
1107 1120 /*
1108 1121 * This isn't really an erratum, but for convenience the
1109 1122 * detection/workaround code lives here and in cpuid_opteron_erratum.
1110 1123 */
1111 1124 if (cpuid_opteron_erratum(cpu, 6336786) > 0) {
1112 1125 #if defined(OPTERON_WORKAROUND_6336786)
1113 1126 /*
1114 1127 * Disable C1-Clock ramping on multi-core/multi-processor
1115 1128 * K8 platforms to guard against TSC drift.
1116 1129 */
1117 1130 if (opteron_workaround_6336786) {
1118 1131 opteron_workaround_6336786++;
1119 1132 #if defined(__xpv)
1120 1133 } else if ((DOMAIN_IS_INITDOMAIN(xen_info) &&
1121 1134 xpv_nr_phys_cpus() > 1) ||
1122 1135 opteron_workaround_6336786_UP) {
1123 1136 /*
1124 1137 * XXPV Hmm. We can't walk the Northbridges on
1125 1138 * the hypervisor; so just complain and drive
1126 1139 * on. This probably needs to be fixed in
1127 1140 * the hypervisor itself.
1128 1141 */
1129 1142 opteron_workaround_6336786++;
1130 1143 workaround_warning(cpu, 6336786);
1131 1144 #else /* __xpv */
1132 1145 } else if ((opteron_get_nnodes() *
1133 1146 cpuid_get_ncpu_per_chip(cpu) > 1) ||
1134 1147 opteron_workaround_6336786_UP) {
1135 1148
1136 1149 uint_t node, nnodes;
1137 1150 uint8_t data;
1138 1151
1139 1152 nnodes = opteron_get_nnodes();
1140 1153 for (node = 0; node < nnodes; node++) {
1141 1154 /*
1142 1155 * Clear PMM7[1:0] (function 3, offset 0x87)
1143 1156 * Northbridge device is the node id + 24.
1144 1157 */
1145 1158 data = pci_getb_func(0, node + 24, 3, 0x87);
1146 1159 data &= 0xFC;
1147 1160 pci_putb_func(0, node + 24, 3, 0x87, data);
1148 1161 }
1149 1162 opteron_workaround_6336786++;
1150 1163 #endif /* __xpv */
1151 1164 }
1152 1165 #else
1153 1166 workaround_warning(cpu, 6336786);
1154 1167 missing++;
1155 1168 #endif
1156 1169 }
1157 1170
1158 1171 /*LINTED*/
1159 1172 /*
1160 1173 * Mutex primitives don't work as expected.
1161 1174 */
1162 1175 if (cpuid_opteron_erratum(cpu, 6323525) > 0) {
1163 1176 #if defined(OPTERON_WORKAROUND_6323525)
1164 1177 /*
1165 1178 * This problem only occurs with 2 or more cores. If bit in
1166 1179 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1167 1180 * is to patch the semaphone routines with the lfence
1168 1181 * instruction to provide necessary load memory barrier with
1169 1182 * possible subsequent read-modify-write ops.
1170 1183 *
1171 1184 * It is too early in boot to call the patch routine so
1172 1185 * set erratum variable to be done in startup_end().
1173 1186 */
1174 1187 if (opteron_workaround_6323525) {
1175 1188 opteron_workaround_6323525++;
1176 1189 #if defined(__xpv)
1177 1190 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2)) {
1178 1191 if (DOMAIN_IS_INITDOMAIN(xen_info)) {
1179 1192 /*
1180 1193 * XXPV Use dom0_msr here when extended
1181 1194 * operations are supported?
1182 1195 */
1183 1196 if (xpv_nr_phys_cpus() > 1)
1184 1197 opteron_workaround_6323525++;
1185 1198 } else {
1186 1199 /*
1187 1200 * We have no way to tell how many physical
1188 1201 * cpus there are, or even if this processor
1189 1202 * has the problem, so enable the workaround
1190 1203 * unconditionally (at some performance cost).
1191 1204 */
1192 1205 opteron_workaround_6323525++;
1193 1206 }
1194 1207 #else /* __xpv */
1195 1208 } else if (is_x86_feature(x86_featureset, X86FSET_SSE2) &&
1196 1209 ((opteron_get_nnodes() *
1197 1210 cpuid_get_ncpu_per_chip(cpu)) > 1)) {
1198 1211 if ((xrdmsr(MSR_AMD_BU_CFG) & (UINT64_C(1) << 33)) == 0)
1199 1212 opteron_workaround_6323525++;
1200 1213 #endif /* __xpv */
1201 1214 }
1202 1215 #else
1203 1216 workaround_warning(cpu, 6323525);
1204 1217 missing++;
1205 1218 #endif
1206 1219 }
1207 1220
1208 1221 missing += do_erratum_298(cpu);
1209 1222
1210 1223 if (cpuid_opteron_erratum(cpu, 721) > 0) {
1211 1224 #if defined(OPTERON_ERRATUM_721)
1212 1225 on_trap_data_t otd;
1213 1226
1214 1227 if (!on_trap(&otd, OT_DATA_ACCESS))
1215 1228 wrmsr(MSR_AMD_DE_CFG,
1216 1229 rdmsr(MSR_AMD_DE_CFG) | AMD_DE_CFG_E721);
1217 1230 no_trap();
1218 1231
1219 1232 opteron_erratum_721++;
1220 1233 #else
1221 1234 workaround_warning(cpu, 721);
1222 1235 missing++;
1223 1236 #endif
1224 1237 }
1225 1238
1226 1239 #ifdef __xpv
1227 1240 return (0);
1228 1241 #else
1229 1242 return (missing);
1230 1243 #endif
1231 1244 }
1232 1245
1233 1246 void
1234 1247 workaround_errata_end()
1235 1248 {
1236 1249 #if defined(OPTERON_ERRATUM_88)
1237 1250 if (opteron_erratum_88)
1238 1251 workaround_applied(88);
1239 1252 #endif
1240 1253 #if defined(OPTERON_ERRATUM_91)
1241 1254 if (opteron_erratum_91)
1242 1255 workaround_applied(91);
1243 1256 #endif
1244 1257 #if defined(OPTERON_ERRATUM_93)
1245 1258 if (opteron_erratum_93)
1246 1259 workaround_applied(93);
1247 1260 #endif
1248 1261 #if defined(OPTERON_ERRATUM_95)
1249 1262 if (opteron_erratum_95)
1250 1263 workaround_applied(95);
1251 1264 #endif
1252 1265 #if defined(OPTERON_ERRATUM_100)
1253 1266 if (opteron_erratum_100)
1254 1267 workaround_applied(100);
1255 1268 #endif
1256 1269 #if defined(OPTERON_ERRATUM_108)
1257 1270 if (opteron_erratum_108)
1258 1271 workaround_applied(108);
1259 1272 #endif
1260 1273 #if defined(OPTERON_ERRATUM_109)
1261 1274 if (opteron_erratum_109) {
1262 1275 cmn_err(CE_WARN,
1263 1276 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1264 1277 " processor\nerratum 109 was not detected; updating your"
1265 1278 " system's BIOS to a version\ncontaining this"
1266 1279 " microcode patch is HIGHLY recommended or erroneous"
1267 1280 " system\noperation may occur.\n");
1268 1281 }
1269 1282 #endif
1270 1283 #if defined(OPTERON_ERRATUM_121)
1271 1284 if (opteron_erratum_121)
1272 1285 workaround_applied(121);
1273 1286 #endif
1274 1287 #if defined(OPTERON_ERRATUM_122)
1275 1288 if (opteron_erratum_122)
1276 1289 workaround_applied(122);
1277 1290 #endif
1278 1291 #if defined(OPTERON_ERRATUM_123)
1279 1292 if (opteron_erratum_123) {
1280 1293 cmn_err(CE_WARN,
1281 1294 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1282 1295 " processor\nerratum 123 was not detected; updating your"
1283 1296 " system's BIOS to a version\ncontaining this"
1284 1297 " microcode patch is HIGHLY recommended or erroneous"
1285 1298 " system\noperation may occur.\n");
1286 1299 }
1287 1300 #endif
1288 1301 #if defined(OPTERON_ERRATUM_131)
1289 1302 if (opteron_erratum_131) {
1290 1303 cmn_err(CE_WARN,
1291 1304 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1292 1305 " processor\nerratum 131 was not detected; updating your"
1293 1306 " system's BIOS to a version\ncontaining this"
1294 1307 " microcode patch is HIGHLY recommended or erroneous"
1295 1308 " system\noperation may occur.\n");
1296 1309 }
1297 1310 #endif
1298 1311 #if defined(OPTERON_WORKAROUND_6336786)
1299 1312 if (opteron_workaround_6336786)
1300 1313 workaround_applied(6336786);
1301 1314 #endif
1302 1315 #if defined(OPTERON_WORKAROUND_6323525)
1303 1316 if (opteron_workaround_6323525)
1304 1317 workaround_applied(6323525);
1305 1318 #endif
1306 1319 #if defined(OPTERON_ERRATUM_298)
1307 1320 if (opteron_erratum_298) {
1308 1321 cmn_err(CE_WARN,
1309 1322 "BIOS microcode patch for AMD 64/Opteron(tm)"
1310 1323 " processor\nerratum 298 was not detected; updating your"
1311 1324 " system's BIOS to a version\ncontaining this"
1312 1325 " microcode patch is HIGHLY recommended or erroneous"
1313 1326 " system\noperation may occur.\n");
1314 1327 }
1315 1328 #endif
1316 1329 #if defined(OPTERON_ERRATUM_721)
1317 1330 if (opteron_erratum_721)
1318 1331 workaround_applied(721);
1319 1332 #endif
1320 1333 }
1321 1334
1322 1335 /*
1323 1336 * The procset_slave and procset_master are used to synchronize
1324 1337 * between the control CPU and the target CPU when starting CPUs.
1325 1338 */
1326 1339 static cpuset_t procset_slave, procset_master;
1327 1340
1328 1341 static void
1329 1342 mp_startup_wait(cpuset_t *sp, processorid_t cpuid)
1330 1343 {
1331 1344 cpuset_t tempset;
1332 1345
1333 1346 for (tempset = *sp; !CPU_IN_SET(tempset, cpuid);
1334 1347 tempset = *(volatile cpuset_t *)sp) {
1335 1348 SMT_PAUSE();
1336 1349 }
1337 1350 CPUSET_ATOMIC_DEL(*(cpuset_t *)sp, cpuid);
1338 1351 }
1339 1352
1340 1353 static void
1341 1354 mp_startup_signal(cpuset_t *sp, processorid_t cpuid)
1342 1355 {
1343 1356 cpuset_t tempset;
1344 1357
1345 1358 CPUSET_ATOMIC_ADD(*(cpuset_t *)sp, cpuid);
1346 1359 for (tempset = *sp; CPU_IN_SET(tempset, cpuid);
1347 1360 tempset = *(volatile cpuset_t *)sp) {
1348 1361 SMT_PAUSE();
1349 1362 }
1350 1363 }
1351 1364
1352 1365 int
1353 1366 mp_start_cpu_common(cpu_t *cp, boolean_t boot)
1354 1367 {
1355 1368 _NOTE(ARGUNUSED(boot));
1356 1369
1357 1370 void *ctx;
1358 1371 int delays;
1359 1372 int error = 0;
1360 1373 cpuset_t tempset;
1361 1374 processorid_t cpuid;
1362 1375 #ifndef __xpv
1363 1376 extern void cpupm_init(cpu_t *);
1364 1377 #endif
1365 1378
1366 1379 ASSERT(cp != NULL);
1367 1380 cpuid = cp->cpu_id;
1368 1381 ctx = mach_cpucontext_alloc(cp);
1369 1382 if (ctx == NULL) {
1370 1383 cmn_err(CE_WARN,
1371 1384 "cpu%d: failed to allocate context", cp->cpu_id);
1372 1385 return (EAGAIN);
1373 1386 }
1374 1387 error = mach_cpu_start(cp, ctx);
1375 1388 if (error != 0) {
1376 1389 cmn_err(CE_WARN,
1377 1390 "cpu%d: failed to start, error %d", cp->cpu_id, error);
1378 1391 mach_cpucontext_free(cp, ctx, error);
1379 1392 return (error);
1380 1393 }
1381 1394
1382 1395 for (delays = 0, tempset = procset_slave; !CPU_IN_SET(tempset, cpuid);
1383 1396 delays++) {
1384 1397 if (delays == 500) {
1385 1398 /*
1386 1399 * After five seconds, things are probably looking
1387 1400 * a bit bleak - explain the hang.
1388 1401 */
1389 1402 cmn_err(CE_NOTE, "cpu%d: started, "
1390 1403 "but not running in the kernel yet", cpuid);
1391 1404 } else if (delays > 2000) {
1392 1405 /*
1393 1406 * We waited at least 20 seconds, bail ..
1394 1407 */
1395 1408 error = ETIMEDOUT;
1396 1409 cmn_err(CE_WARN, "cpu%d: timed out", cpuid);
1397 1410 mach_cpucontext_free(cp, ctx, error);
1398 1411 return (error);
1399 1412 }
1400 1413
1401 1414 /*
1402 1415 * wait at least 10ms, then check again..
1403 1416 */
1404 1417 delay(USEC_TO_TICK_ROUNDUP(10000));
1405 1418 tempset = *((volatile cpuset_t *)&procset_slave);
1406 1419 }
1407 1420 CPUSET_ATOMIC_DEL(procset_slave, cpuid);
1408 1421
1409 1422 mach_cpucontext_free(cp, ctx, 0);
1410 1423
1411 1424 #ifndef __xpv
1412 1425 if (tsc_gethrtime_enable)
1413 1426 tsc_sync_master(cpuid);
1414 1427 #endif
1415 1428
1416 1429 if (dtrace_cpu_init != NULL) {
1417 1430 (*dtrace_cpu_init)(cpuid);
1418 1431 }
1419 1432
1420 1433 /*
1421 1434 * During CPU DR operations, the cpu_lock is held by current
1422 1435 * (the control) thread. We can't release the cpu_lock here
1423 1436 * because that will break the CPU DR logic.
1424 1437 * On the other hand, CPUPM and processor group initialization
1425 1438 * routines need to access the cpu_lock. So we invoke those
1426 1439 * routines here on behalf of mp_startup_common().
1427 1440 *
1428 1441 * CPUPM and processor group initialization routines depend
1429 1442 * on the cpuid probing results. Wait for mp_startup_common()
1430 1443 * to signal that cpuid probing is done.
1431 1444 */
1432 1445 mp_startup_wait(&procset_slave, cpuid);
1433 1446 #ifndef __xpv
1434 1447 cpupm_init(cp);
1435 1448 #endif
1436 1449 (void) pg_cpu_init(cp, B_FALSE);
1437 1450 cpu_set_state(cp);
1438 1451 mp_startup_signal(&procset_master, cpuid);
1439 1452
1440 1453 return (0);
1441 1454 }
1442 1455
1443 1456 /*
1444 1457 * Start a single cpu, assuming that the kernel context is available
1445 1458 * to successfully start another cpu.
1446 1459 *
1447 1460 * (For example, real mode code is mapped into the right place
1448 1461 * in memory and is ready to be run.)
1449 1462 */
1450 1463 int
1451 1464 start_cpu(processorid_t who)
1452 1465 {
1453 1466 cpu_t *cp;
1454 1467 int error = 0;
1455 1468 cpuset_t tempset;
1456 1469
1457 1470 ASSERT(who != 0);
1458 1471
1459 1472 /*
1460 1473 * Check if there's at least a Mbyte of kmem available
1461 1474 * before attempting to start the cpu.
1462 1475 */
1463 1476 if (kmem_avail() < 1024 * 1024) {
1464 1477 /*
1465 1478 * Kick off a reap in case that helps us with
1466 1479 * later attempts ..
1467 1480 */
1468 1481 kmem_reap();
1469 1482 return (ENOMEM);
1470 1483 }
1471 1484
1472 1485 /*
1473 1486 * First configure cpu.
1474 1487 */
1475 1488 cp = mp_cpu_configure_common(who, B_TRUE);
1476 1489 ASSERT(cp != NULL);
1477 1490
1478 1491 /*
1479 1492 * Then start cpu.
1480 1493 */
1481 1494 error = mp_start_cpu_common(cp, B_TRUE);
1482 1495 if (error != 0) {
1483 1496 mp_cpu_unconfigure_common(cp, error);
1484 1497 return (error);
1485 1498 }
1486 1499
1487 1500 mutex_exit(&cpu_lock);
1488 1501 tempset = cpu_ready_set;
1489 1502 while (!CPU_IN_SET(tempset, who)) {
1490 1503 drv_usecwait(1);
1491 1504 tempset = *((volatile cpuset_t *)&cpu_ready_set);
1492 1505 }
1493 1506 mutex_enter(&cpu_lock);
1494 1507
1495 1508 return (0);
1496 1509 }
1497 1510
1498 1511 void
1499 1512 start_other_cpus(int cprboot)
1500 1513 {
1501 1514 _NOTE(ARGUNUSED(cprboot));
1502 1515
1503 1516 uint_t who;
1504 1517 uint_t bootcpuid = 0;
1505 1518
1506 1519 /*
1507 1520 * Initialize our own cpu_info.
1508 1521 */
1509 1522 init_cpu_info(CPU);
1510 1523
1511 1524 #if !defined(__xpv)
1512 1525 init_cpu_id_gdt(CPU);
1513 1526 #endif
1514 1527
1515 1528 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_idstr);
1516 1529 cmn_err(CE_CONT, "?cpu%d: %s\n", CPU->cpu_id, CPU->cpu_brandstr);
1517 1530
1518 1531 /*
1519 1532 * Initialize our syscall handlers
1520 1533 */
1521 1534 init_cpu_syscall(CPU);
1522 1535
1523 1536 /*
1524 1537 * Take the boot cpu out of the mp_cpus set because we know
1525 1538 * it's already running. Add it to the cpu_ready_set for
1526 1539 * precisely the same reason.
1527 1540 */
1528 1541 CPUSET_DEL(mp_cpus, bootcpuid);
1529 1542 CPUSET_ADD(cpu_ready_set, bootcpuid);
1530 1543
1531 1544 /*
1532 1545 * skip the rest of this if
1533 1546 * . only 1 cpu dectected and system isn't hotplug-capable
1534 1547 * . not using MP
1535 1548 */
1536 1549 if ((CPUSET_ISNULL(mp_cpus) && plat_dr_support_cpu() == 0) ||
1537 1550 use_mp == 0) {
1538 1551 if (use_mp == 0)
1539 1552 cmn_err(CE_CONT, "?***** Not in MP mode\n");
1540 1553 goto done;
1541 1554 }
1542 1555
1543 1556 /*
1544 1557 * perform such initialization as is needed
1545 1558 * to be able to take CPUs on- and off-line.
1546 1559 */
1547 1560 cpu_pause_init();
1548 1561
1549 1562 xc_init_cpu(CPU); /* initialize processor crosscalls */
1550 1563
1551 1564 if (mach_cpucontext_init() != 0)
1552 1565 goto done;
1553 1566
1554 1567 flushes_require_xcalls = 1;
1555 1568
1556 1569 /*
1557 1570 * We lock our affinity to the master CPU to ensure that all slave CPUs
1558 1571 * do their TSC syncs with the same CPU.
1559 1572 */
1560 1573 affinity_set(CPU_CURRENT);
1561 1574
1562 1575 for (who = 0; who < NCPU; who++) {
1563 1576 if (!CPU_IN_SET(mp_cpus, who))
1564 1577 continue;
1565 1578 ASSERT(who != bootcpuid);
1566 1579
1567 1580 mutex_enter(&cpu_lock);
1568 1581 if (start_cpu(who) != 0)
1569 1582 CPUSET_DEL(mp_cpus, who);
1570 1583 cpu_state_change_notify(who, CPU_SETUP);
1571 1584 mutex_exit(&cpu_lock);
1572 1585 }
1573 1586
1574 1587 /* Free the space allocated to hold the microcode file */
1575 1588 ucode_cleanup();
1576 1589
1577 1590 affinity_clear();
1578 1591
1579 1592 mach_cpucontext_fini();
1580 1593
1581 1594 done:
1582 1595 if (get_hwenv() == HW_NATIVE)
1583 1596 workaround_errata_end();
1584 1597 cmi_post_mpstartup();
1585 1598
1586 1599 if (use_mp && ncpus != boot_max_ncpus) {
1587 1600 cmn_err(CE_NOTE,
1588 1601 "System detected %d cpus, but "
1589 1602 "only %d cpu(s) were enabled during boot.",
1590 1603 boot_max_ncpus, ncpus);
1591 1604 cmn_err(CE_NOTE,
1592 1605 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1593 1606 "See eeprom(1M).");
1594 1607 }
1595 1608 }
1596 1609
1597 1610 int
1598 1611 mp_cpu_configure(int cpuid)
1599 1612 {
1600 1613 cpu_t *cp;
1601 1614
1602 1615 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1603 1616 return (ENOTSUP);
1604 1617 }
1605 1618
1606 1619 cp = cpu_get(cpuid);
1607 1620 if (cp != NULL) {
1608 1621 return (EALREADY);
1609 1622 }
1610 1623
1611 1624 /*
1612 1625 * Check if there's at least a Mbyte of kmem available
1613 1626 * before attempting to start the cpu.
1614 1627 */
1615 1628 if (kmem_avail() < 1024 * 1024) {
1616 1629 /*
1617 1630 * Kick off a reap in case that helps us with
1618 1631 * later attempts ..
1619 1632 */
1620 1633 kmem_reap();
1621 1634 return (ENOMEM);
1622 1635 }
1623 1636
1624 1637 cp = mp_cpu_configure_common(cpuid, B_FALSE);
1625 1638 ASSERT(cp != NULL && cpu_get(cpuid) == cp);
1626 1639
1627 1640 return (cp != NULL ? 0 : EAGAIN);
1628 1641 }
1629 1642
1630 1643 int
1631 1644 mp_cpu_unconfigure(int cpuid)
1632 1645 {
1633 1646 cpu_t *cp;
1634 1647
1635 1648 if (use_mp == 0 || plat_dr_support_cpu() == 0) {
1636 1649 return (ENOTSUP);
1637 1650 } else if (cpuid < 0 || cpuid >= max_ncpus) {
1638 1651 return (EINVAL);
1639 1652 }
1640 1653
1641 1654 cp = cpu_get(cpuid);
1642 1655 if (cp == NULL) {
1643 1656 return (ENODEV);
1644 1657 }
1645 1658 mp_cpu_unconfigure_common(cp, 0);
1646 1659
1647 1660 return (0);
1648 1661 }
1649 1662
1650 1663 /*
1651 1664 * Startup function for 'other' CPUs (besides boot cpu).
1652 1665 * Called from real_mode_start.
1653 1666 *
1654 1667 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1655 1668 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1656 1669 * hat_unload which requires CPU_READY to be set.
1657 1670 */
1658 1671 static void
1659 1672 mp_startup_common(boolean_t boot)
1660 1673 {
1661 1674 cpu_t *cp = CPU;
1662 1675 uchar_t new_x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)];
1663 1676 extern void cpu_event_init_cpu(cpu_t *);
1664 1677
1665 1678 /*
1666 1679 * We need to get TSC on this proc synced (i.e., any delta
1667 1680 * from cpu0 accounted for) as soon as we can, because many
1668 1681 * many things use gethrtime/pc_gethrestime, including
1669 1682 * interrupts, cmn_err, etc. Before we can do that, we want to
1670 1683 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1671 1684 * right away.
1672 1685 */
1673 1686 bzero(new_x86_featureset, BT_SIZEOFMAP(NUM_X86_FEATURES));
1674 1687 cpuid_pass1(cp, new_x86_featureset);
1675 1688
1676 1689 if (boot && get_hwenv() == HW_NATIVE &&
1677 1690 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
1678 1691 cpuid_getfamily(CPU) == 6 &&
1679 1692 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
1680 1693 is_x86_feature(new_x86_featureset, X86FSET_TSC)) {
1681 1694 (void) wrmsr(REG_TSC, 0UL);
1682 1695 }
1683 1696
1684 1697 /* Let the control CPU continue into tsc_sync_master() */
1685 1698 mp_startup_signal(&procset_slave, cp->cpu_id);
1686 1699
1687 1700 #ifndef __xpv
1688 1701 if (tsc_gethrtime_enable)
1689 1702 tsc_sync_slave();
1690 1703 #endif
1691 1704
1692 1705 /*
1693 1706 * Once this was done from assembly, but it's safer here; if
1694 1707 * it blocks, we need to be able to swtch() to and from, and
1695 1708 * since we get here by calling t_pc, we need to do that call
1696 1709 * before swtch() overwrites it.
1697 1710 */
1698 1711 (void) (*ap_mlsetup)();
1699 1712
1700 1713 #ifndef __xpv
1701 1714 /*
1702 1715 * Program this cpu's PAT
1703 1716 */
1704 1717 pat_sync();
1705 1718 #endif
1706 1719
1707 1720 /*
1708 1721 * Set up TSC_AUX to contain the cpuid for this processor
1709 1722 * for the rdtscp instruction.
1710 1723 */
1711 1724 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
1712 1725 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id);
1713 1726
1714 1727 /*
1715 1728 * Initialize this CPU's syscall handlers
1716 1729 */
1717 1730 init_cpu_syscall(cp);
1718 1731
1719 1732 /*
1720 1733 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1721 1734 * highest level at which a routine is permitted to block on
1722 1735 * an adaptive mutex (allows for cpu poke interrupt in case
1723 1736 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1724 1737 * device interrupts that may end up in the hat layer issuing cross
1725 1738 * calls before CPU_READY is set.
1726 1739 */
1727 1740 splx(ipltospl(LOCK_LEVEL));
1728 1741 sti();
1729 1742
1730 1743 /*
1731 1744 * Do a sanity check to make sure this new CPU is a sane thing
1732 1745 * to add to the collection of processors running this system.
1733 1746 *
1734 1747 * XXX Clearly this needs to get more sophisticated, if x86
1735 1748 * systems start to get built out of heterogenous CPUs; as is
1736 1749 * likely to happen once the number of processors in a configuration
1737 1750 * gets large enough.
1738 1751 */
1739 1752 if (compare_x86_featureset(x86_featureset, new_x86_featureset) ==
1740 1753 B_FALSE) {
1741 1754 cmn_err(CE_CONT, "cpu%d: featureset\n", cp->cpu_id);
1742 1755 print_x86_featureset(new_x86_featureset);
1743 1756 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id);
1744 1757 }
1745 1758
1746 1759 /*
1747 1760 * There exists a small subset of systems which expose differing
1748 1761 * MWAIT/MONITOR support between CPUs. If MWAIT support is absent from
1749 1762 * the boot CPU, but is found on a later CPU, the system continues to
1750 1763 * operate as if no MWAIT support is available.
1751 1764 *
1752 1765 * The reverse case, where MWAIT is available on the boot CPU but not
1753 1766 * on a subsequently initialized CPU, is not presently allowed and will
1754 1767 * result in a panic.
1755 1768 */
1756 1769 if (is_x86_feature(x86_featureset, X86FSET_MWAIT) !=
1757 1770 is_x86_feature(new_x86_featureset, X86FSET_MWAIT)) {
1758 1771 if (!is_x86_feature(x86_featureset, X86FSET_MWAIT)) {
1759 1772 remove_x86_feature(new_x86_featureset, X86FSET_MWAIT);
1760 1773 } else {
1761 1774 panic("unsupported mixed cpu mwait support detected");
1762 1775 }
1763 1776 }
1764 1777
1765 1778 /*
1766 1779 * We could be more sophisticated here, and just mark the CPU
1767 1780 * as "faulted" but at this point we'll opt for the easier
1768 1781 * answer of dying horribly. Provided the boot cpu is ok,
1769 1782 * the system can be recovered by booting with use_mp set to zero.
1770 1783 */
1771 1784 if (workaround_errata(cp) != 0)
1772 1785 panic("critical workaround(s) missing for cpu%d", cp->cpu_id);
1773 1786
1774 1787 /*
1775 1788 * We can touch cpu_flags here without acquiring the cpu_lock here
|
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1776 1789 * because the cpu_lock is held by the control CPU which is running
1777 1790 * mp_start_cpu_common().
1778 1791 * Need to clear CPU_QUIESCED flag before calling any function which
1779 1792 * may cause thread context switching, such as kmem_alloc() etc.
1780 1793 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1781 1794 * it's set. So the startup thread may have no chance to switch back
1782 1795 * again if it's switched away with CPU_QUIESCED set.
1783 1796 */
1784 1797 cp->cpu_flags &= ~(CPU_POWEROFF | CPU_QUIESCED);
1785 1798
1799 + enable_pcid();
1800 +
1786 1801 /*
1787 1802 * Setup this processor for XSAVE.
1788 1803 */
1789 1804 if (fp_save_mech == FP_XSAVE) {
1790 1805 xsave_setup_msr(cp);
1791 1806 }
1792 1807
1793 1808 cpuid_pass2(cp);
1794 1809 cpuid_pass3(cp);
1795 1810 cpuid_pass4(cp, NULL);
1796 1811
1797 1812 /*
1798 1813 * Correct cpu_idstr and cpu_brandstr on target CPU after
1799 1814 * cpuid_pass1() is done.
1800 1815 */
1801 1816 (void) cpuid_getidstr(cp, cp->cpu_idstr, CPU_IDSTRLEN);
1802 1817 (void) cpuid_getbrandstr(cp, cp->cpu_brandstr, CPU_IDSTRLEN);
1803 1818
1804 1819 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_EXISTS;
1805 1820
1806 1821 post_startup_cpu_fixups();
1807 1822
1808 1823 cpu_event_init_cpu(cp);
1809 1824
1810 1825 /*
1811 1826 * Enable preemption here so that contention for any locks acquired
1812 1827 * later in mp_startup_common may be preempted if the thread owning
1813 1828 * those locks is continuously executing on other CPUs (for example,
1814 1829 * this CPU must be preemptible to allow other CPUs to pause it during
1815 1830 * their startup phases). It's safe to enable preemption here because
1816 1831 * the CPU state is pretty-much fully constructed.
1817 1832 */
1818 1833 curthread->t_preempt = 0;
1819 1834
1820 1835 /* The base spl should still be at LOCK LEVEL here */
1821 1836 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL));
1822 1837 set_base_spl(); /* Restore the spl to its proper value */
1823 1838
1824 1839 pghw_physid_create(cp);
1825 1840 /*
1826 1841 * Delegate initialization tasks, which need to access the cpu_lock,
1827 1842 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1828 1843 * during CPU DR operations.
1829 1844 */
1830 1845 mp_startup_signal(&procset_slave, cp->cpu_id);
1831 1846 mp_startup_wait(&procset_master, cp->cpu_id);
1832 1847 pg_cmt_cpu_startup(cp);
1833 1848
1834 1849 if (boot) {
1835 1850 mutex_enter(&cpu_lock);
1836 1851 cp->cpu_flags &= ~CPU_OFFLINE;
1837 1852 cpu_enable_intr(cp);
1838 1853 cpu_add_active(cp);
1839 1854 mutex_exit(&cpu_lock);
1840 1855 }
1841 1856
1842 1857 /* Enable interrupts */
1843 1858 (void) spl0();
1844 1859
1845 1860 /*
1846 1861 * Fill out cpu_ucode_info. Update microcode if necessary.
1847 1862 */
1848 1863 ucode_check(cp);
1849 1864
1850 1865 #ifndef __xpv
1851 1866 {
1852 1867 /*
1853 1868 * Set up the CPU module for this CPU. This can't be done
1854 1869 * before this CPU is made CPU_READY, because we may (in
1855 1870 * heterogeneous systems) need to go load another CPU module.
1856 1871 * The act of attempting to load a module may trigger a
1857 1872 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1858 1873 */
1859 1874 cmi_hdl_t hdl;
1860 1875
1861 1876 if ((hdl = cmi_init(CMI_HDL_NATIVE, cmi_ntv_hwchipid(CPU),
1862 1877 cmi_ntv_hwcoreid(CPU), cmi_ntv_hwstrandid(CPU))) != NULL) {
1863 1878 if (is_x86_feature(x86_featureset, X86FSET_MCA))
1864 1879 cmi_mca_init(hdl);
1865 1880 cp->cpu_m.mcpu_cmi_hdl = hdl;
1866 1881 }
1867 1882 }
1868 1883 #endif /* __xpv */
1869 1884
1870 1885 if (boothowto & RB_DEBUG)
1871 1886 kdi_cpu_init();
1872 1887
1873 1888 /*
1874 1889 * Setting the bit in cpu_ready_set must be the last operation in
1875 1890 * processor initialization; the boot CPU will continue to boot once
1876 1891 * it sees this bit set for all active CPUs.
1877 1892 */
1878 1893 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id);
1879 1894
1880 1895 (void) mach_cpu_create_device_node(cp, NULL);
1881 1896
1882 1897 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr);
1883 1898 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr);
1884 1899 cmn_err(CE_CONT, "?cpu%d initialization complete - online\n",
1885 1900 cp->cpu_id);
1886 1901
1887 1902 /*
1888 1903 * Now we are done with the startup thread, so free it up.
1889 1904 */
1890 1905 thread_exit();
1891 1906 panic("mp_startup: cannot return");
1892 1907 /*NOTREACHED*/
1893 1908 }
1894 1909
1895 1910 /*
1896 1911 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1897 1912 */
1898 1913 static void
1899 1914 mp_startup_boot(void)
1900 1915 {
1901 1916 mp_startup_common(B_TRUE);
1902 1917 }
1903 1918
1904 1919 /*
1905 1920 * Startup function for hotplug CPUs at runtime.
1906 1921 */
1907 1922 void
1908 1923 mp_startup_hotplug(void)
1909 1924 {
1910 1925 mp_startup_common(B_FALSE);
1911 1926 }
1912 1927
1913 1928 /*
1914 1929 * Start CPU on user request.
1915 1930 */
1916 1931 /* ARGSUSED */
1917 1932 int
1918 1933 mp_cpu_start(struct cpu *cp)
1919 1934 {
1920 1935 ASSERT(MUTEX_HELD(&cpu_lock));
1921 1936 return (0);
1922 1937 }
1923 1938
1924 1939 /*
1925 1940 * Stop CPU on user request.
1926 1941 */
1927 1942 int
1928 1943 mp_cpu_stop(struct cpu *cp)
1929 1944 {
1930 1945 extern int cbe_psm_timer_mode;
1931 1946 ASSERT(MUTEX_HELD(&cpu_lock));
1932 1947
1933 1948 #ifdef __xpv
1934 1949 /*
1935 1950 * We can't offline vcpu0.
1936 1951 */
1937 1952 if (cp->cpu_id == 0)
1938 1953 return (EBUSY);
1939 1954 #endif
1940 1955
1941 1956 /*
1942 1957 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1943 1958 * can't stop it. (This is true only for machines with no TSC.)
1944 1959 */
1945 1960
1946 1961 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0))
1947 1962 return (EBUSY);
1948 1963
1949 1964 return (0);
1950 1965 }
1951 1966
1952 1967 /*
1953 1968 * Take the specified CPU out of participation in interrupts.
1954 1969 */
1955 1970 int
1956 1971 cpu_disable_intr(struct cpu *cp)
1957 1972 {
1958 1973 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS)
1959 1974 return (EBUSY);
1960 1975
1961 1976 cp->cpu_flags &= ~CPU_ENABLE;
1962 1977 return (0);
1963 1978 }
1964 1979
1965 1980 /*
1966 1981 * Allow the specified CPU to participate in interrupts.
1967 1982 */
1968 1983 void
1969 1984 cpu_enable_intr(struct cpu *cp)
1970 1985 {
1971 1986 ASSERT(MUTEX_HELD(&cpu_lock));
1972 1987 cp->cpu_flags |= CPU_ENABLE;
1973 1988 psm_enable_intr(cp->cpu_id);
1974 1989 }
1975 1990
1976 1991 void
1977 1992 mp_cpu_faulted_enter(struct cpu *cp)
1978 1993 {
1979 1994 #ifdef __xpv
1980 1995 _NOTE(ARGUNUSED(cp));
1981 1996 #else
1982 1997 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
1983 1998
1984 1999 if (hdl != NULL) {
1985 2000 cmi_hdl_hold(hdl);
1986 2001 } else {
1987 2002 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
1988 2003 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
1989 2004 }
1990 2005 if (hdl != NULL) {
1991 2006 cmi_faulted_enter(hdl);
1992 2007 cmi_hdl_rele(hdl);
1993 2008 }
1994 2009 #endif
1995 2010 }
1996 2011
1997 2012 void
1998 2013 mp_cpu_faulted_exit(struct cpu *cp)
1999 2014 {
2000 2015 #ifdef __xpv
2001 2016 _NOTE(ARGUNUSED(cp));
2002 2017 #else
2003 2018 cmi_hdl_t hdl = cp->cpu_m.mcpu_cmi_hdl;
2004 2019
2005 2020 if (hdl != NULL) {
2006 2021 cmi_hdl_hold(hdl);
2007 2022 } else {
2008 2023 hdl = cmi_hdl_lookup(CMI_HDL_NATIVE, cmi_ntv_hwchipid(cp),
2009 2024 cmi_ntv_hwcoreid(cp), cmi_ntv_hwstrandid(cp));
2010 2025 }
2011 2026 if (hdl != NULL) {
2012 2027 cmi_faulted_exit(hdl);
2013 2028 cmi_hdl_rele(hdl);
2014 2029 }
2015 2030 #endif
2016 2031 }
2017 2032
2018 2033 /*
2019 2034 * The following two routines are used as context operators on threads belonging
2020 2035 * to processes with a private LDT (see sysi86). Due to the rarity of such
2021 2036 * processes, these routines are currently written for best code readability and
2022 2037 * organization rather than speed. We could avoid checking x86_featureset at
2023 2038 * every context switch by installing different context ops, depending on
2024 2039 * x86_featureset, at LDT creation time -- one for each combination of fast
2025 2040 * syscall features.
2026 2041 */
2027 2042
2028 2043 /*ARGSUSED*/
2029 2044 void
2030 2045 cpu_fast_syscall_disable(void *arg)
2031 2046 {
2032 2047 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2033 2048 is_x86_feature(x86_featureset, X86FSET_SEP))
2034 2049 cpu_sep_disable();
2035 2050 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2036 2051 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2037 2052 cpu_asysc_disable();
2038 2053 }
2039 2054
2040 2055 /*ARGSUSED*/
2041 2056 void
2042 2057 cpu_fast_syscall_enable(void *arg)
2043 2058 {
2044 2059 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2045 2060 is_x86_feature(x86_featureset, X86FSET_SEP))
2046 2061 cpu_sep_enable();
2047 2062 if (is_x86_feature(x86_featureset, X86FSET_MSR) &&
2048 2063 is_x86_feature(x86_featureset, X86FSET_ASYSC))
2049 2064 cpu_asysc_enable();
2050 2065 }
2051 2066
2052 2067 static void
2053 2068 cpu_sep_enable(void)
2054 2069 {
2055 2070 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2056 2071 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2057 2072
2058 2073 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL);
2059 2074 }
2060 2075
2061 2076 static void
2062 2077 cpu_sep_disable(void)
2063 2078 {
2064 2079 ASSERT(is_x86_feature(x86_featureset, X86FSET_SEP));
2065 2080 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2066 2081
2067 2082 /*
2068 2083 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2069 2084 * the sysenter or sysexit instruction to trigger a #gp fault.
2070 2085 */
2071 2086 wrmsr(MSR_INTC_SEP_CS, 0);
2072 2087 }
2073 2088
2074 2089 static void
2075 2090 cpu_asysc_enable(void)
2076 2091 {
2077 2092 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2078 2093 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2079 2094
2080 2095 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) |
2081 2096 (uint64_t)(uintptr_t)AMD_EFER_SCE);
2082 2097 }
2083 2098
2084 2099 static void
2085 2100 cpu_asysc_disable(void)
2086 2101 {
2087 2102 ASSERT(is_x86_feature(x86_featureset, X86FSET_ASYSC));
2088 2103 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL);
2089 2104
2090 2105 /*
2091 2106 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2092 2107 * executing syscall or sysret with this bit off will incur a #ud trap.
2093 2108 */
2094 2109 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) &
2095 2110 ~((uint64_t)(uintptr_t)AMD_EFER_SCE));
2096 2111 }
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