1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2012 Gary Mills
23 *
24 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
25 * Copyright (c) 2011 by Delphix. All rights reserved.
26 * Copyright 2018 Joyent, Inc.
27 */
28 /*
29 * Copyright (c) 2010, Intel Corporation.
30 * All rights reserved.
31 */
32
33 #include <sys/types.h>
34 #include <sys/sysmacros.h>
35 #include <sys/disp.h>
36 #include <sys/promif.h>
37 #include <sys/clock.h>
38 #include <sys/cpuvar.h>
39 #include <sys/stack.h>
40 #include <vm/as.h>
41 #include <vm/hat.h>
42 #include <sys/reboot.h>
43 #include <sys/avintr.h>
44 #include <sys/vtrace.h>
45 #include <sys/proc.h>
46 #include <sys/thread.h>
47 #include <sys/cpupart.h>
48 #include <sys/pset.h>
49 #include <sys/copyops.h>
50 #include <sys/pg.h>
51 #include <sys/disp.h>
52 #include <sys/debug.h>
53 #include <sys/sunddi.h>
54 #include <sys/x86_archext.h>
55 #include <sys/privregs.h>
56 #include <sys/machsystm.h>
57 #include <sys/ontrap.h>
58 #include <sys/bootconf.h>
59 #include <sys/boot_console.h>
60 #include <sys/kdi_machimpl.h>
61 #include <sys/archsystm.h>
62 #include <sys/promif.h>
63 #include <sys/pci_cfgspace.h>
64 #include <sys/bootvfs.h>
65 #include <sys/tsc.h>
66 #ifdef __xpv
67 #include <sys/hypervisor.h>
68 #else
69 #include <sys/xpv_support.h>
70 #endif
71
72 /*
73 * some globals for patching the result of cpuid
74 * to solve problems w/ creative cpu vendors
75 */
76
77 extern uint32_t cpuid_feature_ecx_include;
78 extern uint32_t cpuid_feature_ecx_exclude;
79 extern uint32_t cpuid_feature_edx_include;
80 extern uint32_t cpuid_feature_edx_exclude;
81
82 /*
83 * Set console mode
84 */
85 static void
86 set_console_mode(uint8_t val)
87 {
88 struct bop_regs rp = {0};
89
90 rp.eax.byte.ah = 0x0;
91 rp.eax.byte.al = val;
92 rp.ebx.word.bx = 0x0;
93
94 BOP_DOINT(bootops, 0x10, &rp);
95 }
96
97
98 /*
99 * Setup routine called right before main(). Interposing this function
100 * before main() allows us to call it in a machine-independent fashion.
101 */
102 void
103 mlsetup(struct regs *rp)
104 {
105 u_longlong_t prop_value;
106 extern struct classfuncs sys_classfuncs;
107 extern disp_t cpu0_disp;
108 extern char t0stack[];
109 extern int post_fastreboot;
110 extern uint64_t plat_dr_options;
111
112 ASSERT_STACK_ALIGNED();
113
114 /*
115 * initialize cpu_self
116 */
117 cpu[0]->cpu_self = cpu[0];
118
119 #if defined(__xpv)
120 /*
121 * Point at the hypervisor's virtual cpu structure
122 */
123 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0];
124 #endif
125
126 /*
127 * check if we've got special bits to clear or set
128 * when checking cpu features
129 */
130
131 if (bootprop_getval("cpuid_feature_ecx_include", &prop_value) != 0)
132 cpuid_feature_ecx_include = 0;
133 else
134 cpuid_feature_ecx_include = (uint32_t)prop_value;
135
136 if (bootprop_getval("cpuid_feature_ecx_exclude", &prop_value) != 0)
137 cpuid_feature_ecx_exclude = 0;
138 else
139 cpuid_feature_ecx_exclude = (uint32_t)prop_value;
140
141 if (bootprop_getval("cpuid_feature_edx_include", &prop_value) != 0)
142 cpuid_feature_edx_include = 0;
143 else
144 cpuid_feature_edx_include = (uint32_t)prop_value;
145
146 if (bootprop_getval("cpuid_feature_edx_exclude", &prop_value) != 0)
147 cpuid_feature_edx_exclude = 0;
148 else
149 cpuid_feature_edx_exclude = (uint32_t)prop_value;
150
151 #if !defined(__xpv)
152 /*
153 * Check to see if KPTI has been explicitly enabled or disabled.
154 * We have to check this before init_desctbls().
155 */
156 if (bootprop_getval("kpti", &prop_value) == 0) {
157 kpti_enable = (uint64_t)(prop_value == 1);
158 prom_printf("unix: forcing kpti to %s due to boot argument\n",
159 (kpti_enable == 1) ? "ON" : "OFF");
160 } else {
161 kpti_enable = 1;
162 }
163
164 if (bootprop_getval("pcid", &prop_value) == 0 && prop_value == 0) {
165 prom_printf("unix: forcing pcid to OFF due to boot argument\n");
166 x86_use_pcid = 0;
167 } else if (kpti_enable != 1) {
168 x86_use_pcid = 0;
169 }
170 #endif
171
172 /*
173 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss.
174 */
175 init_desctbls();
176
177 /*
178 * lgrp_init() and possibly cpuid_pass1() need PCI config
179 * space access
180 */
181 #if defined(__xpv)
182 if (DOMAIN_IS_INITDOMAIN(xen_info))
183 pci_cfgspace_init();
184 #else
185 pci_cfgspace_init();
186 /*
187 * Initialize the platform type from CPU 0 to ensure that
188 * determine_platform() is only ever called once.
189 */
190 determine_platform();
191 #endif
192
193 /*
194 * The first lightweight pass (pass0) through the cpuid data
195 * was done in locore before mlsetup was called. Do the next
196 * pass in C code.
197 *
198 * The x86_featureset is initialized here based on the capabilities
199 * of the boot CPU. Note that if we choose to support CPUs that have
200 * different feature sets (at which point we would almost certainly
201 * want to set the feature bits to correspond to the feature
202 * minimum) this value may be altered.
203 */
204 cpuid_pass1(cpu[0], x86_featureset);
205
206 #if !defined(__xpv)
207 if ((get_hwenv() & HW_XEN_HVM) != 0)
208 xen_hvm_init();
209
210 /*
211 * Before we do anything with the TSCs, we need to work around
212 * Intel erratum BT81. On some CPUs, warm reset does not
213 * clear the TSC. If we are on such a CPU, we will clear TSC ourselves
214 * here. Other CPUs will clear it when we boot them later, and the
215 * resulting skew will be handled by tsc_sync_master()/_slave();
216 * note that such skew already exists and has to be handled anyway.
217 *
218 * We do this only on metal. This same problem can occur with a
219 * hypervisor that does not happen to virtualise a TSC that starts from
220 * zero, regardless of CPU type; however, we do not expect hypervisors
221 * that do not virtualise TSC that way to handle writes to TSC
222 * correctly, either.
223 */
224 if (get_hwenv() == HW_NATIVE &&
225 cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
226 cpuid_getfamily(CPU) == 6 &&
227 (cpuid_getmodel(CPU) == 0x2d || cpuid_getmodel(CPU) == 0x3e) &&
228 is_x86_feature(x86_featureset, X86FSET_TSC)) {
229 (void) wrmsr(REG_TSC, 0UL);
230 }
231
232 /*
233 * Patch the tsc_read routine with appropriate set of instructions,
234 * depending on the processor family and architecure, to read the
235 * time-stamp counter while ensuring no out-of-order execution.
236 * Patch it while the kernel text is still writable.
237 *
238 * Note: tsc_read is not patched for intel processors whose family
239 * is >6 and for amd whose family >f (in case they don't support rdtscp
240 * instruction, unlikely). By default tsc_read will use cpuid for
241 * serialization in such cases. The following code needs to be
242 * revisited if intel processors of family >= f retains the
243 * instruction serialization nature of mfence instruction.
244 * Note: tsc_read is not patched for x86 processors which do
245 * not support "mfence". By default tsc_read will use cpuid for
246 * serialization in such cases.
247 *
248 * The Xen hypervisor does not correctly report whether rdtscp is
249 * supported or not, so we must assume that it is not.
250 */
251 if ((get_hwenv() & HW_XEN_HVM) == 0 &&
252 is_x86_feature(x86_featureset, X86FSET_TSCP))
253 patch_tsc_read(TSC_TSCP);
254 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD &&
255 cpuid_getfamily(CPU) <= 0xf &&
256 is_x86_feature(x86_featureset, X86FSET_SSE2))
257 patch_tsc_read(TSC_RDTSC_MFENCE);
258 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel &&
259 cpuid_getfamily(CPU) <= 6 &&
260 is_x86_feature(x86_featureset, X86FSET_SSE2))
261 patch_tsc_read(TSC_RDTSC_LFENCE);
262
263 #endif /* !__xpv */
264
265 #if defined(__i386) && !defined(__xpv)
266 /*
267 * Some i386 processors do not implement the rdtsc instruction,
268 * or at least they do not implement it correctly. Patch them to
269 * return 0.
270 */
271 if (!is_x86_feature(x86_featureset, X86FSET_TSC))
272 patch_tsc_read(TSC_NONE);
273 #endif /* __i386 && !__xpv */
274
275 #if defined(__amd64) && !defined(__xpv)
276 patch_memops(cpuid_getvendor(CPU));
277 #endif /* __amd64 && !__xpv */
278
279 #if !defined(__xpv)
280 /* XXPV what, if anything, should be dorked with here under xen? */
281
282 /*
283 * While we're thinking about the TSC, let's set up %cr4 so that
284 * userland can issue rdtsc, and initialize the TSC_AUX value
285 * (the cpuid) for the rdtscp instruction on appropriately
286 * capable hardware.
287 */
288 if (is_x86_feature(x86_featureset, X86FSET_TSC))
289 setcr4(getcr4() & ~CR4_TSD);
290
291 if (is_x86_feature(x86_featureset, X86FSET_TSCP))
292 (void) wrmsr(MSR_AMD_TSCAUX, 0);
293
294 /*
295 * Let's get the other %cr4 stuff while we're here. Note, we defer
296 * enabling CR4_SMAP until startup_end(); however, that's importantly
297 * before we start other CPUs. That ensures that it will be synced out
298 * to other CPUs.
299 */
300 if (is_x86_feature(x86_featureset, X86FSET_DE))
301 setcr4(getcr4() | CR4_DE);
302
303 if (is_x86_feature(x86_featureset, X86FSET_SMEP))
304 setcr4(getcr4() | CR4_SMEP);
305 #endif /* __xpv */
306
307 /*
308 * initialize t0
309 */
310 t0.t_stk = (caddr_t)rp - MINFRAME;
311 t0.t_stkbase = t0stack;
312 t0.t_pri = maxclsyspri - 3;
313 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP;
314 t0.t_procp = &p0;
315 t0.t_plockp = &p0lock.pl_lock;
316 t0.t_lwp = &lwp0;
317 t0.t_forw = &t0;
318 t0.t_back = &t0;
319 t0.t_next = &t0;
320 t0.t_prev = &t0;
321 t0.t_cpu = cpu[0];
322 t0.t_disp_queue = &cpu0_disp;
323 t0.t_bind_cpu = PBIND_NONE;
324 t0.t_bind_pset = PS_NONE;
325 t0.t_bindflag = (uchar_t)default_binding_mode;
326 t0.t_cpupart = &cp_default;
327 t0.t_clfuncs = &sys_classfuncs.thread;
328 t0.t_copyops = NULL;
329 THREAD_ONPROC(&t0, CPU);
330
331 lwp0.lwp_thread = &t0;
332 lwp0.lwp_regs = (void *)rp;
333 lwp0.lwp_procp = &p0;
334 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1;
335
336 p0.p_exec = NULL;
337 p0.p_stat = SRUN;
338 p0.p_flag = SSYS;
339 p0.p_tlist = &t0;
340 p0.p_stksize = 2*PAGESIZE;
341 p0.p_stkpageszc = 0;
342 p0.p_as = &kas;
343 p0.p_lockp = &p0lock;
344 p0.p_brkpageszc = 0;
345 p0.p_t1_lgrpid = LGRP_NONE;
346 p0.p_tr_lgrpid = LGRP_NONE;
347 psecflags_default(&p0.p_secflags);
348
349 sigorset(&p0.p_ignore, &ignoredefault);
350
351 CPU->cpu_thread = &t0;
352 bzero(&cpu0_disp, sizeof (disp_t));
353 CPU->cpu_disp = &cpu0_disp;
354 CPU->cpu_disp->disp_cpu = CPU;
355 CPU->cpu_dispthread = &t0;
356 CPU->cpu_idle_thread = &t0;
357 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE;
358 CPU->cpu_dispatch_pri = t0.t_pri;
359
360 CPU->cpu_id = 0;
361
362 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */
363
364 /*
365 * The kernel doesn't use LDTs unless a process explicitly requests one.
366 */
367 p0.p_ldt_desc = null_sdesc;
368
369 /*
370 * Initialize thread/cpu microstate accounting
371 */
372 init_mstate(&t0, LMS_SYSTEM);
373 init_cpu_mstate(CPU, CMS_SYSTEM);
374
375 /*
376 * Initialize lists of available and active CPUs.
377 */
378 cpu_list_init(CPU);
379
380 pg_cpu_bootstrap(CPU);
381
382 /*
383 * Now that we have taken over the GDT, IDT and have initialized
384 * active CPU list it's time to inform kmdb if present.
385 */
386 if (boothowto & RB_DEBUG)
387 kdi_idt_sync();
388
389 if (BOP_GETPROPLEN(bootops, "efi-systab") < 0) {
390 /*
391 * In BIOS system, explicitly set console to text mode (0x3)
392 * if this is a boot post Fast Reboot, and the console is set
393 * to CONS_SCREEN_TEXT.
394 */
395 if (post_fastreboot &&
396 boot_console_type(NULL) == CONS_SCREEN_TEXT) {
397 set_console_mode(0x3);
398 }
399 }
400
401 /*
402 * If requested (boot -d) drop into kmdb.
403 *
404 * This must be done after cpu_list_init() on the 64-bit kernel
405 * since taking a trap requires that we re-compute gsbase based
406 * on the cpu list.
407 */
408 if (boothowto & RB_DEBUGENTER)
409 kmdb_enter();
410
411 cpu_vm_data_init(CPU);
412
413 rp->r_fp = 0; /* terminate kernel stack traces! */
414
415 prom_init("kernel", (void *)NULL);
416
417 /* User-set option overrides firmware value. */
418 if (bootprop_getval(PLAT_DR_OPTIONS_NAME, &prop_value) == 0) {
419 plat_dr_options = (uint64_t)prop_value;
420 }
421 #if defined(__xpv)
422 /* No support of DR operations on xpv */
423 plat_dr_options = 0;
424 #else /* __xpv */
425 /* Flag PLAT_DR_FEATURE_ENABLED should only be set by DR driver. */
426 plat_dr_options &= ~PLAT_DR_FEATURE_ENABLED;
427 #ifndef __amd64
428 /* Only enable CPU/memory DR on 64 bits kernel. */
429 plat_dr_options &= ~PLAT_DR_FEATURE_MEMORY;
430 plat_dr_options &= ~PLAT_DR_FEATURE_CPU;
431 #endif /* __amd64 */
432 #endif /* __xpv */
433
434 /*
435 * Get value of "plat_dr_physmax" boot option.
436 * It overrides values calculated from MSCT or SRAT table.
437 */
438 if (bootprop_getval(PLAT_DR_PHYSMAX_NAME, &prop_value) == 0) {
439 plat_dr_physmax = ((uint64_t)prop_value) >> PAGESHIFT;
440 }
441
442 /* Get value of boot_ncpus. */
443 if (bootprop_getval(BOOT_NCPUS_NAME, &prop_value) != 0) {
444 boot_ncpus = NCPU;
445 } else {
446 boot_ncpus = (int)prop_value;
447 if (boot_ncpus <= 0 || boot_ncpus > NCPU)
448 boot_ncpus = NCPU;
449 }
450
451 /*
452 * Set max_ncpus and boot_max_ncpus to boot_ncpus if platform doesn't
453 * support CPU DR operations.
454 */
455 if (plat_dr_support_cpu() == 0) {
456 max_ncpus = boot_max_ncpus = boot_ncpus;
457 } else {
458 if (bootprop_getval(PLAT_MAX_NCPUS_NAME, &prop_value) != 0) {
459 max_ncpus = NCPU;
460 } else {
461 max_ncpus = (int)prop_value;
462 if (max_ncpus <= 0 || max_ncpus > NCPU) {
463 max_ncpus = NCPU;
464 }
465 if (boot_ncpus > max_ncpus) {
466 boot_ncpus = max_ncpus;
467 }
468 }
469
470 if (bootprop_getval(BOOT_MAX_NCPUS_NAME, &prop_value) != 0) {
471 boot_max_ncpus = boot_ncpus;
472 } else {
473 boot_max_ncpus = (int)prop_value;
474 if (boot_max_ncpus <= 0 || boot_max_ncpus > NCPU) {
475 boot_max_ncpus = boot_ncpus;
476 } else if (boot_max_ncpus > max_ncpus) {
477 boot_max_ncpus = max_ncpus;
478 }
479 }
480 }
481
482 /*
483 * Initialize the lgrp framework
484 */
485 lgrp_init(LGRP_INIT_STAGE1);
486
487 if (boothowto & RB_HALT) {
488 prom_printf("unix: kernel halted by -h flag\n");
489 prom_enter_mon();
490 }
491
492 ASSERT_STACK_ALIGNED();
493
494 /*
495 * Fill out cpu_ucode_info. Update microcode if necessary.
496 */
497 ucode_check(CPU);
498
499 if (workaround_errata(CPU) != 0)
500 panic("critical workaround(s) missing for boot cpu");
501 }
502
503
504 void
505 mach_modpath(char *path, const char *filename)
506 {
507 /*
508 * Construct the directory path from the filename.
509 */
510
511 int len;
512 char *p;
513 const char isastr[] = "/amd64";
514 size_t isalen = strlen(isastr);
515
516 len = strlen(SYSTEM_BOOT_PATH "/kernel");
517 (void) strcpy(path, SYSTEM_BOOT_PATH "/kernel ");
518 path += len + 1;
519
520 if ((p = strrchr(filename, '/')) == NULL)
521 return;
522
523 while (p > filename && *(p - 1) == '/')
524 p--; /* remove trailing '/' characters */
525 if (p == filename)
526 p++; /* so "/" -is- the modpath in this case */
527
528 /*
529 * Remove optional isa-dependent directory name - the module
530 * subsystem will put this back again (!)
531 */
532 len = p - filename;
533 if (len > isalen &&
534 strncmp(&filename[len - isalen], isastr, isalen) == 0)
535 p -= isalen;
536
537 /*
538 * "/platform/mumblefrotz" + " " + MOD_DEFPATH
539 */
540 len += (p - filename) + 1 + strlen(MOD_DEFPATH) + 1;
541 (void) strncpy(path, filename, p - filename);
542 }