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9215 update CPUID defines
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--- old/usr/src/uts/intel/sys/x86_archext.h
+++ new/usr/src/uts/intel/sys/x86_archext.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 25 */
26 26 /*
27 27 * Copyright (c) 2010, Intel Corporation.
28 28 * All rights reserved.
29 29 */
30 30 /*
31 31 * Copyright 2017 Joyent, Inc.
32 32 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
33 33 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
34 34 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
35 35 */
36 36
37 37 #ifndef _SYS_X86_ARCHEXT_H
38 38 #define _SYS_X86_ARCHEXT_H
39 39
40 40 #if !defined(_ASM)
41 41 #include <sys/regset.h>
42 42 #include <sys/processor.h>
43 43 #include <vm/seg_enum.h>
44 44 #include <vm/page.h>
45 45 #endif /* _ASM */
46 46
47 47 #ifdef __cplusplus
48 48 extern "C" {
49 49 #endif
50 50
51 51 /*
52 52 * cpuid instruction feature flags in %edx (standard function 1)
53 53 */
54 54
55 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
56 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
57 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
58 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
59 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
60 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
61 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
62 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
63 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
64 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
65 65 /* 0x400 - reserved */
66 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
67 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
68 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 75 /* 0x100000 - reserved */
76 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
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84 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87 87
88 88 /*
89 89 * cpuid instruction feature flags in %ecx (standard function 1)
90 90 */
91 91
92 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 - /* 0x00000004 - reserved */
94 +#define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 103 /* 0x00000800 - reserved */
104 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 - /* 0x00008000 - reserved */
107 +#define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 108 /* 0x00010000 - reserved */
109 - /* 0x00020000 - reserved */
109 +#define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 +#define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
116 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
117 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
118 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
119 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
120 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
121 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
122 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
123 124
124 125 /*
125 126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
126 127 */
127 128
128 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
129 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
130 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
131 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
132 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
133 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
134 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
135 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
136 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
137 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
138 139 /* 0x00000400 - sysc on K6m6 */
139 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
140 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
141 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
142 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
143 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
144 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
145 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
146 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
147 148 /* 0x00040000 - reserved */
148 149 /* 0x00080000 - reserved */
149 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
150 151 /* 0x00200000 - reserved */
151 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
152 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
153 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
154 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
155 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
156 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
157 158 /* 0x10000000 - reserved */
158 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
159 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
160 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
161 162
162 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
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163 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
164 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
165 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
166 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
167 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
168 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
169 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
170 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
171 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
172 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
173 -#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
174 +#define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */
174 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
175 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
177 + /* 0x00004000 - reserved */
178 +#define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
179 +#define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
180 + /* 0x00020000 - reserved */
181 + /* 0x00040000 - reserved */
182 +#define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
183 + /* 0x00100000 - reserved */
184 +#define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
176 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
177 186
178 187 /*
179 188 * AMD uses %ebx for some of their features (extended function 0x80000008).
180 189 */
181 190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */
182 191
183 192 /*
184 193 * Intel now seems to have claimed part of the "extended" function
185 194 * space that we previously for non-Intel implementors to use.
186 195 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
187 196 * is available in long mode i.e. what AMD indicate using bit 0.
188 197 * On the other hand, everything else is labelled as reserved.
189 198 */
190 199 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
191 200
192 201 /*
193 202 * Intel also uses cpuid leaf 7 to have additional instructions and features.
194 203 * Like some other leaves, but unlike the current ones we care about, it
195 204 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
196 205 * with the potential use of additional sub-leaves in the future, we now
197 206 * specifically label the EBX features with their leaf and sub-leaf.
198 207 */
199 208 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
200 209 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
201 210 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
202 211 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
203 212 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
204 213 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
205 214 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
206 215 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
207 216 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
208 217 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
209 218 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
210 219 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
211 220 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
212 221 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
213 222 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
214 223 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
215 224 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
216 225 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
217 226 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
218 227
219 228 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
220 229 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
221 230 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
222 231 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
223 232 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
224 233
225 234 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
226 235 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
227 236 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
228 237 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
229 238 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
230 239
231 240 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
232 241 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
233 242
234 243 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
235 244 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
236 245
237 246 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
238 247 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
239 248
240 249 /*
241 250 * Intel also uses cpuid leaf 0xd to report additional instructions and features
242 251 * when the sub-leaf in %ecx == 1. We label these using the same convention as
243 252 * with leaf 7.
244 253 */
245 254 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
246 255 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
247 256 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
248 257
249 258 #define P5_MCHADDR 0x0
250 259 #define P5_CESR 0x11
251 260 #define P5_CTR0 0x12
252 261 #define P5_CTR1 0x13
253 262
254 263 #define K5_MCHADDR 0x0
255 264 #define K5_MCHTYPE 0x01
256 265 #define K5_TSC 0x10
257 266 #define K5_TR12 0x12
258 267
259 268 #define REG_PAT 0x277
260 269
261 270 #define REG_MC0_CTL 0x400
262 271 #define REG_MC5_MISC 0x417
263 272 #define REG_PERFCTR0 0xc1
264 273 #define REG_PERFCTR1 0xc2
265 274
266 275 #define REG_PERFEVNT0 0x186
267 276 #define REG_PERFEVNT1 0x187
268 277
269 278 #define REG_TSC 0x10 /* timestamp counter */
270 279 #define REG_APIC_BASE_MSR 0x1b
271 280 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
272 281
273 282 #if !defined(__xpv)
274 283 /*
275 284 * AMD C1E
276 285 */
277 286 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
278 287 #define AMD_ACTONCMPHALT_SHIFT 27
279 288 #define AMD_ACTONCMPHALT_MASK 3
280 289 #endif
281 290
282 291 #define MSR_DEBUGCTL 0x1d9
283 292
284 293 #define DEBUGCTL_LBR 0x01
285 294 #define DEBUGCTL_BTF 0x02
286 295
287 296 /* Intel P6, AMD */
288 297 #define MSR_LBR_FROM 0x1db
289 298 #define MSR_LBR_TO 0x1dc
290 299 #define MSR_LEX_FROM 0x1dd
291 300 #define MSR_LEX_TO 0x1de
292 301
293 302 /* Intel P4 (pre-Prescott, non P4 M) */
294 303 #define MSR_P4_LBSTK_TOS 0x1da
295 304 #define MSR_P4_LBSTK_0 0x1db
296 305 #define MSR_P4_LBSTK_1 0x1dc
297 306 #define MSR_P4_LBSTK_2 0x1dd
298 307 #define MSR_P4_LBSTK_3 0x1de
299 308
300 309 /* Intel Pentium M */
301 310 #define MSR_P6M_LBSTK_TOS 0x1c9
302 311 #define MSR_P6M_LBSTK_0 0x040
303 312 #define MSR_P6M_LBSTK_1 0x041
304 313 #define MSR_P6M_LBSTK_2 0x042
305 314 #define MSR_P6M_LBSTK_3 0x043
306 315 #define MSR_P6M_LBSTK_4 0x044
307 316 #define MSR_P6M_LBSTK_5 0x045
308 317 #define MSR_P6M_LBSTK_6 0x046
309 318 #define MSR_P6M_LBSTK_7 0x047
310 319
311 320 /* Intel P4 (Prescott) */
312 321 #define MSR_PRP4_LBSTK_TOS 0x1da
313 322 #define MSR_PRP4_LBSTK_FROM_0 0x680
314 323 #define MSR_PRP4_LBSTK_FROM_1 0x681
315 324 #define MSR_PRP4_LBSTK_FROM_2 0x682
316 325 #define MSR_PRP4_LBSTK_FROM_3 0x683
317 326 #define MSR_PRP4_LBSTK_FROM_4 0x684
318 327 #define MSR_PRP4_LBSTK_FROM_5 0x685
319 328 #define MSR_PRP4_LBSTK_FROM_6 0x686
320 329 #define MSR_PRP4_LBSTK_FROM_7 0x687
321 330 #define MSR_PRP4_LBSTK_FROM_8 0x688
322 331 #define MSR_PRP4_LBSTK_FROM_9 0x689
323 332 #define MSR_PRP4_LBSTK_FROM_10 0x68a
324 333 #define MSR_PRP4_LBSTK_FROM_11 0x68b
325 334 #define MSR_PRP4_LBSTK_FROM_12 0x68c
326 335 #define MSR_PRP4_LBSTK_FROM_13 0x68d
327 336 #define MSR_PRP4_LBSTK_FROM_14 0x68e
328 337 #define MSR_PRP4_LBSTK_FROM_15 0x68f
329 338 #define MSR_PRP4_LBSTK_TO_0 0x6c0
330 339 #define MSR_PRP4_LBSTK_TO_1 0x6c1
331 340 #define MSR_PRP4_LBSTK_TO_2 0x6c2
332 341 #define MSR_PRP4_LBSTK_TO_3 0x6c3
333 342 #define MSR_PRP4_LBSTK_TO_4 0x6c4
334 343 #define MSR_PRP4_LBSTK_TO_5 0x6c5
335 344 #define MSR_PRP4_LBSTK_TO_6 0x6c6
336 345 #define MSR_PRP4_LBSTK_TO_7 0x6c7
337 346 #define MSR_PRP4_LBSTK_TO_8 0x6c8
338 347 #define MSR_PRP4_LBSTK_TO_9 0x6c9
339 348 #define MSR_PRP4_LBSTK_TO_10 0x6ca
340 349 #define MSR_PRP4_LBSTK_TO_11 0x6cb
341 350 #define MSR_PRP4_LBSTK_TO_12 0x6cc
342 351 #define MSR_PRP4_LBSTK_TO_13 0x6cd
343 352 #define MSR_PRP4_LBSTK_TO_14 0x6ce
344 353 #define MSR_PRP4_LBSTK_TO_15 0x6cf
345 354
346 355 #define MCI_CTL_VALUE 0xffffffff
347 356
348 357 #define MTRR_TYPE_UC 0
349 358 #define MTRR_TYPE_WC 1
350 359 #define MTRR_TYPE_WT 4
351 360 #define MTRR_TYPE_WP 5
352 361 #define MTRR_TYPE_WB 6
353 362 #define MTRR_TYPE_UC_ 7
354 363
355 364 /*
356 365 * For Solaris we set up the page attritubute table in the following way:
357 366 * PAT0 Write-Back
358 367 * PAT1 Write-Through
359 368 * PAT2 Unchacheable-
360 369 * PAT3 Uncacheable
361 370 * PAT4 Write-Back
362 371 * PAT5 Write-Through
363 372 * PAT6 Write-Combine
364 373 * PAT7 Uncacheable
365 374 * The only difference from h/w default is entry 6.
366 375 */
367 376 #define PAT_DEFAULT_ATTRIBUTE \
368 377 ((uint64_t)MTRR_TYPE_WB | \
369 378 ((uint64_t)MTRR_TYPE_WT << 8) | \
370 379 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
371 380 ((uint64_t)MTRR_TYPE_UC << 24) | \
372 381 ((uint64_t)MTRR_TYPE_WB << 32) | \
373 382 ((uint64_t)MTRR_TYPE_WT << 40) | \
374 383 ((uint64_t)MTRR_TYPE_WC << 48) | \
375 384 ((uint64_t)MTRR_TYPE_UC << 56))
376 385
377 386 #define X86FSET_LARGEPAGE 0
378 387 #define X86FSET_TSC 1
379 388 #define X86FSET_MSR 2
380 389 #define X86FSET_MTRR 3
381 390 #define X86FSET_PGE 4
382 391 #define X86FSET_DE 5
383 392 #define X86FSET_CMOV 6
384 393 #define X86FSET_MMX 7
385 394 #define X86FSET_MCA 8
386 395 #define X86FSET_PAE 9
387 396 #define X86FSET_CX8 10
388 397 #define X86FSET_PAT 11
389 398 #define X86FSET_SEP 12
390 399 #define X86FSET_SSE 13
391 400 #define X86FSET_SSE2 14
392 401 #define X86FSET_HTT 15
393 402 #define X86FSET_ASYSC 16
394 403 #define X86FSET_NX 17
395 404 #define X86FSET_SSE3 18
396 405 #define X86FSET_CX16 19
397 406 #define X86FSET_CMP 20
398 407 #define X86FSET_TSCP 21
399 408 #define X86FSET_MWAIT 22
400 409 #define X86FSET_SSE4A 23
401 410 #define X86FSET_CPUID 24
402 411 #define X86FSET_SSSE3 25
403 412 #define X86FSET_SSE4_1 26
404 413 #define X86FSET_SSE4_2 27
405 414 #define X86FSET_1GPG 28
406 415 #define X86FSET_CLFSH 29
407 416 #define X86FSET_64 30
408 417 #define X86FSET_AES 31
409 418 #define X86FSET_PCLMULQDQ 32
410 419 #define X86FSET_XSAVE 33
411 420 #define X86FSET_AVX 34
412 421 #define X86FSET_VMX 35
413 422 #define X86FSET_SVM 36
414 423 #define X86FSET_TOPOEXT 37
415 424 #define X86FSET_F16C 38
416 425 #define X86FSET_RDRAND 39
417 426 #define X86FSET_X2APIC 40
418 427 #define X86FSET_AVX2 41
419 428 #define X86FSET_BMI1 42
420 429 #define X86FSET_BMI2 43
421 430 #define X86FSET_FMA 44
422 431 #define X86FSET_SMEP 45
423 432 #define X86FSET_SMAP 46
424 433 #define X86FSET_ADX 47
425 434 #define X86FSET_RDSEED 48
426 435 #define X86FSET_MPX 49
427 436 #define X86FSET_AVX512F 50
428 437 #define X86FSET_AVX512DQ 51
429 438 #define X86FSET_AVX512PF 52
430 439 #define X86FSET_AVX512ER 53
431 440 #define X86FSET_AVX512CD 54
432 441 #define X86FSET_AVX512BW 55
433 442 #define X86FSET_AVX512VL 56
434 443 #define X86FSET_AVX512FMA 57
435 444 #define X86FSET_AVX512VBMI 58
436 445 #define X86FSET_AVX512VPOPCDQ 59
437 446 #define X86FSET_AVX512NNIW 60
438 447 #define X86FSET_AVX512FMAPS 61
439 448 #define X86FSET_XSAVEOPT 62
440 449 #define X86FSET_XSAVEC 63
441 450 #define X86FSET_XSAVES 64
442 451 #define X86FSET_SHA 65
443 452 #define X86FSET_UMIP 66
444 453 #define X86FSET_PKU 67
445 454 #define X86FSET_OSPKE 68
446 455
447 456 /*
448 457 * Intel Deep C-State invariant TSC in leaf 0x80000007.
449 458 */
450 459 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
451 460
452 461 /*
453 462 * Intel Deep C-state always-running local APIC timer
454 463 */
455 464 #define CPUID_CSTATE_ARAT (0x4)
456 465
457 466 /*
458 467 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
459 468 */
460 469 #define CPUID_EPB_SUPPORT (1 << 3)
461 470
462 471 /*
463 472 * Intel TSC deadline timer
464 473 */
465 474 #define CPUID_DEADLINE_TSC (1 << 24)
466 475
467 476 /*
468 477 * x86_type is a legacy concept; this is supplanted
469 478 * for most purposes by x86_featureset; modern CPUs
470 479 * should be X86_TYPE_OTHER
471 480 */
472 481 #define X86_TYPE_OTHER 0
473 482 #define X86_TYPE_486 1
474 483 #define X86_TYPE_P5 2
475 484 #define X86_TYPE_P6 3
476 485 #define X86_TYPE_CYRIX_486 4
477 486 #define X86_TYPE_CYRIX_6x86L 5
478 487 #define X86_TYPE_CYRIX_6x86 6
479 488 #define X86_TYPE_CYRIX_GXm 7
480 489 #define X86_TYPE_CYRIX_6x86MX 8
481 490 #define X86_TYPE_CYRIX_MediaGX 9
482 491 #define X86_TYPE_CYRIX_MII 10
483 492 #define X86_TYPE_VIA_CYRIX_III 11
484 493 #define X86_TYPE_P4 12
485 494
486 495 /*
487 496 * x86_vendor allows us to select between
488 497 * implementation features and helps guide
489 498 * the interpretation of the cpuid instruction.
490 499 */
491 500 #define X86_VENDOR_Intel 0
492 501 #define X86_VENDORSTR_Intel "GenuineIntel"
493 502
494 503 #define X86_VENDOR_IntelClone 1
495 504
496 505 #define X86_VENDOR_AMD 2
497 506 #define X86_VENDORSTR_AMD "AuthenticAMD"
498 507
499 508 #define X86_VENDOR_Cyrix 3
500 509 #define X86_VENDORSTR_CYRIX "CyrixInstead"
501 510
502 511 #define X86_VENDOR_UMC 4
503 512 #define X86_VENDORSTR_UMC "UMC UMC UMC "
504 513
505 514 #define X86_VENDOR_NexGen 5
506 515 #define X86_VENDORSTR_NexGen "NexGenDriven"
507 516
508 517 #define X86_VENDOR_Centaur 6
509 518 #define X86_VENDORSTR_Centaur "CentaurHauls"
510 519
511 520 #define X86_VENDOR_Rise 7
512 521 #define X86_VENDORSTR_Rise "RiseRiseRise"
513 522
514 523 #define X86_VENDOR_SiS 8
515 524 #define X86_VENDORSTR_SiS "SiS SiS SiS "
516 525
517 526 #define X86_VENDOR_TM 9
518 527 #define X86_VENDORSTR_TM "GenuineTMx86"
519 528
520 529 #define X86_VENDOR_NSC 10
521 530 #define X86_VENDORSTR_NSC "Geode by NSC"
522 531
523 532 /*
524 533 * Vendor string max len + \0
525 534 */
526 535 #define X86_VENDOR_STRLEN 13
527 536
528 537 /*
529 538 * Some vendor/family/model/stepping ranges are commonly grouped under
530 539 * a single identifying banner by the vendor. The following encode
531 540 * that "revision" in a uint32_t with the 8 most significant bits
532 541 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
533 542 * family, and the remaining 16 typically forming a bitmask of revisions
534 543 * within that family with more significant bits indicating "later" revisions.
535 544 */
536 545
537 546 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
538 547 #define _X86_CHIPREV_VENDOR_SHIFT 24
539 548 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
540 549 #define _X86_CHIPREV_FAMILY_SHIFT 16
541 550 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
542 551
543 552 #define _X86_CHIPREV_VENDOR(x) \
544 553 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
545 554 #define _X86_CHIPREV_FAMILY(x) \
546 555 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
547 556 #define _X86_CHIPREV_REV(x) \
548 557 ((x) & _X86_CHIPREV_REV_MASK)
549 558
550 559 /* True if x matches in vendor and family and if x matches the given rev mask */
551 560 #define X86_CHIPREV_MATCH(x, mask) \
552 561 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
553 562 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
554 563 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
555 564
556 565 /* True if x matches in vendor and family, and rev is at least minx */
557 566 #define X86_CHIPREV_ATLEAST(x, minx) \
558 567 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
559 568 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
560 569 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
561 570
562 571 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
563 572 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
564 573 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
565 574
566 575 /* True if x matches in vendor, and family is at least minx */
567 576 #define X86_CHIPFAM_ATLEAST(x, minx) \
568 577 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
569 578 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
570 579
571 580 /* Revision default */
572 581 #define X86_CHIPREV_UNKNOWN 0x0
573 582
574 583 /*
575 584 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
576 585 * sufficiently different that we will distinguish them; in all other
577 586 * case we will identify the major revision.
578 587 */
579 588 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
580 589 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
581 590 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
582 591 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
583 592 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
584 593 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
585 594 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
586 595
587 596 /*
588 597 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
589 598 */
590 599 #define X86_CHIPREV_AMD_10_REV_A \
591 600 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
592 601 #define X86_CHIPREV_AMD_10_REV_B \
593 602 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
594 603 #define X86_CHIPREV_AMD_10_REV_C2 \
595 604 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
596 605 #define X86_CHIPREV_AMD_10_REV_C3 \
597 606 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
598 607 #define X86_CHIPREV_AMD_10_REV_D0 \
599 608 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
600 609 #define X86_CHIPREV_AMD_10_REV_D1 \
601 610 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
602 611 #define X86_CHIPREV_AMD_10_REV_E \
603 612 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
604 613
605 614 /*
606 615 * Definitions for AMD Family 0x11.
607 616 */
608 617 #define X86_CHIPREV_AMD_11_REV_B \
609 618 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
610 619
611 620 /*
612 621 * Definitions for AMD Family 0x12.
613 622 */
614 623 #define X86_CHIPREV_AMD_12_REV_B \
615 624 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
616 625
617 626 /*
618 627 * Definitions for AMD Family 0x14.
619 628 */
620 629 #define X86_CHIPREV_AMD_14_REV_B \
621 630 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
622 631 #define X86_CHIPREV_AMD_14_REV_C \
623 632 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
624 633
625 634 /*
626 635 * Definitions for AMD Family 0x15
627 636 */
628 637 #define X86_CHIPREV_AMD_15OR_REV_B2 \
629 638 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
630 639
631 640 #define X86_CHIPREV_AMD_15TN_REV_A1 \
632 641 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
633 642
634 643 /*
635 644 * Various socket/package types, extended as the need to distinguish
636 645 * a new type arises. The top 8 byte identfies the vendor and the
637 646 * remaining 24 bits describe 24 socket types.
638 647 */
639 648
640 649 #define _X86_SOCKET_VENDOR_SHIFT 24
641 650 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
642 651 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
643 652 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
644 653
645 654 #define _X86_SOCKET_MKVAL(vendor, bitval) \
646 655 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
647 656
648 657 #define X86_SOCKET_MATCH(s, mask) \
649 658 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
650 659 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
651 660
652 661 #define X86_SOCKET_UNKNOWN 0x0
653 662 /*
654 663 * AMD socket types
655 664 */
656 665 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
657 666 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
658 667 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
659 668 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
660 669 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
661 670 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
662 671 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
663 672 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
664 673 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
665 674 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
666 675 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
667 676 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
668 677 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
669 678 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
670 679 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
671 680 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
672 681 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
673 682 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
674 683 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
675 684 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
676 685 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
677 686 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
678 687
679 688 /*
680 689 * xgetbv/xsetbv support
681 690 * See section 13.3 in vol. 1 of the Intel devlopers manual.
682 691 */
683 692
684 693 #define XFEATURE_ENABLED_MASK 0x0
685 694 /*
686 695 * XFEATURE_ENABLED_MASK values (eax)
687 696 * See setup_xfem().
688 697 */
689 698 #define XFEATURE_LEGACY_FP 0x1
690 699 #define XFEATURE_SSE 0x2
691 700 #define XFEATURE_AVX 0x4
692 701 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */
693 702 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */
694 703 /* bit 8 unused */
695 704 #define XFEATURE_PKRU 0x200
696 705 #define XFEATURE_FP_ALL \
697 706 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
698 707 XFEATURE_AVX512 | XFEATURE_PKRU)
699 708
700 709 #if !defined(_ASM)
701 710
702 711 #if defined(_KERNEL) || defined(_KMEMUSER)
703 712
704 713 #define NUM_X86_FEATURES 69
705 714 extern uchar_t x86_featureset[];
706 715
707 716 extern void free_x86_featureset(void *featureset);
708 717 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
709 718 extern void add_x86_feature(void *featureset, uint_t feature);
710 719 extern void remove_x86_feature(void *featureset, uint_t feature);
711 720 extern boolean_t compare_x86_featureset(void *setA, void *setB);
712 721 extern void print_x86_featureset(void *featureset);
713 722
714 723
715 724 extern uint_t x86_type;
716 725 extern uint_t x86_vendor;
717 726 extern uint_t x86_clflush_size;
718 727
719 728 extern uint_t pentiumpro_bug4046376;
720 729
721 730 extern const char CyrixInstead[];
722 731
723 732 #endif
724 733
725 734 #if defined(_KERNEL)
726 735
727 736 /*
728 737 * This structure is used to pass arguments and get return values back
729 738 * from the CPUID instruction in __cpuid_insn() routine.
730 739 */
731 740 struct cpuid_regs {
732 741 uint32_t cp_eax;
733 742 uint32_t cp_ebx;
734 743 uint32_t cp_ecx;
735 744 uint32_t cp_edx;
736 745 };
737 746
738 747 /*
739 748 * Utility functions to get/set extended control registers (XCR)
740 749 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
741 750 */
742 751 extern uint64_t get_xcr(uint_t);
743 752 extern void set_xcr(uint_t, uint64_t);
744 753
745 754 extern uint64_t rdmsr(uint_t);
746 755 extern void wrmsr(uint_t, const uint64_t);
747 756 extern uint64_t xrdmsr(uint_t);
748 757 extern void xwrmsr(uint_t, const uint64_t);
749 758 extern int checked_rdmsr(uint_t, uint64_t *);
750 759 extern int checked_wrmsr(uint_t, uint64_t);
751 760
752 761 extern void invalidate_cache(void);
753 762 extern ulong_t getcr4(void);
754 763 extern void setcr4(ulong_t);
755 764
756 765 extern void mtrr_sync(void);
757 766
758 767 extern void cpu_fast_syscall_enable(void *);
759 768 extern void cpu_fast_syscall_disable(void *);
760 769
761 770 struct cpu;
762 771
763 772 extern int cpuid_checkpass(struct cpu *, int);
764 773 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
765 774 extern uint32_t __cpuid_insn(struct cpuid_regs *);
766 775 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
767 776 extern int cpuid_getidstr(struct cpu *, char *, size_t);
768 777 extern const char *cpuid_getvendorstr(struct cpu *);
769 778 extern uint_t cpuid_getvendor(struct cpu *);
770 779 extern uint_t cpuid_getfamily(struct cpu *);
771 780 extern uint_t cpuid_getmodel(struct cpu *);
772 781 extern uint_t cpuid_getstep(struct cpu *);
773 782 extern uint_t cpuid_getsig(struct cpu *);
774 783 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
775 784 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
776 785 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
777 786 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
778 787 extern int cpuid_get_chipid(struct cpu *);
779 788 extern id_t cpuid_get_coreid(struct cpu *);
780 789 extern int cpuid_get_pkgcoreid(struct cpu *);
781 790 extern int cpuid_get_clogid(struct cpu *);
782 791 extern int cpuid_get_cacheid(struct cpu *);
783 792 extern uint32_t cpuid_get_apicid(struct cpu *);
784 793 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
785 794 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
786 795 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
787 796 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
788 797 extern size_t cpuid_get_xsave_size();
789 798 extern boolean_t cpuid_need_fp_excp_handling();
790 799 extern int cpuid_is_cmt(struct cpu *);
791 800 extern int cpuid_syscall32_insn(struct cpu *);
792 801 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
793 802
794 803 extern uint32_t cpuid_getchiprev(struct cpu *);
795 804 extern const char *cpuid_getchiprevstr(struct cpu *);
796 805 extern uint32_t cpuid_getsockettype(struct cpu *);
797 806 extern const char *cpuid_getsocketstr(struct cpu *);
798 807
799 808 extern int cpuid_have_cr8access(struct cpu *);
800 809
801 810 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
802 811
803 812 struct cpuid_info;
804 813
805 814 extern void setx86isalist(void);
806 815 extern void cpuid_alloc_space(struct cpu *);
807 816 extern void cpuid_free_space(struct cpu *);
808 817 extern void cpuid_pass1(struct cpu *, uchar_t *);
809 818 extern void cpuid_pass2(struct cpu *);
810 819 extern void cpuid_pass3(struct cpu *);
811 820 extern void cpuid_pass4(struct cpu *, uint_t *);
812 821 extern void cpuid_set_cpu_properties(void *, processorid_t,
813 822 struct cpuid_info *);
814 823
815 824 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
816 825 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
817 826
818 827 #if !defined(__xpv)
819 828 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
820 829 extern void cpuid_mwait_free(struct cpu *);
821 830 extern int cpuid_deep_cstates_supported(void);
822 831 extern int cpuid_arat_supported(void);
823 832 extern int cpuid_iepb_supported(struct cpu *);
824 833 extern int cpuid_deadline_tsc_supported(void);
825 834 extern void vmware_port(int, uint32_t *);
826 835 #endif
827 836
828 837 struct cpu_ucode_info;
829 838
830 839 extern void ucode_alloc_space(struct cpu *);
831 840 extern void ucode_free_space(struct cpu *);
832 841 extern void ucode_check(struct cpu *);
833 842 extern void ucode_cleanup();
834 843
835 844 #if !defined(__xpv)
836 845 extern char _tsc_mfence_start;
837 846 extern char _tsc_mfence_end;
838 847 extern char _tscp_start;
839 848 extern char _tscp_end;
840 849 extern char _no_rdtsc_start;
841 850 extern char _no_rdtsc_end;
842 851 extern char _tsc_lfence_start;
843 852 extern char _tsc_lfence_end;
844 853 #endif
845 854
846 855 #if !defined(__xpv)
847 856 extern char bcopy_patch_start;
848 857 extern char bcopy_patch_end;
849 858 extern char bcopy_ck_size;
850 859 #endif
851 860
852 861 extern void post_startup_cpu_fixups(void);
853 862
854 863 extern uint_t workaround_errata(struct cpu *);
855 864
856 865 #if defined(OPTERON_ERRATUM_93)
857 866 extern int opteron_erratum_93;
858 867 #endif
859 868
860 869 #if defined(OPTERON_ERRATUM_91)
861 870 extern int opteron_erratum_91;
862 871 #endif
863 872
864 873 #if defined(OPTERON_ERRATUM_100)
865 874 extern int opteron_erratum_100;
866 875 #endif
867 876
868 877 #if defined(OPTERON_ERRATUM_121)
869 878 extern int opteron_erratum_121;
870 879 #endif
871 880
872 881 #if defined(OPTERON_WORKAROUND_6323525)
873 882 extern int opteron_workaround_6323525;
874 883 extern void patch_workaround_6323525(void);
875 884 #endif
876 885
877 886 #if !defined(__xpv)
878 887 extern void determine_platform(void);
879 888 #endif
880 889 extern int get_hwenv(void);
881 890 extern int is_controldom(void);
882 891
883 892 extern void xsave_setup_msr(struct cpu *);
884 893
885 894 /*
886 895 * Hypervisor signatures
887 896 */
888 897 #define HVSIG_XEN_HVM "XenVMMXenVMM"
889 898 #define HVSIG_VMWARE "VMwareVMware"
890 899 #define HVSIG_KVM "KVMKVMKVM"
891 900 #define HVSIG_MICROSOFT "Microsoft Hv"
892 901
893 902 /*
894 903 * Defined hardware environments
895 904 */
896 905 #define HW_NATIVE (1 << 0) /* Running on bare metal */
897 906 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
898 907
899 908 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
900 909 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
901 910 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
902 911 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
903 912
904 913 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
905 914
906 915 #endif /* _KERNEL */
907 916
908 917 #endif /* !_ASM */
909 918
910 919 /*
911 920 * VMware hypervisor related defines
912 921 */
913 922 #define VMWARE_HVMAGIC 0x564d5868
914 923 #define VMWARE_HVPORT 0x5658
915 924 #define VMWARE_HVCMD_GETVERSION 0x0a
916 925 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
917 926
918 927 #ifdef __cplusplus
919 928 }
920 929 #endif
921 930
922 931 #endif /* _SYS_X86_ARCHEXT_H */
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