74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 /* 0x100000 - reserved */
76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87
88 /*
89 * cpuid instruction feature flags in %ecx (standard function 1)
90 */
91
92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 /* 0x00000004 - reserved */
95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 /* 0x00000800 - reserved */
104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 /* 0x00008000 - reserved */
108 /* 0x00010000 - reserved */
109 /* 0x00020000 - reserved */
110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
117 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
118 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
119 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
120 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
121 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
122 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
123
124 /*
125 * cpuid instruction feature flags in %edx (extended function 0x80000001)
126 */
127
128 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
129 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
130 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
131 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
132 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
133 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
134 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
135 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
153 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
154 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
155 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
156 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
157 /* 0x10000000 - reserved */
158 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
159 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
160 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
161
162 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
163 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
164 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
165 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
166 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
167 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
168 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
169 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
170 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
171 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
172 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
173 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */
174 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
175 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
176 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
177
178 /*
179 * AMD uses %ebx for some of their features (extended function 0x80000008).
180 */
181 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */
182
183 /*
184 * Intel now seems to have claimed part of the "extended" function
185 * space that we previously for non-Intel implementors to use.
186 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
187 * is available in long mode i.e. what AMD indicate using bit 0.
188 * On the other hand, everything else is labelled as reserved.
189 */
190 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
191
192 /*
193 * Intel also uses cpuid leaf 7 to have additional instructions and features.
194 * Like some other leaves, but unlike the current ones we care about, it
195 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
|
74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 /* 0x100000 - reserved */
76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87
88 /*
89 * cpuid instruction feature flags in %ecx (standard function 1)
90 */
91
92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 /* 0x00000800 - reserved */
104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 /* 0x00010000 - reserved */
109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
124
125 /*
126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
127 */
128
129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
158 /* 0x10000000 - reserved */
159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
162
163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */
175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
177 /* 0x00004000 - reserved */
178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
180 /* 0x00020000 - reserved */
181 /* 0x00040000 - reserved */
182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
183 /* 0x00100000 - reserved */
184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
186
187 /*
188 * AMD uses %ebx for some of their features (extended function 0x80000008).
189 */
190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */
191
192 /*
193 * Intel now seems to have claimed part of the "extended" function
194 * space that we previously for non-Intel implementors to use.
195 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
196 * is available in long mode i.e. what AMD indicate using bit 0.
197 * On the other hand, everything else is labelled as reserved.
198 */
199 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
200
201 /*
202 * Intel also uses cpuid leaf 7 to have additional instructions and features.
203 * Like some other leaves, but unlike the current ones we care about, it
204 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
|