1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved.
25 */
26 /*
27 * Copyright (c) 2010, Intel Corporation.
28 * All rights reserved.
29 */
30 /*
31 * Copyright 2017 Joyent, Inc.
32 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
33 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
34 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
35 */
36
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define _SYS_X86_ARCHEXT_H
39
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif /* _ASM */
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 /*
52 * cpuid instruction feature flags in %edx (standard function 1)
53 */
54
55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
65 /* 0x400 - reserved */
66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 /* 0x100000 - reserved */
76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87
88 /*
89 * cpuid instruction feature flags in %ecx (standard function 1)
90 */
91
92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 /* 0x00000800 - reserved */
104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 /* 0x00010000 - reserved */
109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
124
125 /*
126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
127 */
128
129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
139 /* 0x00000400 - sysc on K6m6 */
140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
148 /* 0x00040000 - reserved */
149 /* 0x00080000 - reserved */
150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
151 /* 0x00200000 - reserved */
152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
158 /* 0x10000000 - reserved */
159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
162
163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */
175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
177 /* 0x00004000 - reserved */
178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
180 /* 0x00020000 - reserved */
181 /* 0x00040000 - reserved */
182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
183 /* 0x00100000 - reserved */
184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
186
187 /*
188 * AMD uses %ebx for some of their features (extended function 0x80000008).
189 */
190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */
191
192 /*
193 * Intel now seems to have claimed part of the "extended" function
194 * space that we previously for non-Intel implementors to use.
195 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
196 * is available in long mode i.e. what AMD indicate using bit 0.
197 * On the other hand, everything else is labelled as reserved.
198 */
199 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
200
201 /*
202 * Intel also uses cpuid leaf 7 to have additional instructions and features.
203 * Like some other leaves, but unlike the current ones we care about, it
204 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
205 * with the potential use of additional sub-leaves in the future, we now
206 * specifically label the EBX features with their leaf and sub-leaf.
207 */
208 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
209 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
210 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
211 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
212 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
213 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
214 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
215 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
216 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
217 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
218 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
219 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
220 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
221 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
222 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
223 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
224 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
225 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
226 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
227
228 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
229 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
230 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
231 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
232 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
233
234 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
235 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
236 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
237 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
238 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
239
240 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
241 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
242
243 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
244 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
245
246 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
247 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
248
249 /*
250 * Intel also uses cpuid leaf 0xd to report additional instructions and features
251 * when the sub-leaf in %ecx == 1. We label these using the same convention as
252 * with leaf 7.
253 */
254 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
255 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
256 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
257
258 #define P5_MCHADDR 0x0
259 #define P5_CESR 0x11
260 #define P5_CTR0 0x12
261 #define P5_CTR1 0x13
262
263 #define K5_MCHADDR 0x0
264 #define K5_MCHTYPE 0x01
265 #define K5_TSC 0x10
266 #define K5_TR12 0x12
267
268 #define REG_PAT 0x277
269
270 #define REG_MC0_CTL 0x400
271 #define REG_MC5_MISC 0x417
272 #define REG_PERFCTR0 0xc1
273 #define REG_PERFCTR1 0xc2
274
275 #define REG_PERFEVNT0 0x186
276 #define REG_PERFEVNT1 0x187
277
278 #define REG_TSC 0x10 /* timestamp counter */
279 #define REG_APIC_BASE_MSR 0x1b
280 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
281
282 #if !defined(__xpv)
283 /*
284 * AMD C1E
285 */
286 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
287 #define AMD_ACTONCMPHALT_SHIFT 27
288 #define AMD_ACTONCMPHALT_MASK 3
289 #endif
290
291 #define MSR_DEBUGCTL 0x1d9
292
293 #define DEBUGCTL_LBR 0x01
294 #define DEBUGCTL_BTF 0x02
295
296 /* Intel P6, AMD */
297 #define MSR_LBR_FROM 0x1db
298 #define MSR_LBR_TO 0x1dc
299 #define MSR_LEX_FROM 0x1dd
300 #define MSR_LEX_TO 0x1de
301
302 /* Intel P4 (pre-Prescott, non P4 M) */
303 #define MSR_P4_LBSTK_TOS 0x1da
304 #define MSR_P4_LBSTK_0 0x1db
305 #define MSR_P4_LBSTK_1 0x1dc
306 #define MSR_P4_LBSTK_2 0x1dd
307 #define MSR_P4_LBSTK_3 0x1de
308
309 /* Intel Pentium M */
310 #define MSR_P6M_LBSTK_TOS 0x1c9
311 #define MSR_P6M_LBSTK_0 0x040
312 #define MSR_P6M_LBSTK_1 0x041
313 #define MSR_P6M_LBSTK_2 0x042
314 #define MSR_P6M_LBSTK_3 0x043
315 #define MSR_P6M_LBSTK_4 0x044
316 #define MSR_P6M_LBSTK_5 0x045
317 #define MSR_P6M_LBSTK_6 0x046
318 #define MSR_P6M_LBSTK_7 0x047
319
320 /* Intel P4 (Prescott) */
321 #define MSR_PRP4_LBSTK_TOS 0x1da
322 #define MSR_PRP4_LBSTK_FROM_0 0x680
323 #define MSR_PRP4_LBSTK_FROM_1 0x681
324 #define MSR_PRP4_LBSTK_FROM_2 0x682
325 #define MSR_PRP4_LBSTK_FROM_3 0x683
326 #define MSR_PRP4_LBSTK_FROM_4 0x684
327 #define MSR_PRP4_LBSTK_FROM_5 0x685
328 #define MSR_PRP4_LBSTK_FROM_6 0x686
329 #define MSR_PRP4_LBSTK_FROM_7 0x687
330 #define MSR_PRP4_LBSTK_FROM_8 0x688
331 #define MSR_PRP4_LBSTK_FROM_9 0x689
332 #define MSR_PRP4_LBSTK_FROM_10 0x68a
333 #define MSR_PRP4_LBSTK_FROM_11 0x68b
334 #define MSR_PRP4_LBSTK_FROM_12 0x68c
335 #define MSR_PRP4_LBSTK_FROM_13 0x68d
336 #define MSR_PRP4_LBSTK_FROM_14 0x68e
337 #define MSR_PRP4_LBSTK_FROM_15 0x68f
338 #define MSR_PRP4_LBSTK_TO_0 0x6c0
339 #define MSR_PRP4_LBSTK_TO_1 0x6c1
340 #define MSR_PRP4_LBSTK_TO_2 0x6c2
341 #define MSR_PRP4_LBSTK_TO_3 0x6c3
342 #define MSR_PRP4_LBSTK_TO_4 0x6c4
343 #define MSR_PRP4_LBSTK_TO_5 0x6c5
344 #define MSR_PRP4_LBSTK_TO_6 0x6c6
345 #define MSR_PRP4_LBSTK_TO_7 0x6c7
346 #define MSR_PRP4_LBSTK_TO_8 0x6c8
347 #define MSR_PRP4_LBSTK_TO_9 0x6c9
348 #define MSR_PRP4_LBSTK_TO_10 0x6ca
349 #define MSR_PRP4_LBSTK_TO_11 0x6cb
350 #define MSR_PRP4_LBSTK_TO_12 0x6cc
351 #define MSR_PRP4_LBSTK_TO_13 0x6cd
352 #define MSR_PRP4_LBSTK_TO_14 0x6ce
353 #define MSR_PRP4_LBSTK_TO_15 0x6cf
354
355 #define MCI_CTL_VALUE 0xffffffff
356
357 #define MTRR_TYPE_UC 0
358 #define MTRR_TYPE_WC 1
359 #define MTRR_TYPE_WT 4
360 #define MTRR_TYPE_WP 5
361 #define MTRR_TYPE_WB 6
362 #define MTRR_TYPE_UC_ 7
363
364 /*
365 * For Solaris we set up the page attritubute table in the following way:
366 * PAT0 Write-Back
367 * PAT1 Write-Through
368 * PAT2 Unchacheable-
369 * PAT3 Uncacheable
370 * PAT4 Write-Back
371 * PAT5 Write-Through
372 * PAT6 Write-Combine
373 * PAT7 Uncacheable
374 * The only difference from h/w default is entry 6.
375 */
376 #define PAT_DEFAULT_ATTRIBUTE \
377 ((uint64_t)MTRR_TYPE_WB | \
378 ((uint64_t)MTRR_TYPE_WT << 8) | \
379 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
380 ((uint64_t)MTRR_TYPE_UC << 24) | \
381 ((uint64_t)MTRR_TYPE_WB << 32) | \
382 ((uint64_t)MTRR_TYPE_WT << 40) | \
383 ((uint64_t)MTRR_TYPE_WC << 48) | \
384 ((uint64_t)MTRR_TYPE_UC << 56))
385
386 #define X86FSET_LARGEPAGE 0
387 #define X86FSET_TSC 1
388 #define X86FSET_MSR 2
389 #define X86FSET_MTRR 3
390 #define X86FSET_PGE 4
391 #define X86FSET_DE 5
392 #define X86FSET_CMOV 6
393 #define X86FSET_MMX 7
394 #define X86FSET_MCA 8
395 #define X86FSET_PAE 9
396 #define X86FSET_CX8 10
397 #define X86FSET_PAT 11
398 #define X86FSET_SEP 12
399 #define X86FSET_SSE 13
400 #define X86FSET_SSE2 14
401 #define X86FSET_HTT 15
402 #define X86FSET_ASYSC 16
403 #define X86FSET_NX 17
404 #define X86FSET_SSE3 18
405 #define X86FSET_CX16 19
406 #define X86FSET_CMP 20
407 #define X86FSET_TSCP 21
408 #define X86FSET_MWAIT 22
409 #define X86FSET_SSE4A 23
410 #define X86FSET_CPUID 24
411 #define X86FSET_SSSE3 25
412 #define X86FSET_SSE4_1 26
413 #define X86FSET_SSE4_2 27
414 #define X86FSET_1GPG 28
415 #define X86FSET_CLFSH 29
416 #define X86FSET_64 30
417 #define X86FSET_AES 31
418 #define X86FSET_PCLMULQDQ 32
419 #define X86FSET_XSAVE 33
420 #define X86FSET_AVX 34
421 #define X86FSET_VMX 35
422 #define X86FSET_SVM 36
423 #define X86FSET_TOPOEXT 37
424 #define X86FSET_F16C 38
425 #define X86FSET_RDRAND 39
426 #define X86FSET_X2APIC 40
427 #define X86FSET_AVX2 41
428 #define X86FSET_BMI1 42
429 #define X86FSET_BMI2 43
430 #define X86FSET_FMA 44
431 #define X86FSET_SMEP 45
432 #define X86FSET_SMAP 46
433 #define X86FSET_ADX 47
434 #define X86FSET_RDSEED 48
435 #define X86FSET_MPX 49
436 #define X86FSET_AVX512F 50
437 #define X86FSET_AVX512DQ 51
438 #define X86FSET_AVX512PF 52
439 #define X86FSET_AVX512ER 53
440 #define X86FSET_AVX512CD 54
441 #define X86FSET_AVX512BW 55
442 #define X86FSET_AVX512VL 56
443 #define X86FSET_AVX512FMA 57
444 #define X86FSET_AVX512VBMI 58
445 #define X86FSET_AVX512VPOPCDQ 59
446 #define X86FSET_AVX512NNIW 60
447 #define X86FSET_AVX512FMAPS 61
448 #define X86FSET_XSAVEOPT 62
449 #define X86FSET_XSAVEC 63
450 #define X86FSET_XSAVES 64
451 #define X86FSET_SHA 65
452 #define X86FSET_UMIP 66
453 #define X86FSET_PKU 67
454 #define X86FSET_OSPKE 68
455
456 /*
457 * Intel Deep C-State invariant TSC in leaf 0x80000007.
458 */
459 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
460
461 /*
462 * Intel Deep C-state always-running local APIC timer
463 */
464 #define CPUID_CSTATE_ARAT (0x4)
465
466 /*
467 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
468 */
469 #define CPUID_EPB_SUPPORT (1 << 3)
470
471 /*
472 * Intel TSC deadline timer
473 */
474 #define CPUID_DEADLINE_TSC (1 << 24)
475
476 /*
477 * x86_type is a legacy concept; this is supplanted
478 * for most purposes by x86_featureset; modern CPUs
479 * should be X86_TYPE_OTHER
480 */
481 #define X86_TYPE_OTHER 0
482 #define X86_TYPE_486 1
483 #define X86_TYPE_P5 2
484 #define X86_TYPE_P6 3
485 #define X86_TYPE_CYRIX_486 4
486 #define X86_TYPE_CYRIX_6x86L 5
487 #define X86_TYPE_CYRIX_6x86 6
488 #define X86_TYPE_CYRIX_GXm 7
489 #define X86_TYPE_CYRIX_6x86MX 8
490 #define X86_TYPE_CYRIX_MediaGX 9
491 #define X86_TYPE_CYRIX_MII 10
492 #define X86_TYPE_VIA_CYRIX_III 11
493 #define X86_TYPE_P4 12
494
495 /*
496 * x86_vendor allows us to select between
497 * implementation features and helps guide
498 * the interpretation of the cpuid instruction.
499 */
500 #define X86_VENDOR_Intel 0
501 #define X86_VENDORSTR_Intel "GenuineIntel"
502
503 #define X86_VENDOR_IntelClone 1
504
505 #define X86_VENDOR_AMD 2
506 #define X86_VENDORSTR_AMD "AuthenticAMD"
507
508 #define X86_VENDOR_Cyrix 3
509 #define X86_VENDORSTR_CYRIX "CyrixInstead"
510
511 #define X86_VENDOR_UMC 4
512 #define X86_VENDORSTR_UMC "UMC UMC UMC "
513
514 #define X86_VENDOR_NexGen 5
515 #define X86_VENDORSTR_NexGen "NexGenDriven"
516
517 #define X86_VENDOR_Centaur 6
518 #define X86_VENDORSTR_Centaur "CentaurHauls"
519
520 #define X86_VENDOR_Rise 7
521 #define X86_VENDORSTR_Rise "RiseRiseRise"
522
523 #define X86_VENDOR_SiS 8
524 #define X86_VENDORSTR_SiS "SiS SiS SiS "
525
526 #define X86_VENDOR_TM 9
527 #define X86_VENDORSTR_TM "GenuineTMx86"
528
529 #define X86_VENDOR_NSC 10
530 #define X86_VENDORSTR_NSC "Geode by NSC"
531
532 /*
533 * Vendor string max len + \0
534 */
535 #define X86_VENDOR_STRLEN 13
536
537 /*
538 * Some vendor/family/model/stepping ranges are commonly grouped under
539 * a single identifying banner by the vendor. The following encode
540 * that "revision" in a uint32_t with the 8 most significant bits
541 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
542 * family, and the remaining 16 typically forming a bitmask of revisions
543 * within that family with more significant bits indicating "later" revisions.
544 */
545
546 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
547 #define _X86_CHIPREV_VENDOR_SHIFT 24
548 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
549 #define _X86_CHIPREV_FAMILY_SHIFT 16
550 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
551
552 #define _X86_CHIPREV_VENDOR(x) \
553 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
554 #define _X86_CHIPREV_FAMILY(x) \
555 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
556 #define _X86_CHIPREV_REV(x) \
557 ((x) & _X86_CHIPREV_REV_MASK)
558
559 /* True if x matches in vendor and family and if x matches the given rev mask */
560 #define X86_CHIPREV_MATCH(x, mask) \
561 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
562 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
563 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
564
565 /* True if x matches in vendor and family, and rev is at least minx */
566 #define X86_CHIPREV_ATLEAST(x, minx) \
567 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
568 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
569 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
570
571 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
572 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
573 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
574
575 /* True if x matches in vendor, and family is at least minx */
576 #define X86_CHIPFAM_ATLEAST(x, minx) \
577 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
578 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
579
580 /* Revision default */
581 #define X86_CHIPREV_UNKNOWN 0x0
582
583 /*
584 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
585 * sufficiently different that we will distinguish them; in all other
586 * case we will identify the major revision.
587 */
588 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
589 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
590 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
591 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
592 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
593 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
594 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
595
596 /*
597 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
598 */
599 #define X86_CHIPREV_AMD_10_REV_A \
600 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
601 #define X86_CHIPREV_AMD_10_REV_B \
602 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
603 #define X86_CHIPREV_AMD_10_REV_C2 \
604 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
605 #define X86_CHIPREV_AMD_10_REV_C3 \
606 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
607 #define X86_CHIPREV_AMD_10_REV_D0 \
608 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
609 #define X86_CHIPREV_AMD_10_REV_D1 \
610 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
611 #define X86_CHIPREV_AMD_10_REV_E \
612 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
613
614 /*
615 * Definitions for AMD Family 0x11.
616 */
617 #define X86_CHIPREV_AMD_11_REV_B \
618 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
619
620 /*
621 * Definitions for AMD Family 0x12.
622 */
623 #define X86_CHIPREV_AMD_12_REV_B \
624 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
625
626 /*
627 * Definitions for AMD Family 0x14.
628 */
629 #define X86_CHIPREV_AMD_14_REV_B \
630 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
631 #define X86_CHIPREV_AMD_14_REV_C \
632 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
633
634 /*
635 * Definitions for AMD Family 0x15
636 */
637 #define X86_CHIPREV_AMD_15OR_REV_B2 \
638 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
639
640 #define X86_CHIPREV_AMD_15TN_REV_A1 \
641 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
642
643 /*
644 * Various socket/package types, extended as the need to distinguish
645 * a new type arises. The top 8 byte identfies the vendor and the
646 * remaining 24 bits describe 24 socket types.
647 */
648
649 #define _X86_SOCKET_VENDOR_SHIFT 24
650 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
651 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
652 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
653
654 #define _X86_SOCKET_MKVAL(vendor, bitval) \
655 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
656
657 #define X86_SOCKET_MATCH(s, mask) \
658 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
659 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
660
661 #define X86_SOCKET_UNKNOWN 0x0
662 /*
663 * AMD socket types
664 */
665 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
666 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
667 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
668 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
669 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
670 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
671 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
672 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
673 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
674 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
675 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
676 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
677 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
678 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
679 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
680 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
681 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
682 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
683 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
684 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
685 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
686 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
687
688 /*
689 * xgetbv/xsetbv support
690 * See section 13.3 in vol. 1 of the Intel devlopers manual.
691 */
692
693 #define XFEATURE_ENABLED_MASK 0x0
694 /*
695 * XFEATURE_ENABLED_MASK values (eax)
696 * See setup_xfem().
697 */
698 #define XFEATURE_LEGACY_FP 0x1
699 #define XFEATURE_SSE 0x2
700 #define XFEATURE_AVX 0x4
701 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */
702 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */
703 /* bit 8 unused */
704 #define XFEATURE_PKRU 0x200
705 #define XFEATURE_FP_ALL \
706 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
707 XFEATURE_AVX512 | XFEATURE_PKRU)
708
709 #if !defined(_ASM)
710
711 #if defined(_KERNEL) || defined(_KMEMUSER)
712
713 #define NUM_X86_FEATURES 69
714 extern uchar_t x86_featureset[];
715
716 extern void free_x86_featureset(void *featureset);
717 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
718 extern void add_x86_feature(void *featureset, uint_t feature);
719 extern void remove_x86_feature(void *featureset, uint_t feature);
720 extern boolean_t compare_x86_featureset(void *setA, void *setB);
721 extern void print_x86_featureset(void *featureset);
722
723
724 extern uint_t x86_type;
725 extern uint_t x86_vendor;
726 extern uint_t x86_clflush_size;
727
728 extern uint_t pentiumpro_bug4046376;
729
730 extern const char CyrixInstead[];
731
732 #endif
733
734 #if defined(_KERNEL)
735
736 /*
737 * This structure is used to pass arguments and get return values back
738 * from the CPUID instruction in __cpuid_insn() routine.
739 */
740 struct cpuid_regs {
741 uint32_t cp_eax;
742 uint32_t cp_ebx;
743 uint32_t cp_ecx;
744 uint32_t cp_edx;
745 };
746
747 /*
748 * Utility functions to get/set extended control registers (XCR)
749 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
750 */
751 extern uint64_t get_xcr(uint_t);
752 extern void set_xcr(uint_t, uint64_t);
753
754 extern uint64_t rdmsr(uint_t);
755 extern void wrmsr(uint_t, const uint64_t);
756 extern uint64_t xrdmsr(uint_t);
757 extern void xwrmsr(uint_t, const uint64_t);
758 extern int checked_rdmsr(uint_t, uint64_t *);
759 extern int checked_wrmsr(uint_t, uint64_t);
760
761 extern void invalidate_cache(void);
762 extern ulong_t getcr4(void);
763 extern void setcr4(ulong_t);
764
765 extern void mtrr_sync(void);
766
767 extern void cpu_fast_syscall_enable(void *);
768 extern void cpu_fast_syscall_disable(void *);
769
770 struct cpu;
771
772 extern int cpuid_checkpass(struct cpu *, int);
773 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
774 extern uint32_t __cpuid_insn(struct cpuid_regs *);
775 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
776 extern int cpuid_getidstr(struct cpu *, char *, size_t);
777 extern const char *cpuid_getvendorstr(struct cpu *);
778 extern uint_t cpuid_getvendor(struct cpu *);
779 extern uint_t cpuid_getfamily(struct cpu *);
780 extern uint_t cpuid_getmodel(struct cpu *);
781 extern uint_t cpuid_getstep(struct cpu *);
782 extern uint_t cpuid_getsig(struct cpu *);
783 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
784 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
785 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
786 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
787 extern int cpuid_get_chipid(struct cpu *);
788 extern id_t cpuid_get_coreid(struct cpu *);
789 extern int cpuid_get_pkgcoreid(struct cpu *);
790 extern int cpuid_get_clogid(struct cpu *);
791 extern int cpuid_get_cacheid(struct cpu *);
792 extern uint32_t cpuid_get_apicid(struct cpu *);
793 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
794 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
795 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
796 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
797 extern size_t cpuid_get_xsave_size();
798 extern boolean_t cpuid_need_fp_excp_handling();
799 extern int cpuid_is_cmt(struct cpu *);
800 extern int cpuid_syscall32_insn(struct cpu *);
801 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
802
803 extern uint32_t cpuid_getchiprev(struct cpu *);
804 extern const char *cpuid_getchiprevstr(struct cpu *);
805 extern uint32_t cpuid_getsockettype(struct cpu *);
806 extern const char *cpuid_getsocketstr(struct cpu *);
807
808 extern int cpuid_have_cr8access(struct cpu *);
809
810 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
811
812 struct cpuid_info;
813
814 extern void setx86isalist(void);
815 extern void cpuid_alloc_space(struct cpu *);
816 extern void cpuid_free_space(struct cpu *);
817 extern void cpuid_pass1(struct cpu *, uchar_t *);
818 extern void cpuid_pass2(struct cpu *);
819 extern void cpuid_pass3(struct cpu *);
820 extern void cpuid_pass4(struct cpu *, uint_t *);
821 extern void cpuid_set_cpu_properties(void *, processorid_t,
822 struct cpuid_info *);
823
824 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
825 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
826
827 #if !defined(__xpv)
828 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
829 extern void cpuid_mwait_free(struct cpu *);
830 extern int cpuid_deep_cstates_supported(void);
831 extern int cpuid_arat_supported(void);
832 extern int cpuid_iepb_supported(struct cpu *);
833 extern int cpuid_deadline_tsc_supported(void);
834 extern void vmware_port(int, uint32_t *);
835 #endif
836
837 struct cpu_ucode_info;
838
839 extern void ucode_alloc_space(struct cpu *);
840 extern void ucode_free_space(struct cpu *);
841 extern void ucode_check(struct cpu *);
842 extern void ucode_cleanup();
843
844 #if !defined(__xpv)
845 extern char _tsc_mfence_start;
846 extern char _tsc_mfence_end;
847 extern char _tscp_start;
848 extern char _tscp_end;
849 extern char _no_rdtsc_start;
850 extern char _no_rdtsc_end;
851 extern char _tsc_lfence_start;
852 extern char _tsc_lfence_end;
853 #endif
854
855 #if !defined(__xpv)
856 extern char bcopy_patch_start;
857 extern char bcopy_patch_end;
858 extern char bcopy_ck_size;
859 #endif
860
861 extern void post_startup_cpu_fixups(void);
862
863 extern uint_t workaround_errata(struct cpu *);
864
865 #if defined(OPTERON_ERRATUM_93)
866 extern int opteron_erratum_93;
867 #endif
868
869 #if defined(OPTERON_ERRATUM_91)
870 extern int opteron_erratum_91;
871 #endif
872
873 #if defined(OPTERON_ERRATUM_100)
874 extern int opteron_erratum_100;
875 #endif
876
877 #if defined(OPTERON_ERRATUM_121)
878 extern int opteron_erratum_121;
879 #endif
880
881 #if defined(OPTERON_WORKAROUND_6323525)
882 extern int opteron_workaround_6323525;
883 extern void patch_workaround_6323525(void);
884 #endif
885
886 #if !defined(__xpv)
887 extern void determine_platform(void);
888 #endif
889 extern int get_hwenv(void);
890 extern int is_controldom(void);
891
892 extern void xsave_setup_msr(struct cpu *);
893
894 /*
895 * Hypervisor signatures
896 */
897 #define HVSIG_XEN_HVM "XenVMMXenVMM"
898 #define HVSIG_VMWARE "VMwareVMware"
899 #define HVSIG_KVM "KVMKVMKVM"
900 #define HVSIG_MICROSOFT "Microsoft Hv"
901
902 /*
903 * Defined hardware environments
904 */
905 #define HW_NATIVE (1 << 0) /* Running on bare metal */
906 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
907
908 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
909 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
910 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
911 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
912
913 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
914
915 #endif /* _KERNEL */
916
917 #endif /* !_ASM */
918
919 /*
920 * VMware hypervisor related defines
921 */
922 #define VMWARE_HVMAGIC 0x564d5868
923 #define VMWARE_HVPORT 0x5658
924 #define VMWARE_HVCMD_GETVERSION 0x0a
925 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
926
927 #ifdef __cplusplus
928 }
929 #endif
930
931 #endif /* _SYS_X86_ARCHEXT_H */