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9210 remove KMDB branch debugging support
9211 ::crregs could do with cr2/cr3 support
9209 ::ttrace should be able to filter by thread
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>


   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
  23  * Copyright 2015, Joyent, Inc.


  24  */
  25 
  26 #ifndef _SYS_CONTROLREGS_H
  27 #define _SYS_CONTROLREGS_H
  28 
  29 #ifndef _ASM
  30 #include <sys/types.h>
  31 #endif
  32 
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36 
  37 /*
  38  * This file describes the x86 architecture control registers which
  39  * are part of the privileged architecture.
  40  *
  41  * Many of these definitions are shared between IA-32-style and
  42  * AMD64-style processors.
  43  */


  91 
  92 #define FMT_CR3 "\20\5pcd\4pwt"
  93 
  94 /* CR4 Register */
  95 
  96 #define CR4_VME         0x0001          /* virtual-8086 mode extensions */
  97 #define CR4_PVI         0x0002          /* protected-mode virtual interrupts */
  98 #define CR4_TSD         0x0004          /* time stamp disable           */
  99 #define CR4_DE          0x0008          /* debugging extensions         */
 100 #define CR4_PSE         0x0010          /* page size extensions         */
 101 #define CR4_PAE         0x0020          /* physical address extension   */
 102 #define CR4_MCE         0x0040          /* machine check enable         */
 103 #define CR4_PGE         0x0080          /* page global enable           */
 104 #define CR4_PCE         0x0100          /* perf-monitoring counter enable */
 105 #define CR4_OSFXSR      0x0200          /* OS fxsave/fxrstor support    */
 106 #define CR4_OSXMMEXCPT  0x0400          /* OS unmasked exception support */
 107                                         /* 0x0800 reserved */
 108                                         /* 0x1000 reserved */
 109 #define CR4_VMXE        0x2000
 110 #define CR4_SMXE        0x4000

 111 #define CR4_OSXSAVE     0x40000         /* OS xsave/xrestore support    */
 112 #define CR4_SMEP        0x100000        /* NX for user pages in kernel */
 113 #define CR4_SMAP        0x200000        /* kernel can't access user pages */
 114 
 115 #define FMT_CR4                                         \
 116         "\20\26smap\25smep\23osxsav"                    \
 117         "\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge"      \
 118         "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
 119 
 120 /*
 121  * Enable the SSE-related control bits to explain to the processor that
 122  * we're managing XMM state and exceptions
 123  */
 124 #define CR4_ENABLE_SSE_FLAGS(cr)        \
 125         ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT)
 126 
 127 /*
 128  * Disable the SSE-related control bits to explain to the processor
 129  * that we're NOT managing XMM state
 130  */
 131 #define CR4_DISABLE_SSE_FLAGS(cr)       \
 132         ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT))
 133 
 134 /* Intel's SYSENTER configuration registers */
 135 
 136 #define MSR_INTC_SEP_CS 0x174           /* kernel code selector MSR */




   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
  23  * Copyright 2015, Joyent, Inc.
  24  *
  25  * Copyright 2018 Joyent, Inc.
  26  */
  27 
  28 #ifndef _SYS_CONTROLREGS_H
  29 #define _SYS_CONTROLREGS_H
  30 
  31 #ifndef _ASM
  32 #include <sys/types.h>
  33 #endif
  34 
  35 #ifdef __cplusplus
  36 extern "C" {
  37 #endif
  38 
  39 /*
  40  * This file describes the x86 architecture control registers which
  41  * are part of the privileged architecture.
  42  *
  43  * Many of these definitions are shared between IA-32-style and
  44  * AMD64-style processors.
  45  */


  93 
  94 #define FMT_CR3 "\20\5pcd\4pwt"
  95 
  96 /* CR4 Register */
  97 
  98 #define CR4_VME         0x0001          /* virtual-8086 mode extensions */
  99 #define CR4_PVI         0x0002          /* protected-mode virtual interrupts */
 100 #define CR4_TSD         0x0004          /* time stamp disable           */
 101 #define CR4_DE          0x0008          /* debugging extensions         */
 102 #define CR4_PSE         0x0010          /* page size extensions         */
 103 #define CR4_PAE         0x0020          /* physical address extension   */
 104 #define CR4_MCE         0x0040          /* machine check enable         */
 105 #define CR4_PGE         0x0080          /* page global enable           */
 106 #define CR4_PCE         0x0100          /* perf-monitoring counter enable */
 107 #define CR4_OSFXSR      0x0200          /* OS fxsave/fxrstor support    */
 108 #define CR4_OSXMMEXCPT  0x0400          /* OS unmasked exception support */
 109                                         /* 0x0800 reserved */
 110                                         /* 0x1000 reserved */
 111 #define CR4_VMXE        0x2000
 112 #define CR4_SMXE        0x4000
 113 #define CR4_PCIDE       0x20000         /* PCID enable */
 114 #define CR4_OSXSAVE     0x40000         /* OS xsave/xrestore support    */
 115 #define CR4_SMEP        0x100000        /* NX for user pages in kernel */
 116 #define CR4_SMAP        0x200000        /* kernel can't access user pages */
 117 
 118 #define FMT_CR4                                         \
 119         "\20\26smap\25smep\23osxsav\22pcide"            \
 120         "\17smxe\16vmxe\13xmme\12fxsr\11pce\10pge"      \
 121         "\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
 122 
 123 /*
 124  * Enable the SSE-related control bits to explain to the processor that
 125  * we're managing XMM state and exceptions
 126  */
 127 #define CR4_ENABLE_SSE_FLAGS(cr)        \
 128         ((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT)
 129 
 130 /*
 131  * Disable the SSE-related control bits to explain to the processor
 132  * that we're NOT managing XMM state
 133  */
 134 #define CR4_DISABLE_SSE_FLAGS(cr)       \
 135         ((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT))
 136 
 137 /* Intel's SYSENTER configuration registers */
 138 
 139 #define MSR_INTC_SEP_CS 0x174           /* kernel code selector MSR */