Print this page
9208 hati_demap_func should take pagesize into account
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Tim Kordas <tim.kordas@joyent.com>


   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.

  24  */
  25 
  26 #ifndef _VM_HAT_PTE_H
  27 #define _VM_HAT_PTE_H
  28 
  29 #ifdef  __cplusplus
  30 extern "C" {
  31 #endif
  32 
  33 #include <sys/types.h>
  34 #include <sys/mach_mmu.h>
  35 
  36 /*
  37  * macros to get/set/clear the PTE fields
  38  */
  39 #define PTE_SET(p, f)   ((p) |= (f))
  40 #define PTE_CLR(p, f)   ((p) &= ~(x86pte_t)(f))
  41 #define PTE_GET(p, f)   ((p) & (f))
  42 
  43 /*


 121  *      AMD/INTEL name          Level #
 122  *      ----------------------  -------
 123  *      Page Map Level 4           3
 124  *      Page Directory Pointer     2
 125  *      Page Directory             1
 126  *      Page Table                 0
 127  *
 128  * The numbering scheme is such that the values of 0 and 1 can correspond to
 129  * the pagesize codes used for MPSS support. For now the Maximum level at
 130  * which you can have a large page is a constant, that may change in
 131  * future processors.
 132  *
 133  * The type of "level_t" is signed so that it can be used like:
 134  *      level_t l;
 135  *      ...
 136  *      while (--l >= 0)
 137  *              ...
 138  */
 139 #define MAX_NUM_LEVEL           4
 140 #define MAX_PAGE_LEVEL          2

 141 typedef int8_t level_t;
 142 #define LEVEL_SHIFT(l)  (mmu.level_shift[l])
 143 #define LEVEL_SIZE(l)   (mmu.level_size[l])
 144 #define LEVEL_OFFSET(l) (mmu.level_offset[l])
 145 #define LEVEL_MASK(l)   (mmu.level_mask[l])
 146 
 147 /*
 148  * Macros to:
 149  * Check for a PFN above 4Gig and 64Gig for 32 bit PAE support
 150  */
 151 #define PFN_4G          (4ull * (1024 * 1024 * 1024 / MMU_PAGESIZE))
 152 #define PFN_64G         (64ull * (1024 * 1024 * 1024 / MMU_PAGESIZE))
 153 #define PFN_ABOVE4G(pfn) ((pfn) >= PFN_4G)
 154 #define PFN_ABOVE64G(pfn) ((pfn) >= PFN_64G)
 155 
 156 /*
 157  * The CR3 register holds the physical address of the top level page table.
 158  */
 159 #define MAKECR3(pfn)    mmu_ptob(pfn)
 160 




   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  * Copyright 2017 Joyent, Inc.  All rights reserved.
  25  */
  26 
  27 #ifndef _VM_HAT_PTE_H
  28 #define _VM_HAT_PTE_H
  29 
  30 #ifdef  __cplusplus
  31 extern "C" {
  32 #endif
  33 
  34 #include <sys/types.h>
  35 #include <sys/mach_mmu.h>
  36 
  37 /*
  38  * macros to get/set/clear the PTE fields
  39  */
  40 #define PTE_SET(p, f)   ((p) |= (f))
  41 #define PTE_CLR(p, f)   ((p) &= ~(x86pte_t)(f))
  42 #define PTE_GET(p, f)   ((p) & (f))
  43 
  44 /*


 122  *      AMD/INTEL name          Level #
 123  *      ----------------------  -------
 124  *      Page Map Level 4           3
 125  *      Page Directory Pointer     2
 126  *      Page Directory             1
 127  *      Page Table                 0
 128  *
 129  * The numbering scheme is such that the values of 0 and 1 can correspond to
 130  * the pagesize codes used for MPSS support. For now the Maximum level at
 131  * which you can have a large page is a constant, that may change in
 132  * future processors.
 133  *
 134  * The type of "level_t" is signed so that it can be used like:
 135  *      level_t l;
 136  *      ...
 137  *      while (--l >= 0)
 138  *              ...
 139  */
 140 #define MAX_NUM_LEVEL           4
 141 #define MAX_PAGE_LEVEL          2
 142 #define MIN_PAGE_LEVEL          0
 143 typedef int8_t level_t;
 144 #define LEVEL_SHIFT(l)  (mmu.level_shift[l])
 145 #define LEVEL_SIZE(l)   (mmu.level_size[l])
 146 #define LEVEL_OFFSET(l) (mmu.level_offset[l])
 147 #define LEVEL_MASK(l)   (mmu.level_mask[l])
 148 
 149 /*
 150  * Macros to:
 151  * Check for a PFN above 4Gig and 64Gig for 32 bit PAE support
 152  */
 153 #define PFN_4G          (4ull * (1024 * 1024 * 1024 / MMU_PAGESIZE))
 154 #define PFN_64G         (64ull * (1024 * 1024 * 1024 / MMU_PAGESIZE))
 155 #define PFN_ABOVE4G(pfn) ((pfn) >= PFN_4G)
 156 #define PFN_ABOVE64G(pfn) ((pfn) >= PFN_64G)
 157 
 158 /*
 159  * The CR3 register holds the physical address of the top level page table.
 160  */
 161 #define MAKECR3(pfn)    mmu_ptob(pfn)
 162