Print this page
9208 hati_demap_func should take pagesize into account
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Tim Kordas <tim.kordas@joyent.com>
Split |
Close |
Expand all |
Collapse all |
--- old/usr/src/uts/i86pc/vm/hat_i86.c
+++ new/usr/src/uts/i86pc/vm/hat_i86.c
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
↓ open down ↓ |
19 lines elided |
↑ open up ↑ |
20 20 */
21 21 /*
22 22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24 /*
25 25 * Copyright (c) 2010, Intel Corporation.
26 26 * All rights reserved.
27 27 */
28 28 /*
29 29 * Copyright 2011 Nexenta Systems, Inc. All rights reserved.
30 + * Copyright 2017 Joyent, Inc. All rights reserved.
30 31 * Copyright (c) 2014, 2015 by Delphix. All rights reserved.
31 32 */
32 33
33 34 /*
34 35 * VM - Hardware Address Translation management for i386 and amd64
35 36 *
36 37 * Implementation of the interfaces described in <common/vm/hat.h>
37 38 *
38 39 * Nearly all the details of how the hardware is managed should not be
39 40 * visible outside this layer except for misc. machine specific functions
40 41 * that work in conjunction with this code.
41 42 *
42 43 * Routines used only inside of i86pc/vm start with hati_ for HAT Internal.
43 44 */
44 45
45 46 #include <sys/machparam.h>
46 47 #include <sys/machsystm.h>
47 48 #include <sys/mman.h>
48 49 #include <sys/types.h>
49 50 #include <sys/systm.h>
50 51 #include <sys/cpuvar.h>
51 52 #include <sys/thread.h>
52 53 #include <sys/proc.h>
53 54 #include <sys/cpu.h>
54 55 #include <sys/kmem.h>
55 56 #include <sys/disp.h>
56 57 #include <sys/shm.h>
57 58 #include <sys/sysmacros.h>
58 59 #include <sys/machparam.h>
59 60 #include <sys/vmem.h>
60 61 #include <sys/vmsystm.h>
61 62 #include <sys/promif.h>
62 63 #include <sys/var.h>
63 64 #include <sys/x86_archext.h>
64 65 #include <sys/atomic.h>
65 66 #include <sys/bitmap.h>
66 67 #include <sys/controlregs.h>
67 68 #include <sys/bootconf.h>
68 69 #include <sys/bootsvcs.h>
69 70 #include <sys/bootinfo.h>
70 71 #include <sys/archsystm.h>
71 72
72 73 #include <vm/seg_kmem.h>
73 74 #include <vm/hat_i86.h>
74 75 #include <vm/as.h>
75 76 #include <vm/seg.h>
76 77 #include <vm/page.h>
77 78 #include <vm/seg_kp.h>
78 79 #include <vm/seg_kpm.h>
79 80 #include <vm/vm_dep.h>
80 81 #ifdef __xpv
81 82 #include <sys/hypervisor.h>
82 83 #endif
83 84 #include <vm/kboot_mmu.h>
84 85 #include <vm/seg_spt.h>
85 86
86 87 #include <sys/cmn_err.h>
87 88
88 89 /*
89 90 * Basic parameters for hat operation.
90 91 */
91 92 struct hat_mmu_info mmu;
92 93
93 94 /*
94 95 * The page that is the kernel's top level pagetable.
95 96 *
96 97 * For 32 bit PAE support on i86pc, the kernel hat will use the 1st 4 entries
97 98 * on this 4K page for its top level page table. The remaining groups of
98 99 * 4 entries are used for per processor copies of user VLP pagetables for
99 100 * running threads. See hat_switch() and reload_pae32() for details.
100 101 *
101 102 * vlp_page[0..3] - level==2 PTEs for kernel HAT
102 103 * vlp_page[4..7] - level==2 PTEs for user thread on cpu 0
103 104 * vlp_page[8..11] - level==2 PTE for user thread on cpu 1
104 105 * etc...
105 106 */
106 107 static x86pte_t *vlp_page;
107 108
108 109 /*
109 110 * forward declaration of internal utility routines
110 111 */
111 112 static x86pte_t hati_update_pte(htable_t *ht, uint_t entry, x86pte_t expected,
112 113 x86pte_t new);
113 114
114 115 /*
115 116 * The kernel address space exists in all HATs. To implement this the
116 117 * kernel reserves a fixed number of entries in the topmost level(s) of page
117 118 * tables. The values are setup during startup and then copied to every user
118 119 * hat created by hat_alloc(). This means that kernelbase must be:
119 120 *
120 121 * 4Meg aligned for 32 bit kernels
121 122 * 512Gig aligned for x86_64 64 bit kernel
122 123 *
123 124 * The hat_kernel_range_ts describe what needs to be copied from kernel hat
124 125 * to each user hat.
125 126 */
126 127 typedef struct hat_kernel_range {
127 128 level_t hkr_level;
128 129 uintptr_t hkr_start_va;
129 130 uintptr_t hkr_end_va; /* zero means to end of memory */
130 131 } hat_kernel_range_t;
131 132 #define NUM_KERNEL_RANGE 2
132 133 static hat_kernel_range_t kernel_ranges[NUM_KERNEL_RANGE];
133 134 static int num_kernel_ranges;
134 135
135 136 uint_t use_boot_reserve = 1; /* cleared after early boot process */
136 137 uint_t can_steal_post_boot = 0; /* set late in boot to enable stealing */
137 138
138 139 /*
139 140 * enable_1gpg: controls 1g page support for user applications.
140 141 * By default, 1g pages are exported to user applications. enable_1gpg can
141 142 * be set to 0 to not export.
142 143 */
143 144 int enable_1gpg = 1;
144 145
145 146 /*
146 147 * AMD shanghai processors provide better management of 1gb ptes in its tlb.
147 148 * By default, 1g page support will be disabled for pre-shanghai AMD
148 149 * processors that don't have optimal tlb support for the 1g page size.
149 150 * chk_optimal_1gtlb can be set to 0 to force 1g page support on sub-optimal
150 151 * processors.
151 152 */
152 153 int chk_optimal_1gtlb = 1;
153 154
154 155
155 156 #ifdef DEBUG
156 157 uint_t map1gcnt;
157 158 #endif
158 159
159 160
160 161 /*
161 162 * A cpuset for all cpus. This is used for kernel address cross calls, since
162 163 * the kernel addresses apply to all cpus.
163 164 */
164 165 cpuset_t khat_cpuset;
165 166
166 167 /*
167 168 * management stuff for hat structures
168 169 */
169 170 kmutex_t hat_list_lock;
170 171 kcondvar_t hat_list_cv;
171 172 kmem_cache_t *hat_cache;
172 173 kmem_cache_t *hat_hash_cache;
173 174 kmem_cache_t *vlp_hash_cache;
174 175
175 176 /*
176 177 * Simple statistics
177 178 */
178 179 struct hatstats hatstat;
179 180
180 181 /*
181 182 * Some earlier hypervisor versions do not emulate cmpxchg of PTEs
182 183 * correctly. For such hypervisors we must set PT_USER for kernel
183 184 * entries ourselves (normally the emulation would set PT_USER for
184 185 * kernel entries and PT_USER|PT_GLOBAL for user entries). pt_kern is
185 186 * thus set appropriately. Note that dboot/kbm is OK, as only the full
186 187 * HAT uses cmpxchg() and the other paths (hypercall etc.) were never
187 188 * incorrect.
188 189 */
189 190 int pt_kern;
190 191
191 192 /*
192 193 * useful stuff for atomic access/clearing/setting REF/MOD/RO bits in page_t's.
193 194 */
194 195 extern void atomic_orb(uchar_t *addr, uchar_t val);
195 196 extern void atomic_andb(uchar_t *addr, uchar_t val);
196 197
197 198 #ifndef __xpv
198 199 extern pfn_t memseg_get_start(struct memseg *);
199 200 #endif
200 201
201 202 #define PP_GETRM(pp, rmmask) (pp->p_nrm & rmmask)
202 203 #define PP_ISMOD(pp) PP_GETRM(pp, P_MOD)
203 204 #define PP_ISREF(pp) PP_GETRM(pp, P_REF)
204 205 #define PP_ISRO(pp) PP_GETRM(pp, P_RO)
205 206
206 207 #define PP_SETRM(pp, rm) atomic_orb(&(pp->p_nrm), rm)
207 208 #define PP_SETMOD(pp) PP_SETRM(pp, P_MOD)
208 209 #define PP_SETREF(pp) PP_SETRM(pp, P_REF)
209 210 #define PP_SETRO(pp) PP_SETRM(pp, P_RO)
210 211
211 212 #define PP_CLRRM(pp, rm) atomic_andb(&(pp->p_nrm), ~(rm))
212 213 #define PP_CLRMOD(pp) PP_CLRRM(pp, P_MOD)
213 214 #define PP_CLRREF(pp) PP_CLRRM(pp, P_REF)
214 215 #define PP_CLRRO(pp) PP_CLRRM(pp, P_RO)
215 216 #define PP_CLRALL(pp) PP_CLRRM(pp, P_MOD | P_REF | P_RO)
216 217
217 218 /*
218 219 * kmem cache constructor for struct hat
219 220 */
220 221 /*ARGSUSED*/
221 222 static int
222 223 hati_constructor(void *buf, void *handle, int kmflags)
223 224 {
224 225 hat_t *hat = buf;
225 226
226 227 mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
227 228 bzero(hat->hat_pages_mapped,
228 229 sizeof (pgcnt_t) * (mmu.max_page_level + 1));
229 230 hat->hat_ism_pgcnt = 0;
230 231 hat->hat_stats = 0;
231 232 hat->hat_flags = 0;
232 233 CPUSET_ZERO(hat->hat_cpus);
233 234 hat->hat_htable = NULL;
234 235 hat->hat_ht_hash = NULL;
235 236 return (0);
236 237 }
237 238
238 239 /*
239 240 * Allocate a hat structure for as. We also create the top level
240 241 * htable and initialize it to contain the kernel hat entries.
241 242 */
242 243 hat_t *
243 244 hat_alloc(struct as *as)
244 245 {
245 246 hat_t *hat;
246 247 htable_t *ht; /* top level htable */
247 248 uint_t use_vlp;
248 249 uint_t r;
249 250 hat_kernel_range_t *rp;
250 251 uintptr_t va;
251 252 uintptr_t eva;
252 253 uint_t start;
253 254 uint_t cnt;
254 255 htable_t *src;
255 256
256 257 /*
257 258 * Once we start creating user process HATs we can enable
258 259 * the htable_steal() code.
259 260 */
260 261 if (can_steal_post_boot == 0)
261 262 can_steal_post_boot = 1;
262 263
263 264 ASSERT(AS_WRITE_HELD(as));
264 265 hat = kmem_cache_alloc(hat_cache, KM_SLEEP);
265 266 hat->hat_as = as;
266 267 mutex_init(&hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
267 268 ASSERT(hat->hat_flags == 0);
268 269
269 270 #if defined(__xpv)
270 271 /*
271 272 * No VLP stuff on the hypervisor due to the 64-bit split top level
272 273 * page tables. On 32-bit it's not needed as the hypervisor takes
273 274 * care of copying the top level PTEs to a below 4Gig page.
274 275 */
275 276 use_vlp = 0;
276 277 #else /* __xpv */
277 278 /* 32 bit processes uses a VLP style hat when running with PAE */
278 279 #if defined(__amd64)
279 280 use_vlp = (ttoproc(curthread)->p_model == DATAMODEL_ILP32);
280 281 #elif defined(__i386)
281 282 use_vlp = mmu.pae_hat;
282 283 #endif
283 284 #endif /* __xpv */
284 285 if (use_vlp) {
285 286 hat->hat_flags = HAT_VLP;
286 287 bzero(hat->hat_vlp_ptes, VLP_SIZE);
287 288 }
288 289
289 290 /*
290 291 * Allocate the htable hash
291 292 */
292 293 if ((hat->hat_flags & HAT_VLP)) {
293 294 hat->hat_num_hash = mmu.vlp_hash_cnt;
294 295 hat->hat_ht_hash = kmem_cache_alloc(vlp_hash_cache, KM_SLEEP);
295 296 } else {
296 297 hat->hat_num_hash = mmu.hash_cnt;
297 298 hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_SLEEP);
298 299 }
299 300 bzero(hat->hat_ht_hash, hat->hat_num_hash * sizeof (htable_t *));
300 301
301 302 /*
302 303 * Initialize Kernel HAT entries at the top of the top level page
303 304 * tables for the new hat.
304 305 */
305 306 hat->hat_htable = NULL;
306 307 hat->hat_ht_cached = NULL;
307 308 XPV_DISALLOW_MIGRATE();
308 309 ht = htable_create(hat, (uintptr_t)0, TOP_LEVEL(hat), NULL);
309 310 hat->hat_htable = ht;
310 311
311 312 #if defined(__amd64)
312 313 if (hat->hat_flags & HAT_VLP)
313 314 goto init_done;
314 315 #endif
315 316
316 317 for (r = 0; r < num_kernel_ranges; ++r) {
317 318 rp = &kernel_ranges[r];
318 319 for (va = rp->hkr_start_va; va != rp->hkr_end_va;
319 320 va += cnt * LEVEL_SIZE(rp->hkr_level)) {
320 321
321 322 if (rp->hkr_level == TOP_LEVEL(hat))
322 323 ht = hat->hat_htable;
323 324 else
324 325 ht = htable_create(hat, va, rp->hkr_level,
325 326 NULL);
326 327
327 328 start = htable_va2entry(va, ht);
328 329 cnt = HTABLE_NUM_PTES(ht) - start;
329 330 eva = va +
330 331 ((uintptr_t)cnt << LEVEL_SHIFT(rp->hkr_level));
331 332 if (rp->hkr_end_va != 0 &&
332 333 (eva > rp->hkr_end_va || eva == 0))
333 334 cnt = htable_va2entry(rp->hkr_end_va, ht) -
334 335 start;
335 336
336 337 #if defined(__i386) && !defined(__xpv)
337 338 if (ht->ht_flags & HTABLE_VLP) {
338 339 bcopy(&vlp_page[start],
339 340 &hat->hat_vlp_ptes[start],
340 341 cnt * sizeof (x86pte_t));
341 342 continue;
342 343 }
343 344 #endif
344 345 src = htable_lookup(kas.a_hat, va, rp->hkr_level);
345 346 ASSERT(src != NULL);
346 347 x86pte_copy(src, ht, start, cnt);
347 348 htable_release(src);
348 349 }
349 350 }
350 351
351 352 init_done:
352 353
353 354 #if defined(__xpv)
354 355 /*
355 356 * Pin top level page tables after initializing them
356 357 */
357 358 xen_pin(hat->hat_htable->ht_pfn, mmu.max_level);
358 359 #if defined(__amd64)
359 360 xen_pin(hat->hat_user_ptable, mmu.max_level);
360 361 #endif
361 362 #endif
362 363 XPV_ALLOW_MIGRATE();
363 364
364 365 /*
365 366 * Put it at the start of the global list of all hats (used by stealing)
366 367 *
367 368 * kas.a_hat is not in the list but is instead used to find the
368 369 * first and last items in the list.
369 370 *
370 371 * - kas.a_hat->hat_next points to the start of the user hats.
371 372 * The list ends where hat->hat_next == NULL
372 373 *
373 374 * - kas.a_hat->hat_prev points to the last of the user hats.
374 375 * The list begins where hat->hat_prev == NULL
375 376 */
376 377 mutex_enter(&hat_list_lock);
377 378 hat->hat_prev = NULL;
378 379 hat->hat_next = kas.a_hat->hat_next;
379 380 if (hat->hat_next)
380 381 hat->hat_next->hat_prev = hat;
381 382 else
382 383 kas.a_hat->hat_prev = hat;
383 384 kas.a_hat->hat_next = hat;
384 385 mutex_exit(&hat_list_lock);
385 386
386 387 return (hat);
387 388 }
388 389
389 390 /*
390 391 * process has finished executing but as has not been cleaned up yet.
391 392 */
392 393 /*ARGSUSED*/
393 394 void
394 395 hat_free_start(hat_t *hat)
395 396 {
396 397 ASSERT(AS_WRITE_HELD(hat->hat_as));
397 398
398 399 /*
399 400 * If the hat is currently a stealing victim, wait for the stealing
400 401 * to finish. Once we mark it as HAT_FREEING, htable_steal()
401 402 * won't look at its pagetables anymore.
402 403 */
403 404 mutex_enter(&hat_list_lock);
404 405 while (hat->hat_flags & HAT_VICTIM)
405 406 cv_wait(&hat_list_cv, &hat_list_lock);
406 407 hat->hat_flags |= HAT_FREEING;
407 408 mutex_exit(&hat_list_lock);
408 409 }
409 410
410 411 /*
411 412 * An address space is being destroyed, so we destroy the associated hat.
412 413 */
413 414 void
414 415 hat_free_end(hat_t *hat)
415 416 {
416 417 kmem_cache_t *cache;
417 418
418 419 ASSERT(hat->hat_flags & HAT_FREEING);
419 420
420 421 /*
421 422 * must not be running on the given hat
422 423 */
423 424 ASSERT(CPU->cpu_current_hat != hat);
424 425
425 426 /*
426 427 * Remove it from the list of HATs
427 428 */
428 429 mutex_enter(&hat_list_lock);
429 430 if (hat->hat_prev)
430 431 hat->hat_prev->hat_next = hat->hat_next;
431 432 else
432 433 kas.a_hat->hat_next = hat->hat_next;
433 434 if (hat->hat_next)
434 435 hat->hat_next->hat_prev = hat->hat_prev;
435 436 else
436 437 kas.a_hat->hat_prev = hat->hat_prev;
437 438 mutex_exit(&hat_list_lock);
438 439 hat->hat_next = hat->hat_prev = NULL;
439 440
440 441 #if defined(__xpv)
441 442 /*
442 443 * On the hypervisor, unpin top level page table(s)
443 444 */
444 445 xen_unpin(hat->hat_htable->ht_pfn);
445 446 #if defined(__amd64)
446 447 xen_unpin(hat->hat_user_ptable);
447 448 #endif
448 449 #endif
449 450
450 451 /*
451 452 * Make a pass through the htables freeing them all up.
452 453 */
453 454 htable_purge_hat(hat);
454 455
455 456 /*
456 457 * Decide which kmem cache the hash table came from, then free it.
457 458 */
458 459 if (hat->hat_flags & HAT_VLP)
459 460 cache = vlp_hash_cache;
460 461 else
461 462 cache = hat_hash_cache;
462 463 kmem_cache_free(cache, hat->hat_ht_hash);
463 464 hat->hat_ht_hash = NULL;
464 465
465 466 hat->hat_flags = 0;
466 467 kmem_cache_free(hat_cache, hat);
467 468 }
468 469
469 470 /*
470 471 * round kernelbase down to a supported value to use for _userlimit
471 472 *
472 473 * userlimit must be aligned down to an entry in the top level htable.
473 474 * The one exception is for 32 bit HAT's running PAE.
474 475 */
475 476 uintptr_t
476 477 hat_kernelbase(uintptr_t va)
477 478 {
478 479 #if defined(__i386)
479 480 va &= LEVEL_MASK(1);
480 481 #endif
481 482 if (IN_VA_HOLE(va))
482 483 panic("_userlimit %p will fall in VA hole\n", (void *)va);
483 484 return (va);
484 485 }
485 486
486 487 /*
487 488 *
488 489 */
489 490 static void
490 491 set_max_page_level()
491 492 {
492 493 level_t lvl;
493 494
494 495 if (!kbm_largepage_support) {
495 496 lvl = 0;
496 497 } else {
497 498 if (is_x86_feature(x86_featureset, X86FSET_1GPG)) {
498 499 lvl = 2;
499 500 if (chk_optimal_1gtlb &&
500 501 cpuid_opteron_erratum(CPU, 6671130)) {
501 502 lvl = 1;
502 503 }
503 504 if (plat_mnode_xcheck(LEVEL_SIZE(2) >>
504 505 LEVEL_SHIFT(0))) {
505 506 lvl = 1;
506 507 }
507 508 } else {
508 509 lvl = 1;
509 510 }
510 511 }
511 512 mmu.max_page_level = lvl;
512 513
513 514 if ((lvl == 2) && (enable_1gpg == 0))
514 515 mmu.umax_page_level = 1;
515 516 else
516 517 mmu.umax_page_level = lvl;
517 518 }
518 519
519 520 /*
520 521 * Initialize hat data structures based on processor MMU information.
521 522 */
522 523 void
523 524 mmu_init(void)
524 525 {
525 526 uint_t max_htables;
526 527 uint_t pa_bits;
527 528 uint_t va_bits;
528 529 int i;
529 530
530 531 /*
531 532 * If CPU enabled the page table global bit, use it for the kernel
532 533 * This is bit 7 in CR4 (PGE - Page Global Enable).
533 534 */
534 535 if (is_x86_feature(x86_featureset, X86FSET_PGE) &&
535 536 (getcr4() & CR4_PGE) != 0)
536 537 mmu.pt_global = PT_GLOBAL;
537 538
538 539 /*
539 540 * Detect NX and PAE usage.
540 541 */
541 542 mmu.pae_hat = kbm_pae_support;
542 543 if (kbm_nx_support)
543 544 mmu.pt_nx = PT_NX;
544 545 else
545 546 mmu.pt_nx = 0;
546 547
547 548 /*
548 549 * Use CPU info to set various MMU parameters
549 550 */
550 551 cpuid_get_addrsize(CPU, &pa_bits, &va_bits);
551 552
552 553 if (va_bits < sizeof (void *) * NBBY) {
553 554 mmu.hole_start = (1ul << (va_bits - 1));
554 555 mmu.hole_end = 0ul - mmu.hole_start - 1;
555 556 } else {
556 557 mmu.hole_end = 0;
557 558 mmu.hole_start = mmu.hole_end - 1;
558 559 }
559 560 #if defined(OPTERON_ERRATUM_121)
560 561 /*
561 562 * If erratum 121 has already been detected at this time, hole_start
562 563 * contains the value to be subtracted from mmu.hole_start.
563 564 */
564 565 ASSERT(hole_start == 0 || opteron_erratum_121 != 0);
565 566 hole_start = mmu.hole_start - hole_start;
566 567 #else
567 568 hole_start = mmu.hole_start;
568 569 #endif
569 570 hole_end = mmu.hole_end;
570 571
571 572 mmu.highest_pfn = mmu_btop((1ull << pa_bits) - 1);
572 573 if (mmu.pae_hat == 0 && pa_bits > 32)
573 574 mmu.highest_pfn = PFN_4G - 1;
574 575
575 576 if (mmu.pae_hat) {
576 577 mmu.pte_size = 8; /* 8 byte PTEs */
577 578 mmu.pte_size_shift = 3;
578 579 } else {
579 580 mmu.pte_size = 4; /* 4 byte PTEs */
580 581 mmu.pte_size_shift = 2;
581 582 }
582 583
583 584 if (mmu.pae_hat && !is_x86_feature(x86_featureset, X86FSET_PAE))
584 585 panic("Processor does not support PAE");
585 586
586 587 if (!is_x86_feature(x86_featureset, X86FSET_CX8))
587 588 panic("Processor does not support cmpxchg8b instruction");
588 589
589 590 #if defined(__amd64)
590 591
591 592 mmu.num_level = 4;
592 593 mmu.max_level = 3;
593 594 mmu.ptes_per_table = 512;
594 595 mmu.top_level_count = 512;
595 596
596 597 mmu.level_shift[0] = 12;
597 598 mmu.level_shift[1] = 21;
598 599 mmu.level_shift[2] = 30;
599 600 mmu.level_shift[3] = 39;
600 601
601 602 #elif defined(__i386)
602 603
603 604 if (mmu.pae_hat) {
604 605 mmu.num_level = 3;
605 606 mmu.max_level = 2;
606 607 mmu.ptes_per_table = 512;
607 608 mmu.top_level_count = 4;
608 609
609 610 mmu.level_shift[0] = 12;
610 611 mmu.level_shift[1] = 21;
611 612 mmu.level_shift[2] = 30;
612 613
613 614 } else {
614 615 mmu.num_level = 2;
615 616 mmu.max_level = 1;
616 617 mmu.ptes_per_table = 1024;
617 618 mmu.top_level_count = 1024;
618 619
619 620 mmu.level_shift[0] = 12;
620 621 mmu.level_shift[1] = 22;
621 622 }
622 623
623 624 #endif /* __i386 */
624 625
625 626 for (i = 0; i < mmu.num_level; ++i) {
626 627 mmu.level_size[i] = 1UL << mmu.level_shift[i];
627 628 mmu.level_offset[i] = mmu.level_size[i] - 1;
628 629 mmu.level_mask[i] = ~mmu.level_offset[i];
629 630 }
630 631
631 632 set_max_page_level();
632 633
633 634 mmu_page_sizes = mmu.max_page_level + 1;
634 635 mmu_exported_page_sizes = mmu.umax_page_level + 1;
635 636
636 637 /* restrict legacy applications from using pagesizes 1g and above */
637 638 mmu_legacy_page_sizes =
638 639 (mmu_exported_page_sizes > 2) ? 2 : mmu_exported_page_sizes;
639 640
640 641
641 642 for (i = 0; i <= mmu.max_page_level; ++i) {
642 643 mmu.pte_bits[i] = PT_VALID | pt_kern;
643 644 if (i > 0)
644 645 mmu.pte_bits[i] |= PT_PAGESIZE;
645 646 }
646 647
647 648 /*
648 649 * NOTE Legacy 32 bit PAE mode only has the P_VALID bit at top level.
649 650 */
650 651 for (i = 1; i < mmu.num_level; ++i)
651 652 mmu.ptp_bits[i] = PT_PTPBITS;
652 653
653 654 #if defined(__i386)
654 655 mmu.ptp_bits[2] = PT_VALID;
655 656 #endif
656 657
657 658 /*
658 659 * Compute how many hash table entries to have per process for htables.
659 660 * We start with 1 page's worth of entries.
660 661 *
661 662 * If physical memory is small, reduce the amount need to cover it.
662 663 */
663 664 max_htables = physmax / mmu.ptes_per_table;
664 665 mmu.hash_cnt = MMU_PAGESIZE / sizeof (htable_t *);
665 666 while (mmu.hash_cnt > 16 && mmu.hash_cnt >= max_htables)
666 667 mmu.hash_cnt >>= 1;
667 668 mmu.vlp_hash_cnt = mmu.hash_cnt;
668 669
669 670 #if defined(__amd64)
670 671 /*
671 672 * If running in 64 bits and physical memory is large,
672 673 * increase the size of the cache to cover all of memory for
673 674 * a 64 bit process.
674 675 */
675 676 #define HASH_MAX_LENGTH 4
676 677 while (mmu.hash_cnt * HASH_MAX_LENGTH < max_htables)
677 678 mmu.hash_cnt <<= 1;
678 679 #endif
679 680 }
680 681
681 682
682 683 /*
683 684 * initialize hat data structures
684 685 */
685 686 void
686 687 hat_init()
687 688 {
688 689 #if defined(__i386)
689 690 /*
690 691 * _userlimit must be aligned correctly
691 692 */
692 693 if ((_userlimit & LEVEL_MASK(1)) != _userlimit) {
693 694 prom_printf("hat_init(): _userlimit=%p, not aligned at %p\n",
694 695 (void *)_userlimit, (void *)LEVEL_SIZE(1));
695 696 halt("hat_init(): Unable to continue");
696 697 }
697 698 #endif
698 699
699 700 cv_init(&hat_list_cv, NULL, CV_DEFAULT, NULL);
700 701
701 702 /*
702 703 * initialize kmem caches
703 704 */
704 705 htable_init();
705 706 hment_init();
706 707
707 708 hat_cache = kmem_cache_create("hat_t",
708 709 sizeof (hat_t), 0, hati_constructor, NULL, NULL,
709 710 NULL, 0, 0);
710 711
711 712 hat_hash_cache = kmem_cache_create("HatHash",
712 713 mmu.hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL,
713 714 NULL, 0, 0);
714 715
715 716 /*
716 717 * VLP hats can use a smaller hash table size on large memroy machines
717 718 */
718 719 if (mmu.hash_cnt == mmu.vlp_hash_cnt) {
719 720 vlp_hash_cache = hat_hash_cache;
720 721 } else {
721 722 vlp_hash_cache = kmem_cache_create("HatVlpHash",
722 723 mmu.vlp_hash_cnt * sizeof (htable_t *), 0, NULL, NULL, NULL,
723 724 NULL, 0, 0);
724 725 }
725 726
726 727 /*
727 728 * Set up the kernel's hat
728 729 */
729 730 AS_LOCK_ENTER(&kas, RW_WRITER);
730 731 kas.a_hat = kmem_cache_alloc(hat_cache, KM_NOSLEEP);
731 732 mutex_init(&kas.a_hat->hat_mutex, NULL, MUTEX_DEFAULT, NULL);
732 733 kas.a_hat->hat_as = &kas;
733 734 kas.a_hat->hat_flags = 0;
734 735 AS_LOCK_EXIT(&kas);
735 736
736 737 CPUSET_ZERO(khat_cpuset);
737 738 CPUSET_ADD(khat_cpuset, CPU->cpu_id);
738 739
739 740 /*
740 741 * The kernel hat's next pointer serves as the head of the hat list .
741 742 * The kernel hat's prev pointer tracks the last hat on the list for
742 743 * htable_steal() to use.
743 744 */
744 745 kas.a_hat->hat_next = NULL;
745 746 kas.a_hat->hat_prev = NULL;
746 747
747 748 /*
748 749 * Allocate an htable hash bucket for the kernel
749 750 * XX64 - tune for 64 bit procs
750 751 */
751 752 kas.a_hat->hat_num_hash = mmu.hash_cnt;
752 753 kas.a_hat->hat_ht_hash = kmem_cache_alloc(hat_hash_cache, KM_NOSLEEP);
753 754 bzero(kas.a_hat->hat_ht_hash, mmu.hash_cnt * sizeof (htable_t *));
754 755
755 756 /*
756 757 * zero out the top level and cached htable pointers
757 758 */
758 759 kas.a_hat->hat_ht_cached = NULL;
759 760 kas.a_hat->hat_htable = NULL;
760 761
761 762 /*
762 763 * Pre-allocate hrm_hashtab before enabling the collection of
763 764 * refmod statistics. Allocating on the fly would mean us
764 765 * running the risk of suffering recursive mutex enters or
765 766 * deadlocks.
766 767 */
767 768 hrm_hashtab = kmem_zalloc(HRM_HASHSIZE * sizeof (struct hrmstat *),
768 769 KM_SLEEP);
769 770 }
770 771
771 772 /*
772 773 * Prepare CPU specific pagetables for VLP processes on 64 bit kernels.
773 774 *
774 775 * Each CPU has a set of 2 pagetables that are reused for any 32 bit
775 776 * process it runs. They are the top level pagetable, hci_vlp_l3ptes, and
776 777 * the next to top level table for the bottom 512 Gig, hci_vlp_l2ptes.
777 778 */
778 779 /*ARGSUSED*/
779 780 static void
780 781 hat_vlp_setup(struct cpu *cpu)
781 782 {
782 783 #if defined(__amd64) && !defined(__xpv)
783 784 struct hat_cpu_info *hci = cpu->cpu_hat_info;
784 785 pfn_t pfn;
785 786
786 787 /*
787 788 * allocate the level==2 page table for the bottom most
788 789 * 512Gig of address space (this is where 32 bit apps live)
789 790 */
790 791 ASSERT(hci != NULL);
791 792 hci->hci_vlp_l2ptes = kmem_zalloc(MMU_PAGESIZE, KM_SLEEP);
792 793
793 794 /*
794 795 * Allocate a top level pagetable and copy the kernel's
795 796 * entries into it. Then link in hci_vlp_l2ptes in the 1st entry.
796 797 */
797 798 hci->hci_vlp_l3ptes = kmem_zalloc(MMU_PAGESIZE, KM_SLEEP);
798 799 hci->hci_vlp_pfn =
799 800 hat_getpfnum(kas.a_hat, (caddr_t)hci->hci_vlp_l3ptes);
800 801 ASSERT(hci->hci_vlp_pfn != PFN_INVALID);
801 802 bcopy(vlp_page, hci->hci_vlp_l3ptes, MMU_PAGESIZE);
802 803
803 804 pfn = hat_getpfnum(kas.a_hat, (caddr_t)hci->hci_vlp_l2ptes);
804 805 ASSERT(pfn != PFN_INVALID);
805 806 hci->hci_vlp_l3ptes[0] = MAKEPTP(pfn, 2);
806 807 #endif /* __amd64 && !__xpv */
807 808 }
808 809
809 810 /*ARGSUSED*/
810 811 static void
811 812 hat_vlp_teardown(cpu_t *cpu)
812 813 {
813 814 #if defined(__amd64) && !defined(__xpv)
814 815 struct hat_cpu_info *hci;
815 816
816 817 if ((hci = cpu->cpu_hat_info) == NULL)
817 818 return;
818 819 if (hci->hci_vlp_l2ptes)
819 820 kmem_free(hci->hci_vlp_l2ptes, MMU_PAGESIZE);
820 821 if (hci->hci_vlp_l3ptes)
821 822 kmem_free(hci->hci_vlp_l3ptes, MMU_PAGESIZE);
822 823 #endif
823 824 }
824 825
825 826 #define NEXT_HKR(r, l, s, e) { \
826 827 kernel_ranges[r].hkr_level = l; \
827 828 kernel_ranges[r].hkr_start_va = s; \
828 829 kernel_ranges[r].hkr_end_va = e; \
829 830 ++r; \
830 831 }
831 832
832 833 /*
833 834 * Finish filling in the kernel hat.
834 835 * Pre fill in all top level kernel page table entries for the kernel's
835 836 * part of the address range. From this point on we can't use any new
836 837 * kernel large pages if they need PTE's at max_level
837 838 *
838 839 * create the kmap mappings.
839 840 */
840 841 void
841 842 hat_init_finish(void)
842 843 {
843 844 size_t size;
844 845 uint_t r = 0;
845 846 uintptr_t va;
846 847 hat_kernel_range_t *rp;
847 848
848 849
849 850 /*
850 851 * We are now effectively running on the kernel hat.
851 852 * Clearing use_boot_reserve shuts off using the pre-allocated boot
852 853 * reserve for all HAT allocations. From here on, the reserves are
853 854 * only used when avoiding recursion in kmem_alloc().
854 855 */
855 856 use_boot_reserve = 0;
856 857 htable_adjust_reserve();
857 858
858 859 /*
859 860 * User HATs are initialized with copies of all kernel mappings in
860 861 * higher level page tables. Ensure that those entries exist.
861 862 */
862 863 #if defined(__amd64)
863 864
864 865 NEXT_HKR(r, 3, kernelbase, 0);
865 866 #if defined(__xpv)
866 867 NEXT_HKR(r, 3, HYPERVISOR_VIRT_START, HYPERVISOR_VIRT_END);
867 868 #endif
868 869
869 870 #elif defined(__i386)
870 871
871 872 #if !defined(__xpv)
872 873 if (mmu.pae_hat) {
873 874 va = kernelbase;
874 875 if ((va & LEVEL_MASK(2)) != va) {
875 876 va = P2ROUNDUP(va, LEVEL_SIZE(2));
876 877 NEXT_HKR(r, 1, kernelbase, va);
877 878 }
878 879 if (va != 0)
879 880 NEXT_HKR(r, 2, va, 0);
880 881 } else
881 882 #endif /* __xpv */
882 883 NEXT_HKR(r, 1, kernelbase, 0);
883 884
884 885 #endif /* __i386 */
885 886
886 887 num_kernel_ranges = r;
887 888
888 889 /*
889 890 * Create all the kernel pagetables that will have entries
890 891 * shared to user HATs.
891 892 */
892 893 for (r = 0; r < num_kernel_ranges; ++r) {
893 894 rp = &kernel_ranges[r];
894 895 for (va = rp->hkr_start_va; va != rp->hkr_end_va;
895 896 va += LEVEL_SIZE(rp->hkr_level)) {
896 897 htable_t *ht;
897 898
898 899 if (IN_HYPERVISOR_VA(va))
899 900 continue;
900 901
901 902 /* can/must skip if a page mapping already exists */
902 903 if (rp->hkr_level <= mmu.max_page_level &&
903 904 (ht = htable_getpage(kas.a_hat, va, NULL)) !=
904 905 NULL) {
905 906 htable_release(ht);
906 907 continue;
907 908 }
908 909
909 910 (void) htable_create(kas.a_hat, va, rp->hkr_level - 1,
910 911 NULL);
911 912 }
912 913 }
913 914
914 915 /*
915 916 * 32 bit PAE metal kernels use only 4 of the 512 entries in the
916 917 * page holding the top level pagetable. We use the remainder for
917 918 * the "per CPU" page tables for VLP processes.
918 919 * Map the top level kernel pagetable into the kernel to make
919 920 * it easy to use bcopy access these tables.
920 921 */
921 922 if (mmu.pae_hat) {
922 923 vlp_page = vmem_alloc(heap_arena, MMU_PAGESIZE, VM_SLEEP);
923 924 hat_devload(kas.a_hat, (caddr_t)vlp_page, MMU_PAGESIZE,
924 925 kas.a_hat->hat_htable->ht_pfn,
925 926 #if !defined(__xpv)
926 927 PROT_WRITE |
927 928 #endif
928 929 PROT_READ | HAT_NOSYNC | HAT_UNORDERED_OK,
929 930 HAT_LOAD | HAT_LOAD_NOCONSIST);
930 931 }
931 932 hat_vlp_setup(CPU);
932 933
933 934 /*
934 935 * Create kmap (cached mappings of kernel PTEs)
935 936 * for 32 bit we map from segmap_start .. ekernelheap
936 937 * for 64 bit we map from segmap_start .. segmap_start + segmapsize;
937 938 */
938 939 #if defined(__i386)
939 940 size = (uintptr_t)ekernelheap - segmap_start;
940 941 #elif defined(__amd64)
941 942 size = segmapsize;
942 943 #endif
943 944 hat_kmap_init((uintptr_t)segmap_start, size);
944 945 }
945 946
946 947 /*
947 948 * On 32 bit PAE mode, PTE's are 64 bits, but ordinary atomic memory references
948 949 * are 32 bit, so for safety we must use atomic_cas_64() to install these.
949 950 */
950 951 #ifdef __i386
951 952 static void
952 953 reload_pae32(hat_t *hat, cpu_t *cpu)
953 954 {
954 955 x86pte_t *src;
955 956 x86pte_t *dest;
956 957 x86pte_t pte;
957 958 int i;
958 959
959 960 /*
960 961 * Load the 4 entries of the level 2 page table into this
961 962 * cpu's range of the vlp_page and point cr3 at them.
962 963 */
963 964 ASSERT(mmu.pae_hat);
964 965 src = hat->hat_vlp_ptes;
965 966 dest = vlp_page + (cpu->cpu_id + 1) * VLP_NUM_PTES;
966 967 for (i = 0; i < VLP_NUM_PTES; ++i) {
967 968 for (;;) {
968 969 pte = dest[i];
969 970 if (pte == src[i])
970 971 break;
971 972 if (atomic_cas_64(dest + i, pte, src[i]) != src[i])
972 973 break;
973 974 }
974 975 }
975 976 }
976 977 #endif
977 978
978 979 /*
979 980 * Switch to a new active hat, maintaining bit masks to track active CPUs.
980 981 *
981 982 * On the 32-bit PAE hypervisor, %cr3 is a 64-bit value, on metal it
982 983 * remains a 32-bit value.
983 984 */
984 985 void
985 986 hat_switch(hat_t *hat)
986 987 {
987 988 uint64_t newcr3;
988 989 cpu_t *cpu = CPU;
989 990 hat_t *old = cpu->cpu_current_hat;
990 991
991 992 /*
992 993 * set up this information first, so we don't miss any cross calls
993 994 */
994 995 if (old != NULL) {
995 996 if (old == hat)
996 997 return;
997 998 if (old != kas.a_hat)
998 999 CPUSET_ATOMIC_DEL(old->hat_cpus, cpu->cpu_id);
999 1000 }
1000 1001
1001 1002 /*
1002 1003 * Add this CPU to the active set for this HAT.
1003 1004 */
1004 1005 if (hat != kas.a_hat) {
1005 1006 CPUSET_ATOMIC_ADD(hat->hat_cpus, cpu->cpu_id);
1006 1007 }
1007 1008 cpu->cpu_current_hat = hat;
1008 1009
1009 1010 /*
1010 1011 * now go ahead and load cr3
1011 1012 */
1012 1013 if (hat->hat_flags & HAT_VLP) {
1013 1014 #if defined(__amd64)
1014 1015 x86pte_t *vlpptep = cpu->cpu_hat_info->hci_vlp_l2ptes;
1015 1016
1016 1017 VLP_COPY(hat->hat_vlp_ptes, vlpptep);
1017 1018 newcr3 = MAKECR3(cpu->cpu_hat_info->hci_vlp_pfn);
1018 1019 #elif defined(__i386)
1019 1020 reload_pae32(hat, cpu);
1020 1021 newcr3 = MAKECR3(kas.a_hat->hat_htable->ht_pfn) +
1021 1022 (cpu->cpu_id + 1) * VLP_SIZE;
1022 1023 #endif
1023 1024 } else {
1024 1025 newcr3 = MAKECR3((uint64_t)hat->hat_htable->ht_pfn);
1025 1026 }
1026 1027 #ifdef __xpv
1027 1028 {
1028 1029 struct mmuext_op t[2];
1029 1030 uint_t retcnt;
1030 1031 uint_t opcnt = 1;
1031 1032
1032 1033 t[0].cmd = MMUEXT_NEW_BASEPTR;
1033 1034 t[0].arg1.mfn = mmu_btop(pa_to_ma(newcr3));
1034 1035 #if defined(__amd64)
1035 1036 /*
1036 1037 * There's an interesting problem here, as to what to
1037 1038 * actually specify when switching to the kernel hat.
1038 1039 * For now we'll reuse the kernel hat again.
1039 1040 */
1040 1041 t[1].cmd = MMUEXT_NEW_USER_BASEPTR;
1041 1042 if (hat == kas.a_hat)
1042 1043 t[1].arg1.mfn = mmu_btop(pa_to_ma(newcr3));
1043 1044 else
1044 1045 t[1].arg1.mfn = pfn_to_mfn(hat->hat_user_ptable);
1045 1046 ++opcnt;
1046 1047 #endif /* __amd64 */
1047 1048 if (HYPERVISOR_mmuext_op(t, opcnt, &retcnt, DOMID_SELF) < 0)
1048 1049 panic("HYPERVISOR_mmu_update() failed");
1049 1050 ASSERT(retcnt == opcnt);
1050 1051
1051 1052 }
1052 1053 #else
1053 1054 setcr3(newcr3);
1054 1055 #endif
1055 1056 ASSERT(cpu == CPU);
1056 1057 }
1057 1058
1058 1059 /*
1059 1060 * Utility to return a valid x86pte_t from protections, pfn, and level number
1060 1061 */
1061 1062 static x86pte_t
1062 1063 hati_mkpte(pfn_t pfn, uint_t attr, level_t level, uint_t flags)
1063 1064 {
1064 1065 x86pte_t pte;
1065 1066 uint_t cache_attr = attr & HAT_ORDER_MASK;
1066 1067
1067 1068 pte = MAKEPTE(pfn, level);
1068 1069
1069 1070 if (attr & PROT_WRITE)
1070 1071 PTE_SET(pte, PT_WRITABLE);
1071 1072
1072 1073 if (attr & PROT_USER)
1073 1074 PTE_SET(pte, PT_USER);
1074 1075
1075 1076 if (!(attr & PROT_EXEC))
1076 1077 PTE_SET(pte, mmu.pt_nx);
1077 1078
1078 1079 /*
1079 1080 * Set the software bits used track ref/mod sync's and hments.
1080 1081 * If not using REF/MOD, set them to avoid h/w rewriting PTEs.
1081 1082 */
1082 1083 if (flags & HAT_LOAD_NOCONSIST)
1083 1084 PTE_SET(pte, PT_NOCONSIST | PT_REF | PT_MOD);
1084 1085 else if (attr & HAT_NOSYNC)
1085 1086 PTE_SET(pte, PT_NOSYNC | PT_REF | PT_MOD);
1086 1087
1087 1088 /*
1088 1089 * Set the caching attributes in the PTE. The combination
1089 1090 * of attributes are poorly defined, so we pay attention
1090 1091 * to them in the given order.
1091 1092 *
1092 1093 * The test for HAT_STRICTORDER is different because it's defined
1093 1094 * as "0" - which was a stupid thing to do, but is too late to change!
1094 1095 */
1095 1096 if (cache_attr == HAT_STRICTORDER) {
1096 1097 PTE_SET(pte, PT_NOCACHE);
1097 1098 /*LINTED [Lint hates empty ifs, but it's the obvious way to do this] */
1098 1099 } else if (cache_attr & (HAT_UNORDERED_OK | HAT_STORECACHING_OK)) {
1099 1100 /* nothing to set */;
1100 1101 } else if (cache_attr & (HAT_MERGING_OK | HAT_LOADCACHING_OK)) {
1101 1102 PTE_SET(pte, PT_NOCACHE);
1102 1103 if (is_x86_feature(x86_featureset, X86FSET_PAT))
1103 1104 PTE_SET(pte, (level == 0) ? PT_PAT_4K : PT_PAT_LARGE);
1104 1105 else
1105 1106 PTE_SET(pte, PT_WRITETHRU);
1106 1107 } else {
1107 1108 panic("hati_mkpte(): bad caching attributes: %x\n", cache_attr);
1108 1109 }
1109 1110
1110 1111 return (pte);
1111 1112 }
1112 1113
1113 1114 /*
1114 1115 * Duplicate address translations of the parent to the child.
1115 1116 * This function really isn't used anymore.
1116 1117 */
1117 1118 /*ARGSUSED*/
1118 1119 int
1119 1120 hat_dup(hat_t *old, hat_t *new, caddr_t addr, size_t len, uint_t flag)
1120 1121 {
1121 1122 ASSERT((uintptr_t)addr < kernelbase);
1122 1123 ASSERT(new != kas.a_hat);
1123 1124 ASSERT(old != kas.a_hat);
1124 1125 return (0);
1125 1126 }
1126 1127
1127 1128 /*
1128 1129 * Allocate any hat resources required for a process being swapped in.
1129 1130 */
1130 1131 /*ARGSUSED*/
1131 1132 void
1132 1133 hat_swapin(hat_t *hat)
1133 1134 {
1134 1135 /* do nothing - we let everything fault back in */
1135 1136 }
1136 1137
1137 1138 /*
1138 1139 * Unload all translations associated with an address space of a process
1139 1140 * that is being swapped out.
1140 1141 */
1141 1142 void
1142 1143 hat_swapout(hat_t *hat)
1143 1144 {
1144 1145 uintptr_t vaddr = (uintptr_t)0;
1145 1146 uintptr_t eaddr = _userlimit;
1146 1147 htable_t *ht = NULL;
1147 1148 level_t l;
1148 1149
1149 1150 XPV_DISALLOW_MIGRATE();
1150 1151 /*
1151 1152 * We can't just call hat_unload(hat, 0, _userlimit...) here, because
1152 1153 * seg_spt and shared pagetables can't be swapped out.
1153 1154 * Take a look at segspt_shmswapout() - it's a big no-op.
1154 1155 *
1155 1156 * Instead we'll walk through all the address space and unload
1156 1157 * any mappings which we are sure are not shared, not locked.
1157 1158 */
1158 1159 ASSERT(IS_PAGEALIGNED(vaddr));
1159 1160 ASSERT(IS_PAGEALIGNED(eaddr));
1160 1161 ASSERT(AS_LOCK_HELD(hat->hat_as));
1161 1162 if ((uintptr_t)hat->hat_as->a_userlimit < eaddr)
1162 1163 eaddr = (uintptr_t)hat->hat_as->a_userlimit;
1163 1164
1164 1165 while (vaddr < eaddr) {
1165 1166 (void) htable_walk(hat, &ht, &vaddr, eaddr);
1166 1167 if (ht == NULL)
1167 1168 break;
1168 1169
1169 1170 ASSERT(!IN_VA_HOLE(vaddr));
1170 1171
1171 1172 /*
1172 1173 * If the page table is shared skip its entire range.
1173 1174 */
1174 1175 l = ht->ht_level;
1175 1176 if (ht->ht_flags & HTABLE_SHARED_PFN) {
1176 1177 vaddr = ht->ht_vaddr + LEVEL_SIZE(l + 1);
1177 1178 htable_release(ht);
1178 1179 ht = NULL;
1179 1180 continue;
1180 1181 }
1181 1182
1182 1183 /*
1183 1184 * If the page table has no locked entries, unload this one.
1184 1185 */
1185 1186 if (ht->ht_lock_cnt == 0)
1186 1187 hat_unload(hat, (caddr_t)vaddr, LEVEL_SIZE(l),
1187 1188 HAT_UNLOAD_UNMAP);
1188 1189
1189 1190 /*
1190 1191 * If we have a level 0 page table with locked entries,
1191 1192 * skip the entire page table, otherwise skip just one entry.
1192 1193 */
1193 1194 if (ht->ht_lock_cnt > 0 && l == 0)
1194 1195 vaddr = ht->ht_vaddr + LEVEL_SIZE(1);
1195 1196 else
1196 1197 vaddr += LEVEL_SIZE(l);
1197 1198 }
1198 1199 if (ht)
1199 1200 htable_release(ht);
1200 1201
1201 1202 /*
1202 1203 * We're in swapout because the system is low on memory, so
1203 1204 * go back and flush all the htables off the cached list.
1204 1205 */
1205 1206 htable_purge_hat(hat);
1206 1207 XPV_ALLOW_MIGRATE();
1207 1208 }
1208 1209
1209 1210 /*
1210 1211 * returns number of bytes that have valid mappings in hat.
1211 1212 */
1212 1213 size_t
1213 1214 hat_get_mapped_size(hat_t *hat)
1214 1215 {
1215 1216 size_t total = 0;
1216 1217 int l;
1217 1218
1218 1219 for (l = 0; l <= mmu.max_page_level; l++)
1219 1220 total += (hat->hat_pages_mapped[l] << LEVEL_SHIFT(l));
1220 1221 total += hat->hat_ism_pgcnt;
1221 1222
1222 1223 return (total);
1223 1224 }
1224 1225
1225 1226 /*
1226 1227 * enable/disable collection of stats for hat.
1227 1228 */
1228 1229 int
1229 1230 hat_stats_enable(hat_t *hat)
1230 1231 {
1231 1232 atomic_inc_32(&hat->hat_stats);
1232 1233 return (1);
1233 1234 }
1234 1235
1235 1236 void
1236 1237 hat_stats_disable(hat_t *hat)
1237 1238 {
1238 1239 atomic_dec_32(&hat->hat_stats);
1239 1240 }
1240 1241
1241 1242 /*
1242 1243 * Utility to sync the ref/mod bits from a page table entry to the page_t
1243 1244 * We must be holding the mapping list lock when this is called.
1244 1245 */
1245 1246 static void
1246 1247 hati_sync_pte_to_page(page_t *pp, x86pte_t pte, level_t level)
1247 1248 {
1248 1249 uint_t rm = 0;
1249 1250 pgcnt_t pgcnt;
1250 1251
1251 1252 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC)
1252 1253 return;
1253 1254
1254 1255 if (PTE_GET(pte, PT_REF))
1255 1256 rm |= P_REF;
1256 1257
1257 1258 if (PTE_GET(pte, PT_MOD))
1258 1259 rm |= P_MOD;
1259 1260
1260 1261 if (rm == 0)
1261 1262 return;
1262 1263
1263 1264 /*
1264 1265 * sync to all constituent pages of a large page
1265 1266 */
1266 1267 ASSERT(x86_hm_held(pp));
1267 1268 pgcnt = page_get_pagecnt(level);
1268 1269 ASSERT(IS_P2ALIGNED(pp->p_pagenum, pgcnt));
1269 1270 for (; pgcnt > 0; --pgcnt) {
1270 1271 /*
1271 1272 * hat_page_demote() can't decrease
1272 1273 * pszc below this mapping size
1273 1274 * since this large mapping existed after we
1274 1275 * took mlist lock.
1275 1276 */
1276 1277 ASSERT(pp->p_szc >= level);
1277 1278 hat_page_setattr(pp, rm);
1278 1279 ++pp;
1279 1280 }
1280 1281 }
1281 1282
1282 1283 /*
1283 1284 * This the set of PTE bits for PFN, permissions and caching
1284 1285 * that are allowed to change on a HAT_LOAD_REMAP
1285 1286 */
1286 1287 #define PT_REMAP_BITS \
1287 1288 (PT_PADDR | PT_NX | PT_WRITABLE | PT_WRITETHRU | \
1288 1289 PT_NOCACHE | PT_PAT_4K | PT_PAT_LARGE | PT_IGNORE | PT_REF | PT_MOD)
1289 1290
1290 1291 #define REMAPASSERT(EX) if (!(EX)) panic("hati_pte_map: " #EX)
1291 1292 /*
1292 1293 * Do the low-level work to get a mapping entered into a HAT's pagetables
1293 1294 * and in the mapping list of the associated page_t.
1294 1295 */
1295 1296 static int
1296 1297 hati_pte_map(
1297 1298 htable_t *ht,
1298 1299 uint_t entry,
1299 1300 page_t *pp,
1300 1301 x86pte_t pte,
1301 1302 int flags,
1302 1303 void *pte_ptr)
1303 1304 {
1304 1305 hat_t *hat = ht->ht_hat;
1305 1306 x86pte_t old_pte;
1306 1307 level_t l = ht->ht_level;
1307 1308 hment_t *hm;
1308 1309 uint_t is_consist;
1309 1310 uint_t is_locked;
1310 1311 int rv = 0;
1311 1312
1312 1313 /*
1313 1314 * Is this a consistent (ie. need mapping list lock) mapping?
1314 1315 */
1315 1316 is_consist = (pp != NULL && (flags & HAT_LOAD_NOCONSIST) == 0);
1316 1317
1317 1318 /*
1318 1319 * Track locked mapping count in the htable. Do this first,
1319 1320 * as we track locking even if there already is a mapping present.
1320 1321 */
1321 1322 is_locked = (flags & HAT_LOAD_LOCK) != 0 && hat != kas.a_hat;
1322 1323 if (is_locked)
1323 1324 HTABLE_LOCK_INC(ht);
1324 1325
1325 1326 /*
1326 1327 * Acquire the page's mapping list lock and get an hment to use.
1327 1328 * Note that hment_prepare() might return NULL.
1328 1329 */
1329 1330 if (is_consist) {
1330 1331 x86_hm_enter(pp);
1331 1332 hm = hment_prepare(ht, entry, pp);
1332 1333 }
1333 1334
1334 1335 /*
1335 1336 * Set the new pte, retrieving the old one at the same time.
1336 1337 */
1337 1338 old_pte = x86pte_set(ht, entry, pte, pte_ptr);
1338 1339
1339 1340 /*
1340 1341 * Did we get a large page / page table collision?
1341 1342 */
1342 1343 if (old_pte == LPAGE_ERROR) {
1343 1344 if (is_locked)
1344 1345 HTABLE_LOCK_DEC(ht);
1345 1346 rv = -1;
1346 1347 goto done;
1347 1348 }
1348 1349
1349 1350 /*
1350 1351 * If the mapping didn't change there is nothing more to do.
1351 1352 */
1352 1353 if (PTE_EQUIV(pte, old_pte))
1353 1354 goto done;
1354 1355
1355 1356 /*
1356 1357 * Install a new mapping in the page's mapping list
1357 1358 */
1358 1359 if (!PTE_ISVALID(old_pte)) {
1359 1360 if (is_consist) {
1360 1361 hment_assign(ht, entry, pp, hm);
1361 1362 x86_hm_exit(pp);
1362 1363 } else {
1363 1364 ASSERT(flags & HAT_LOAD_NOCONSIST);
1364 1365 }
1365 1366 #if defined(__amd64)
1366 1367 if (ht->ht_flags & HTABLE_VLP) {
1367 1368 cpu_t *cpu = CPU;
1368 1369 x86pte_t *vlpptep = cpu->cpu_hat_info->hci_vlp_l2ptes;
1369 1370 VLP_COPY(hat->hat_vlp_ptes, vlpptep);
1370 1371 }
1371 1372 #endif
1372 1373 HTABLE_INC(ht->ht_valid_cnt);
1373 1374 PGCNT_INC(hat, l);
1374 1375 return (rv);
1375 1376 }
1376 1377
1377 1378 /*
1378 1379 * Remap's are more complicated:
1379 1380 * - HAT_LOAD_REMAP must be specified if changing the pfn.
1380 1381 * We also require that NOCONSIST be specified.
1381 1382 * - Otherwise only permission or caching bits may change.
1382 1383 */
1383 1384 if (!PTE_ISPAGE(old_pte, l))
1384 1385 panic("non-null/page mapping pte=" FMT_PTE, old_pte);
1385 1386
1386 1387 if (PTE2PFN(old_pte, l) != PTE2PFN(pte, l)) {
1387 1388 REMAPASSERT(flags & HAT_LOAD_REMAP);
1388 1389 REMAPASSERT(flags & HAT_LOAD_NOCONSIST);
1389 1390 REMAPASSERT(PTE_GET(old_pte, PT_SOFTWARE) >= PT_NOCONSIST);
1390 1391 REMAPASSERT(pf_is_memory(PTE2PFN(old_pte, l)) ==
1391 1392 pf_is_memory(PTE2PFN(pte, l)));
1392 1393 REMAPASSERT(!is_consist);
1393 1394 }
1394 1395
1395 1396 /*
1396 1397 * We only let remaps change the certain bits in the PTE.
1397 1398 */
1398 1399 if (PTE_GET(old_pte, ~PT_REMAP_BITS) != PTE_GET(pte, ~PT_REMAP_BITS))
1399 1400 panic("remap bits changed: old_pte="FMT_PTE", pte="FMT_PTE"\n",
1400 1401 old_pte, pte);
1401 1402
1402 1403 /*
1403 1404 * We don't create any mapping list entries on a remap, so release
1404 1405 * any allocated hment after we drop the mapping list lock.
1405 1406 */
1406 1407 done:
1407 1408 if (is_consist) {
1408 1409 x86_hm_exit(pp);
1409 1410 if (hm != NULL)
1410 1411 hment_free(hm);
1411 1412 }
1412 1413 return (rv);
1413 1414 }
1414 1415
1415 1416 /*
1416 1417 * Internal routine to load a single page table entry. This only fails if
1417 1418 * we attempt to overwrite a page table link with a large page.
1418 1419 */
1419 1420 static int
1420 1421 hati_load_common(
1421 1422 hat_t *hat,
1422 1423 uintptr_t va,
1423 1424 page_t *pp,
1424 1425 uint_t attr,
1425 1426 uint_t flags,
1426 1427 level_t level,
1427 1428 pfn_t pfn)
1428 1429 {
1429 1430 htable_t *ht;
1430 1431 uint_t entry;
1431 1432 x86pte_t pte;
1432 1433 int rv = 0;
1433 1434
1434 1435 /*
1435 1436 * The number 16 is arbitrary and here to catch a recursion problem
1436 1437 * early before we blow out the kernel stack.
1437 1438 */
1438 1439 ++curthread->t_hatdepth;
1439 1440 ASSERT(curthread->t_hatdepth < 16);
1440 1441
1441 1442 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
1442 1443
1443 1444 if (flags & HAT_LOAD_SHARE)
1444 1445 hat->hat_flags |= HAT_SHARED;
1445 1446
1446 1447 /*
1447 1448 * Find the page table that maps this page if it already exists.
1448 1449 */
1449 1450 ht = htable_lookup(hat, va, level);
1450 1451
1451 1452 /*
1452 1453 * We must have HAT_LOAD_NOCONSIST if page_t is NULL.
1453 1454 */
1454 1455 if (pp == NULL)
1455 1456 flags |= HAT_LOAD_NOCONSIST;
1456 1457
1457 1458 if (ht == NULL) {
1458 1459 ht = htable_create(hat, va, level, NULL);
1459 1460 ASSERT(ht != NULL);
1460 1461 }
1461 1462 entry = htable_va2entry(va, ht);
1462 1463
1463 1464 /*
1464 1465 * a bunch of paranoid error checking
1465 1466 */
1466 1467 ASSERT(ht->ht_busy > 0);
1467 1468 if (ht->ht_vaddr > va || va > HTABLE_LAST_PAGE(ht))
1468 1469 panic("hati_load_common: bad htable %p, va %p",
1469 1470 (void *)ht, (void *)va);
1470 1471 ASSERT(ht->ht_level == level);
1471 1472
1472 1473 /*
1473 1474 * construct the new PTE
1474 1475 */
1475 1476 if (hat == kas.a_hat)
1476 1477 attr &= ~PROT_USER;
1477 1478 pte = hati_mkpte(pfn, attr, level, flags);
1478 1479 if (hat == kas.a_hat && va >= kernelbase)
1479 1480 PTE_SET(pte, mmu.pt_global);
1480 1481
1481 1482 /*
1482 1483 * establish the mapping
1483 1484 */
1484 1485 rv = hati_pte_map(ht, entry, pp, pte, flags, NULL);
1485 1486
1486 1487 /*
1487 1488 * release the htable and any reserves
1488 1489 */
1489 1490 htable_release(ht);
1490 1491 --curthread->t_hatdepth;
1491 1492 return (rv);
1492 1493 }
1493 1494
1494 1495 /*
1495 1496 * special case of hat_memload to deal with some kernel addrs for performance
1496 1497 */
1497 1498 static void
1498 1499 hat_kmap_load(
1499 1500 caddr_t addr,
1500 1501 page_t *pp,
1501 1502 uint_t attr,
1502 1503 uint_t flags)
1503 1504 {
1504 1505 uintptr_t va = (uintptr_t)addr;
1505 1506 x86pte_t pte;
1506 1507 pfn_t pfn = page_pptonum(pp);
1507 1508 pgcnt_t pg_off = mmu_btop(va - mmu.kmap_addr);
1508 1509 htable_t *ht;
1509 1510 uint_t entry;
1510 1511 void *pte_ptr;
1511 1512
1512 1513 /*
1513 1514 * construct the requested PTE
1514 1515 */
1515 1516 attr &= ~PROT_USER;
1516 1517 attr |= HAT_STORECACHING_OK;
1517 1518 pte = hati_mkpte(pfn, attr, 0, flags);
1518 1519 PTE_SET(pte, mmu.pt_global);
1519 1520
1520 1521 /*
1521 1522 * Figure out the pte_ptr and htable and use common code to finish up
1522 1523 */
1523 1524 if (mmu.pae_hat)
1524 1525 pte_ptr = mmu.kmap_ptes + pg_off;
1525 1526 else
1526 1527 pte_ptr = (x86pte32_t *)mmu.kmap_ptes + pg_off;
1527 1528 ht = mmu.kmap_htables[(va - mmu.kmap_htables[0]->ht_vaddr) >>
1528 1529 LEVEL_SHIFT(1)];
1529 1530 entry = htable_va2entry(va, ht);
1530 1531 ++curthread->t_hatdepth;
1531 1532 ASSERT(curthread->t_hatdepth < 16);
1532 1533 (void) hati_pte_map(ht, entry, pp, pte, flags, pte_ptr);
1533 1534 --curthread->t_hatdepth;
1534 1535 }
1535 1536
1536 1537 /*
1537 1538 * hat_memload() - load a translation to the given page struct
1538 1539 *
1539 1540 * Flags for hat_memload/hat_devload/hat_*attr.
1540 1541 *
1541 1542 * HAT_LOAD Default flags to load a translation to the page.
1542 1543 *
1543 1544 * HAT_LOAD_LOCK Lock down mapping resources; hat_map(), hat_memload(),
1544 1545 * and hat_devload().
1545 1546 *
1546 1547 * HAT_LOAD_NOCONSIST Do not add mapping to page_t mapping list.
1547 1548 * sets PT_NOCONSIST
1548 1549 *
1549 1550 * HAT_LOAD_SHARE A flag to hat_memload() to indicate h/w page tables
1550 1551 * that map some user pages (not kas) is shared by more
1551 1552 * than one process (eg. ISM).
1552 1553 *
1553 1554 * HAT_LOAD_REMAP Reload a valid pte with a different page frame.
1554 1555 *
1555 1556 * HAT_NO_KALLOC Do not kmem_alloc while creating the mapping; at this
1556 1557 * point, it's setting up mapping to allocate internal
1557 1558 * hat layer data structures. This flag forces hat layer
1558 1559 * to tap its reserves in order to prevent infinite
1559 1560 * recursion.
1560 1561 *
1561 1562 * The following is a protection attribute (like PROT_READ, etc.)
1562 1563 *
1563 1564 * HAT_NOSYNC set PT_NOSYNC - this mapping's ref/mod bits
1564 1565 * are never cleared.
1565 1566 *
1566 1567 * Installing new valid PTE's and creation of the mapping list
1567 1568 * entry are controlled under the same lock. It's derived from the
1568 1569 * page_t being mapped.
1569 1570 */
1570 1571 static uint_t supported_memload_flags =
1571 1572 HAT_LOAD | HAT_LOAD_LOCK | HAT_LOAD_ADV | HAT_LOAD_NOCONSIST |
1572 1573 HAT_LOAD_SHARE | HAT_NO_KALLOC | HAT_LOAD_REMAP | HAT_LOAD_TEXT;
1573 1574
1574 1575 void
1575 1576 hat_memload(
1576 1577 hat_t *hat,
1577 1578 caddr_t addr,
1578 1579 page_t *pp,
1579 1580 uint_t attr,
1580 1581 uint_t flags)
1581 1582 {
1582 1583 uintptr_t va = (uintptr_t)addr;
1583 1584 level_t level = 0;
1584 1585 pfn_t pfn = page_pptonum(pp);
1585 1586
1586 1587 XPV_DISALLOW_MIGRATE();
1587 1588 ASSERT(IS_PAGEALIGNED(va));
1588 1589 ASSERT(hat == kas.a_hat || va < _userlimit);
1589 1590 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
1590 1591 ASSERT((flags & supported_memload_flags) == flags);
1591 1592
1592 1593 ASSERT(!IN_VA_HOLE(va));
1593 1594 ASSERT(!PP_ISFREE(pp));
1594 1595
1595 1596 /*
1596 1597 * kernel address special case for performance.
1597 1598 */
1598 1599 if (mmu.kmap_addr <= va && va < mmu.kmap_eaddr) {
1599 1600 ASSERT(hat == kas.a_hat);
1600 1601 hat_kmap_load(addr, pp, attr, flags);
1601 1602 XPV_ALLOW_MIGRATE();
1602 1603 return;
1603 1604 }
1604 1605
1605 1606 /*
1606 1607 * This is used for memory with normal caching enabled, so
1607 1608 * always set HAT_STORECACHING_OK.
1608 1609 */
1609 1610 attr |= HAT_STORECACHING_OK;
1610 1611 if (hati_load_common(hat, va, pp, attr, flags, level, pfn) != 0)
1611 1612 panic("unexpected hati_load_common() failure");
1612 1613 XPV_ALLOW_MIGRATE();
1613 1614 }
1614 1615
1615 1616 /* ARGSUSED */
1616 1617 void
1617 1618 hat_memload_region(struct hat *hat, caddr_t addr, struct page *pp,
1618 1619 uint_t attr, uint_t flags, hat_region_cookie_t rcookie)
1619 1620 {
1620 1621 hat_memload(hat, addr, pp, attr, flags);
1621 1622 }
1622 1623
1623 1624 /*
1624 1625 * Load the given array of page structs using large pages when possible
1625 1626 */
1626 1627 void
1627 1628 hat_memload_array(
1628 1629 hat_t *hat,
1629 1630 caddr_t addr,
1630 1631 size_t len,
1631 1632 page_t **pages,
1632 1633 uint_t attr,
1633 1634 uint_t flags)
1634 1635 {
1635 1636 uintptr_t va = (uintptr_t)addr;
1636 1637 uintptr_t eaddr = va + len;
1637 1638 level_t level;
1638 1639 size_t pgsize;
1639 1640 pgcnt_t pgindx = 0;
1640 1641 pfn_t pfn;
1641 1642 pgcnt_t i;
1642 1643
1643 1644 XPV_DISALLOW_MIGRATE();
1644 1645 ASSERT(IS_PAGEALIGNED(va));
1645 1646 ASSERT(hat == kas.a_hat || va + len <= _userlimit);
1646 1647 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
1647 1648 ASSERT((flags & supported_memload_flags) == flags);
1648 1649
1649 1650 /*
1650 1651 * memload is used for memory with full caching enabled, so
1651 1652 * set HAT_STORECACHING_OK.
1652 1653 */
1653 1654 attr |= HAT_STORECACHING_OK;
1654 1655
1655 1656 /*
1656 1657 * handle all pages using largest possible pagesize
1657 1658 */
1658 1659 while (va < eaddr) {
1659 1660 /*
1660 1661 * decide what level mapping to use (ie. pagesize)
1661 1662 */
1662 1663 pfn = page_pptonum(pages[pgindx]);
1663 1664 for (level = mmu.max_page_level; ; --level) {
1664 1665 pgsize = LEVEL_SIZE(level);
1665 1666 if (level == 0)
1666 1667 break;
1667 1668
1668 1669 if (!IS_P2ALIGNED(va, pgsize) ||
1669 1670 (eaddr - va) < pgsize ||
1670 1671 !IS_P2ALIGNED(pfn_to_pa(pfn), pgsize))
1671 1672 continue;
1672 1673
1673 1674 /*
1674 1675 * To use a large mapping of this size, all the
1675 1676 * pages we are passed must be sequential subpages
1676 1677 * of the large page.
1677 1678 * hat_page_demote() can't change p_szc because
1678 1679 * all pages are locked.
1679 1680 */
1680 1681 if (pages[pgindx]->p_szc >= level) {
1681 1682 for (i = 0; i < mmu_btop(pgsize); ++i) {
1682 1683 if (pfn + i !=
1683 1684 page_pptonum(pages[pgindx + i]))
1684 1685 break;
1685 1686 ASSERT(pages[pgindx + i]->p_szc >=
1686 1687 level);
1687 1688 ASSERT(pages[pgindx] + i ==
1688 1689 pages[pgindx + i]);
1689 1690 }
1690 1691 if (i == mmu_btop(pgsize)) {
1691 1692 #ifdef DEBUG
1692 1693 if (level == 2)
1693 1694 map1gcnt++;
1694 1695 #endif
1695 1696 break;
1696 1697 }
1697 1698 }
1698 1699 }
1699 1700
1700 1701 /*
1701 1702 * Load this page mapping. If the load fails, try a smaller
1702 1703 * pagesize.
1703 1704 */
1704 1705 ASSERT(!IN_VA_HOLE(va));
1705 1706 while (hati_load_common(hat, va, pages[pgindx], attr,
1706 1707 flags, level, pfn) != 0) {
1707 1708 if (level == 0)
1708 1709 panic("unexpected hati_load_common() failure");
1709 1710 --level;
1710 1711 pgsize = LEVEL_SIZE(level);
1711 1712 }
1712 1713
1713 1714 /*
1714 1715 * move to next page
1715 1716 */
1716 1717 va += pgsize;
1717 1718 pgindx += mmu_btop(pgsize);
1718 1719 }
1719 1720 XPV_ALLOW_MIGRATE();
1720 1721 }
1721 1722
1722 1723 /* ARGSUSED */
1723 1724 void
1724 1725 hat_memload_array_region(struct hat *hat, caddr_t addr, size_t len,
1725 1726 struct page **pps, uint_t attr, uint_t flags,
1726 1727 hat_region_cookie_t rcookie)
1727 1728 {
1728 1729 hat_memload_array(hat, addr, len, pps, attr, flags);
1729 1730 }
1730 1731
1731 1732 /*
1732 1733 * void hat_devload(hat, addr, len, pf, attr, flags)
1733 1734 * load/lock the given page frame number
1734 1735 *
1735 1736 * Advisory ordering attributes. Apply only to device mappings.
1736 1737 *
1737 1738 * HAT_STRICTORDER: the CPU must issue the references in order, as the
1738 1739 * programmer specified. This is the default.
1739 1740 * HAT_UNORDERED_OK: the CPU may reorder the references (this is all kinds
1740 1741 * of reordering; store or load with store or load).
1741 1742 * HAT_MERGING_OK: merging and batching: the CPU may merge individual stores
1742 1743 * to consecutive locations (for example, turn two consecutive byte
1743 1744 * stores into one halfword store), and it may batch individual loads
1744 1745 * (for example, turn two consecutive byte loads into one halfword load).
1745 1746 * This also implies re-ordering.
1746 1747 * HAT_LOADCACHING_OK: the CPU may cache the data it fetches and reuse it
1747 1748 * until another store occurs. The default is to fetch new data
1748 1749 * on every load. This also implies merging.
1749 1750 * HAT_STORECACHING_OK: the CPU may keep the data in the cache and push it to
1750 1751 * the device (perhaps with other data) at a later time. The default is
1751 1752 * to push the data right away. This also implies load caching.
1752 1753 *
1753 1754 * Equivalent of hat_memload(), but can be used for device memory where
1754 1755 * there are no page_t's and we support additional flags (write merging, etc).
1755 1756 * Note that we can have large page mappings with this interface.
1756 1757 */
1757 1758 int supported_devload_flags = HAT_LOAD | HAT_LOAD_LOCK |
1758 1759 HAT_LOAD_NOCONSIST | HAT_STRICTORDER | HAT_UNORDERED_OK |
1759 1760 HAT_MERGING_OK | HAT_LOADCACHING_OK | HAT_STORECACHING_OK;
1760 1761
1761 1762 void
1762 1763 hat_devload(
1763 1764 hat_t *hat,
1764 1765 caddr_t addr,
1765 1766 size_t len,
1766 1767 pfn_t pfn,
1767 1768 uint_t attr,
1768 1769 int flags)
1769 1770 {
1770 1771 uintptr_t va = ALIGN2PAGE(addr);
1771 1772 uintptr_t eva = va + len;
1772 1773 level_t level;
1773 1774 size_t pgsize;
1774 1775 page_t *pp;
1775 1776 int f; /* per PTE copy of flags - maybe modified */
1776 1777 uint_t a; /* per PTE copy of attr */
1777 1778
1778 1779 XPV_DISALLOW_MIGRATE();
1779 1780 ASSERT(IS_PAGEALIGNED(va));
1780 1781 ASSERT(hat == kas.a_hat || eva <= _userlimit);
1781 1782 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
1782 1783 ASSERT((flags & supported_devload_flags) == flags);
1783 1784
1784 1785 /*
1785 1786 * handle all pages
1786 1787 */
1787 1788 while (va < eva) {
1788 1789
1789 1790 /*
1790 1791 * decide what level mapping to use (ie. pagesize)
1791 1792 */
1792 1793 for (level = mmu.max_page_level; ; --level) {
1793 1794 pgsize = LEVEL_SIZE(level);
1794 1795 if (level == 0)
1795 1796 break;
1796 1797 if (IS_P2ALIGNED(va, pgsize) &&
1797 1798 (eva - va) >= pgsize &&
1798 1799 IS_P2ALIGNED(pfn, mmu_btop(pgsize))) {
1799 1800 #ifdef DEBUG
1800 1801 if (level == 2)
1801 1802 map1gcnt++;
1802 1803 #endif
1803 1804 break;
1804 1805 }
1805 1806 }
1806 1807
1807 1808 /*
1808 1809 * If this is just memory then allow caching (this happens
1809 1810 * for the nucleus pages) - though HAT_PLAT_NOCACHE can be used
1810 1811 * to override that. If we don't have a page_t then make sure
1811 1812 * NOCONSIST is set.
1812 1813 */
1813 1814 a = attr;
1814 1815 f = flags;
1815 1816 if (!pf_is_memory(pfn))
1816 1817 f |= HAT_LOAD_NOCONSIST;
1817 1818 else if (!(a & HAT_PLAT_NOCACHE))
1818 1819 a |= HAT_STORECACHING_OK;
1819 1820
1820 1821 if (f & HAT_LOAD_NOCONSIST)
1821 1822 pp = NULL;
1822 1823 else
1823 1824 pp = page_numtopp_nolock(pfn);
1824 1825
1825 1826 /*
1826 1827 * Check to make sure we are really trying to map a valid
1827 1828 * memory page. The caller wishing to intentionally map
1828 1829 * free memory pages will have passed the HAT_LOAD_NOCONSIST
1829 1830 * flag, then pp will be NULL.
1830 1831 */
1831 1832 if (pp != NULL) {
1832 1833 if (PP_ISFREE(pp)) {
1833 1834 panic("hat_devload: loading "
1834 1835 "a mapping to free page %p", (void *)pp);
1835 1836 }
1836 1837
1837 1838 if (!PAGE_LOCKED(pp) && !PP_ISNORELOC(pp)) {
1838 1839 panic("hat_devload: loading a mapping "
1839 1840 "to an unlocked page %p",
1840 1841 (void *)pp);
1841 1842 }
1842 1843 }
1843 1844
1844 1845 /*
1845 1846 * load this page mapping
1846 1847 */
1847 1848 ASSERT(!IN_VA_HOLE(va));
1848 1849 while (hati_load_common(hat, va, pp, a, f, level, pfn) != 0) {
1849 1850 if (level == 0)
1850 1851 panic("unexpected hati_load_common() failure");
1851 1852 --level;
1852 1853 pgsize = LEVEL_SIZE(level);
1853 1854 }
1854 1855
1855 1856 /*
1856 1857 * move to next page
1857 1858 */
1858 1859 va += pgsize;
1859 1860 pfn += mmu_btop(pgsize);
1860 1861 }
1861 1862 XPV_ALLOW_MIGRATE();
1862 1863 }
1863 1864
1864 1865 /*
1865 1866 * void hat_unlock(hat, addr, len)
1866 1867 * unlock the mappings to a given range of addresses
1867 1868 *
1868 1869 * Locks are tracked by ht_lock_cnt in the htable.
1869 1870 */
1870 1871 void
1871 1872 hat_unlock(hat_t *hat, caddr_t addr, size_t len)
1872 1873 {
1873 1874 uintptr_t vaddr = (uintptr_t)addr;
1874 1875 uintptr_t eaddr = vaddr + len;
1875 1876 htable_t *ht = NULL;
1876 1877
1877 1878 /*
1878 1879 * kernel entries are always locked, we don't track lock counts
1879 1880 */
1880 1881 ASSERT(hat == kas.a_hat || eaddr <= _userlimit);
1881 1882 ASSERT(IS_PAGEALIGNED(vaddr));
1882 1883 ASSERT(IS_PAGEALIGNED(eaddr));
1883 1884 if (hat == kas.a_hat)
1884 1885 return;
1885 1886 if (eaddr > _userlimit)
1886 1887 panic("hat_unlock() address out of range - above _userlimit");
1887 1888
1888 1889 XPV_DISALLOW_MIGRATE();
1889 1890 ASSERT(AS_LOCK_HELD(hat->hat_as));
1890 1891 while (vaddr < eaddr) {
1891 1892 (void) htable_walk(hat, &ht, &vaddr, eaddr);
1892 1893 if (ht == NULL)
1893 1894 break;
1894 1895
1895 1896 ASSERT(!IN_VA_HOLE(vaddr));
1896 1897
1897 1898 if (ht->ht_lock_cnt < 1)
1898 1899 panic("hat_unlock(): lock_cnt < 1, "
1899 1900 "htable=%p, vaddr=%p\n", (void *)ht, (void *)vaddr);
1900 1901 HTABLE_LOCK_DEC(ht);
1901 1902
1902 1903 vaddr += LEVEL_SIZE(ht->ht_level);
1903 1904 }
1904 1905 if (ht)
1905 1906 htable_release(ht);
1906 1907 XPV_ALLOW_MIGRATE();
↓ open down ↓ |
1867 lines elided |
↑ open up ↑ |
1907 1908 }
1908 1909
1909 1910 /* ARGSUSED */
1910 1911 void
1911 1912 hat_unlock_region(struct hat *hat, caddr_t addr, size_t len,
1912 1913 hat_region_cookie_t rcookie)
1913 1914 {
1914 1915 panic("No shared region support on x86");
1915 1916 }
1916 1917
1918 +/*
1919 + * A range of virtual pages for purposes of demapping.
1920 + */
1921 +typedef struct range_info {
1922 + uintptr_t rng_va; /* address of page */
1923 + ulong_t rng_cnt; /* number of pages in range */
1924 + level_t rng_level; /* page table level */
1925 +} range_info_t;
1926 +
1917 1927 #if !defined(__xpv)
1918 1928 /*
1919 - * Cross call service routine to demap a virtual page on
1920 - * the current CPU or flush all mappings in TLB.
1929 + * Cross call service routine to demap a range of virtual
1930 + * pages on the current CPU or flush all mappings in TLB.
1921 1931 */
1922 1932 /*ARGSUSED*/
1923 1933 static int
1924 1934 hati_demap_func(xc_arg_t a1, xc_arg_t a2, xc_arg_t a3)
1925 1935 {
1926 - hat_t *hat = (hat_t *)a1;
1927 - caddr_t addr = (caddr_t)a2;
1928 - size_t len = (size_t)a3;
1936 + hat_t *hat = (hat_t *)a1;
1937 + range_info_t *range = (range_info_t *)a2;
1938 + size_t len = (size_t)a3;
1939 + caddr_t addr = (caddr_t)range->rng_va;
1940 + size_t pgsz = LEVEL_SIZE(range->rng_level);
1929 1941
1930 1942 /*
1931 1943 * If the target hat isn't the kernel and this CPU isn't operating
1932 1944 * in the target hat, we can ignore the cross call.
1933 1945 */
1934 1946 if (hat != kas.a_hat && hat != CPU->cpu_current_hat)
1935 1947 return (0);
1936 1948
1937 1949 /*
1938 1950 * For a normal address, we flush a range of contiguous mappings
1939 1951 */
1940 1952 if ((uintptr_t)addr != DEMAP_ALL_ADDR) {
1941 - for (size_t i = 0; i < len; i += MMU_PAGESIZE)
1953 + for (size_t i = 0; i < len; i += pgsz)
1942 1954 mmu_tlbflush_entry(addr + i);
1943 1955 return (0);
1944 1956 }
1945 1957
1946 1958 /*
1947 1959 * Otherwise we reload cr3 to effect a complete TLB flush.
1948 1960 *
1949 1961 * A reload of cr3 on a VLP process also means we must also recopy in
1950 1962 * the pte values from the struct hat
1951 1963 */
1952 1964 if (hat->hat_flags & HAT_VLP) {
1953 1965 #if defined(__amd64)
1954 1966 x86pte_t *vlpptep = CPU->cpu_hat_info->hci_vlp_l2ptes;
1955 1967
1956 1968 VLP_COPY(hat->hat_vlp_ptes, vlpptep);
1957 1969 #elif defined(__i386)
1958 1970 reload_pae32(hat, CPU);
1959 1971 #endif
1960 1972 }
1961 1973 reload_cr3();
1962 1974 return (0);
1963 1975 }
1964 1976
1965 1977 /*
1966 1978 * Flush all TLB entries, including global (ie. kernel) ones.
1967 1979 */
1968 1980 static void
1969 1981 flush_all_tlb_entries(void)
1970 1982 {
1971 1983 ulong_t cr4 = getcr4();
1972 1984
1973 1985 if (cr4 & CR4_PGE) {
1974 1986 setcr4(cr4 & ~(ulong_t)CR4_PGE);
1975 1987 setcr4(cr4);
1976 1988
1977 1989 /*
1978 1990 * 32 bit PAE also needs to always reload_cr3()
1979 1991 */
1980 1992 if (mmu.max_level == 2)
1981 1993 reload_cr3();
1982 1994 } else {
1983 1995 reload_cr3();
1984 1996 }
1985 1997 }
1986 1998
1987 1999 #define TLB_CPU_HALTED (01ul)
1988 2000 #define TLB_INVAL_ALL (02ul)
1989 2001 #define CAS_TLB_INFO(cpu, old, new) \
1990 2002 atomic_cas_ulong((ulong_t *)&(cpu)->cpu_m.mcpu_tlb_info, (old), (new))
1991 2003
1992 2004 /*
1993 2005 * Record that a CPU is going idle
1994 2006 */
1995 2007 void
1996 2008 tlb_going_idle(void)
1997 2009 {
1998 2010 atomic_or_ulong((ulong_t *)&CPU->cpu_m.mcpu_tlb_info, TLB_CPU_HALTED);
1999 2011 }
2000 2012
2001 2013 /*
2002 2014 * Service a delayed TLB flush if coming out of being idle.
2003 2015 * It will be called from cpu idle notification with interrupt disabled.
2004 2016 */
2005 2017 void
2006 2018 tlb_service(void)
2007 2019 {
2008 2020 ulong_t tlb_info;
2009 2021 ulong_t found;
2010 2022
2011 2023 /*
2012 2024 * We only have to do something if coming out of being idle.
2013 2025 */
2014 2026 tlb_info = CPU->cpu_m.mcpu_tlb_info;
2015 2027 if (tlb_info & TLB_CPU_HALTED) {
2016 2028 ASSERT(CPU->cpu_current_hat == kas.a_hat);
2017 2029
2018 2030 /*
2019 2031 * Atomic clear and fetch of old state.
2020 2032 */
2021 2033 while ((found = CAS_TLB_INFO(CPU, tlb_info, 0)) != tlb_info) {
2022 2034 ASSERT(found & TLB_CPU_HALTED);
2023 2035 tlb_info = found;
2024 2036 SMT_PAUSE();
2025 2037 }
2026 2038 if (tlb_info & TLB_INVAL_ALL)
↓ open down ↓ |
75 lines elided |
↑ open up ↑ |
2027 2039 flush_all_tlb_entries();
2028 2040 }
2029 2041 }
2030 2042 #endif /* !__xpv */
2031 2043
2032 2044 /*
2033 2045 * Internal routine to do cross calls to invalidate a range of pages on
2034 2046 * all CPUs using a given hat.
2035 2047 */
2036 2048 void
2037 -hat_tlb_inval_range(hat_t *hat, uintptr_t va, size_t len)
2049 +hat_tlb_inval_range(hat_t *hat, range_info_t *range)
2038 2050 {
2039 2051 extern int flushes_require_xcalls; /* from mp_startup.c */
2040 2052 cpuset_t justme;
2041 2053 cpuset_t cpus_to_shootdown;
2054 + uintptr_t va = range->rng_va;
2055 + size_t len = range->rng_cnt << LEVEL_SHIFT(range->rng_level);
2042 2056 #ifndef __xpv
2043 2057 cpuset_t check_cpus;
2044 2058 cpu_t *cpup;
2045 2059 int c;
2046 2060 #endif
2047 2061
2048 2062 /*
2049 2063 * If the hat is being destroyed, there are no more users, so
2050 2064 * demap need not do anything.
2051 2065 */
2052 2066 if (hat->hat_flags & HAT_FREEING)
2053 2067 return;
2054 2068
2055 2069 /*
2056 2070 * If demapping from a shared pagetable, we best demap the
2057 2071 * entire set of user TLBs, since we don't know what addresses
2058 2072 * these were shared at.
2059 2073 */
2060 2074 if (hat->hat_flags & HAT_SHARED) {
2061 2075 hat = kas.a_hat;
2062 2076 va = DEMAP_ALL_ADDR;
2063 2077 }
2064 2078
2065 2079 /*
2066 2080 * if not running with multiple CPUs, don't use cross calls
2067 2081 */
↓ open down ↓ |
16 lines elided |
↑ open up ↑ |
2068 2082 if (panicstr || !flushes_require_xcalls) {
2069 2083 #ifdef __xpv
2070 2084 if (va == DEMAP_ALL_ADDR) {
2071 2085 xen_flush_tlb();
2072 2086 } else {
2073 2087 for (size_t i = 0; i < len; i += MMU_PAGESIZE)
2074 2088 xen_flush_va((caddr_t)(va + i));
2075 2089 }
2076 2090 #else
2077 2091 (void) hati_demap_func((xc_arg_t)hat,
2078 - (xc_arg_t)va, (xc_arg_t)len);
2092 + (xc_arg_t)range, (xc_arg_t)len);
2079 2093 #endif
2080 2094 return;
2081 2095 }
2082 2096
2083 2097
2084 2098 /*
2085 2099 * Determine CPUs to shootdown. Kernel changes always do all CPUs.
2086 2100 * Otherwise it's just CPUs currently executing in this hat.
2087 2101 */
2088 2102 kpreempt_disable();
2089 2103 CPUSET_ONLY(justme, CPU->cpu_id);
2090 2104 if (hat == kas.a_hat)
2091 2105 cpus_to_shootdown = khat_cpuset;
2092 2106 else
2093 2107 cpus_to_shootdown = hat->hat_cpus;
2094 2108
2095 2109 #ifndef __xpv
2096 2110 /*
2097 2111 * If any CPUs in the set are idle, just request a delayed flush
2098 2112 * and avoid waking them up.
2099 2113 */
2100 2114 check_cpus = cpus_to_shootdown;
2101 2115 for (c = 0; c < NCPU && !CPUSET_ISNULL(check_cpus); ++c) {
2102 2116 ulong_t tlb_info;
2103 2117
2104 2118 if (!CPU_IN_SET(check_cpus, c))
2105 2119 continue;
2106 2120 CPUSET_DEL(check_cpus, c);
2107 2121 cpup = cpu[c];
2108 2122 if (cpup == NULL)
2109 2123 continue;
2110 2124
2111 2125 tlb_info = cpup->cpu_m.mcpu_tlb_info;
2112 2126 while (tlb_info == TLB_CPU_HALTED) {
2113 2127 (void) CAS_TLB_INFO(cpup, TLB_CPU_HALTED,
2114 2128 TLB_CPU_HALTED | TLB_INVAL_ALL);
2115 2129 SMT_PAUSE();
2116 2130 tlb_info = cpup->cpu_m.mcpu_tlb_info;
2117 2131 }
2118 2132 if (tlb_info == (TLB_CPU_HALTED | TLB_INVAL_ALL)) {
2119 2133 HATSTAT_INC(hs_tlb_inval_delayed);
2120 2134 CPUSET_DEL(cpus_to_shootdown, c);
2121 2135 }
2122 2136 }
2123 2137 #endif
2124 2138
2125 2139 if (CPUSET_ISNULL(cpus_to_shootdown) ||
2126 2140 CPUSET_ISEQUAL(cpus_to_shootdown, justme)) {
↓ open down ↓ |
38 lines elided |
↑ open up ↑ |
2127 2141
2128 2142 #ifdef __xpv
2129 2143 if (va == DEMAP_ALL_ADDR) {
2130 2144 xen_flush_tlb();
2131 2145 } else {
2132 2146 for (size_t i = 0; i < len; i += MMU_PAGESIZE)
2133 2147 xen_flush_va((caddr_t)(va + i));
2134 2148 }
2135 2149 #else
2136 2150 (void) hati_demap_func((xc_arg_t)hat,
2137 - (xc_arg_t)va, (xc_arg_t)len);
2151 + (xc_arg_t)range, (xc_arg_t)len);
2138 2152 #endif
2139 2153
2140 2154 } else {
2141 2155
2142 2156 CPUSET_ADD(cpus_to_shootdown, CPU->cpu_id);
2143 2157 #ifdef __xpv
2144 2158 if (va == DEMAP_ALL_ADDR) {
2145 2159 xen_gflush_tlb(cpus_to_shootdown);
2146 2160 } else {
2147 2161 for (size_t i = 0; i < len; i += MMU_PAGESIZE) {
2148 2162 xen_gflush_va((caddr_t)(va + i),
2149 2163 cpus_to_shootdown);
2150 2164 }
2151 2165 }
2152 2166 #else
2153 - xc_call((xc_arg_t)hat, (xc_arg_t)va, (xc_arg_t)len,
2167 + xc_call((xc_arg_t)hat, (xc_arg_t)range, (xc_arg_t)len,
2154 2168 CPUSET2BV(cpus_to_shootdown), hati_demap_func);
2155 2169 #endif
2156 2170
2157 2171 }
2158 2172 kpreempt_enable();
2159 2173 }
2160 2174
2161 2175 void
2162 2176 hat_tlb_inval(hat_t *hat, uintptr_t va)
2163 2177 {
2164 - hat_tlb_inval_range(hat, va, MMU_PAGESIZE);
2178 + /*
2179 + * Create range for a single page.
2180 + */
2181 + range_info_t range;
2182 + range.rng_va = va;
2183 + range.rng_cnt = 1; /* one page */
2184 + range.rng_level = MIN_PAGE_LEVEL; /* pages are MMU_PAGESIZE */
2185 +
2186 + hat_tlb_inval_range(hat, &range);
2165 2187 }
2166 2188
2167 2189 /*
2168 2190 * Interior routine for HAT_UNLOADs from hat_unload_callback(),
2169 2191 * hat_kmap_unload() OR from hat_steal() code. This routine doesn't
2170 2192 * handle releasing of the htables.
2171 2193 */
2172 2194 void
2173 2195 hat_pte_unmap(
2174 2196 htable_t *ht,
2175 2197 uint_t entry,
2176 2198 uint_t flags,
2177 2199 x86pte_t old_pte,
2178 2200 void *pte_ptr,
2179 2201 boolean_t tlb)
2180 2202 {
2181 2203 hat_t *hat = ht->ht_hat;
2182 2204 hment_t *hm = NULL;
2183 2205 page_t *pp = NULL;
2184 2206 level_t l = ht->ht_level;
2185 2207 pfn_t pfn;
2186 2208
2187 2209 /*
2188 2210 * We always track the locking counts, even if nothing is unmapped
2189 2211 */
2190 2212 if ((flags & HAT_UNLOAD_UNLOCK) != 0 && hat != kas.a_hat) {
2191 2213 ASSERT(ht->ht_lock_cnt > 0);
2192 2214 HTABLE_LOCK_DEC(ht);
2193 2215 }
2194 2216
2195 2217 /*
2196 2218 * Figure out which page's mapping list lock to acquire using the PFN
2197 2219 * passed in "old" PTE. We then attempt to invalidate the PTE.
2198 2220 * If another thread, probably a hat_pageunload, has asynchronously
2199 2221 * unmapped/remapped this address we'll loop here.
2200 2222 */
2201 2223 ASSERT(ht->ht_busy > 0);
2202 2224 while (PTE_ISVALID(old_pte)) {
2203 2225 pfn = PTE2PFN(old_pte, l);
2204 2226 if (PTE_GET(old_pte, PT_SOFTWARE) >= PT_NOCONSIST) {
2205 2227 pp = NULL;
2206 2228 } else {
2207 2229 #ifdef __xpv
2208 2230 if (pfn == PFN_INVALID)
2209 2231 panic("Invalid PFN, but not PT_NOCONSIST");
2210 2232 #endif
2211 2233 pp = page_numtopp_nolock(pfn);
2212 2234 if (pp == NULL) {
2213 2235 panic("no page_t, not NOCONSIST: old_pte="
2214 2236 FMT_PTE " ht=%lx entry=0x%x pte_ptr=%lx",
2215 2237 old_pte, (uintptr_t)ht, entry,
2216 2238 (uintptr_t)pte_ptr);
2217 2239 }
2218 2240 x86_hm_enter(pp);
2219 2241 }
2220 2242
2221 2243 old_pte = x86pte_inval(ht, entry, old_pte, pte_ptr, tlb);
2222 2244
2223 2245 /*
2224 2246 * If the page hadn't changed we've unmapped it and can proceed
2225 2247 */
2226 2248 if (PTE_ISVALID(old_pte) && PTE2PFN(old_pte, l) == pfn)
2227 2249 break;
2228 2250
2229 2251 /*
2230 2252 * Otherwise, we'll have to retry with the current old_pte.
2231 2253 * Drop the hment lock, since the pfn may have changed.
2232 2254 */
2233 2255 if (pp != NULL) {
2234 2256 x86_hm_exit(pp);
2235 2257 pp = NULL;
2236 2258 } else {
2237 2259 ASSERT(PTE_GET(old_pte, PT_SOFTWARE) >= PT_NOCONSIST);
2238 2260 }
2239 2261 }
2240 2262
2241 2263 /*
2242 2264 * If the old mapping wasn't valid, there's nothing more to do
2243 2265 */
2244 2266 if (!PTE_ISVALID(old_pte)) {
2245 2267 if (pp != NULL)
2246 2268 x86_hm_exit(pp);
2247 2269 return;
2248 2270 }
2249 2271
2250 2272 /*
2251 2273 * Take care of syncing any MOD/REF bits and removing the hment.
2252 2274 */
2253 2275 if (pp != NULL) {
2254 2276 if (!(flags & HAT_UNLOAD_NOSYNC))
2255 2277 hati_sync_pte_to_page(pp, old_pte, l);
2256 2278 hm = hment_remove(pp, ht, entry);
2257 2279 x86_hm_exit(pp);
2258 2280 if (hm != NULL)
2259 2281 hment_free(hm);
2260 2282 }
2261 2283
2262 2284 /*
2263 2285 * Handle book keeping in the htable and hat
2264 2286 */
2265 2287 ASSERT(ht->ht_valid_cnt > 0);
2266 2288 HTABLE_DEC(ht->ht_valid_cnt);
2267 2289 PGCNT_DEC(hat, l);
2268 2290 }
2269 2291
2270 2292 /*
2271 2293 * very cheap unload implementation to special case some kernel addresses
2272 2294 */
2273 2295 static void
2274 2296 hat_kmap_unload(caddr_t addr, size_t len, uint_t flags)
2275 2297 {
2276 2298 uintptr_t va = (uintptr_t)addr;
2277 2299 uintptr_t eva = va + len;
2278 2300 pgcnt_t pg_index;
2279 2301 htable_t *ht;
2280 2302 uint_t entry;
2281 2303 x86pte_t *pte_ptr;
2282 2304 x86pte_t old_pte;
2283 2305
2284 2306 for (; va < eva; va += MMU_PAGESIZE) {
2285 2307 /*
2286 2308 * Get the PTE
2287 2309 */
2288 2310 pg_index = mmu_btop(va - mmu.kmap_addr);
2289 2311 pte_ptr = PT_INDEX_PTR(mmu.kmap_ptes, pg_index);
2290 2312 old_pte = GET_PTE(pte_ptr);
2291 2313
2292 2314 /*
2293 2315 * get the htable / entry
2294 2316 */
2295 2317 ht = mmu.kmap_htables[(va - mmu.kmap_htables[0]->ht_vaddr)
2296 2318 >> LEVEL_SHIFT(1)];
2297 2319 entry = htable_va2entry(va, ht);
2298 2320
2299 2321 /*
2300 2322 * use mostly common code to unmap it.
2301 2323 */
2302 2324 hat_pte_unmap(ht, entry, flags, old_pte, pte_ptr, B_TRUE);
2303 2325 }
2304 2326 }
2305 2327
2306 2328
2307 2329 /*
2308 2330 * unload a range of virtual address space (no callback)
2309 2331 */
2310 2332 void
2311 2333 hat_unload(hat_t *hat, caddr_t addr, size_t len, uint_t flags)
2312 2334 {
2313 2335 uintptr_t va = (uintptr_t)addr;
2314 2336
2315 2337 XPV_DISALLOW_MIGRATE();
2316 2338 ASSERT(hat == kas.a_hat || va + len <= _userlimit);
2317 2339
2318 2340 /*
2319 2341 * special case for performance.
2320 2342 */
↓ open down ↓ |
146 lines elided |
↑ open up ↑ |
2321 2343 if (mmu.kmap_addr <= va && va < mmu.kmap_eaddr) {
2322 2344 ASSERT(hat == kas.a_hat);
2323 2345 hat_kmap_unload(addr, len, flags);
2324 2346 } else {
2325 2347 hat_unload_callback(hat, addr, len, flags, NULL);
2326 2348 }
2327 2349 XPV_ALLOW_MIGRATE();
2328 2350 }
2329 2351
2330 2352 /*
2331 - * Do the callbacks for ranges being unloaded.
2332 - */
2333 -typedef struct range_info {
2334 - uintptr_t rng_va;
2335 - ulong_t rng_cnt;
2336 - level_t rng_level;
2337 -} range_info_t;
2338 -
2339 -/*
2340 2353 * Invalidate the TLB, and perform the callback to the upper level VM system,
2341 2354 * for the specified ranges of contiguous pages.
2342 2355 */
2343 2356 static void
2344 2357 handle_ranges(hat_t *hat, hat_callback_t *cb, uint_t cnt, range_info_t *range)
2345 2358 {
2346 2359 while (cnt > 0) {
2347 - size_t len;
2348 -
2349 2360 --cnt;
2350 - len = range[cnt].rng_cnt << LEVEL_SHIFT(range[cnt].rng_level);
2351 - hat_tlb_inval_range(hat, (uintptr_t)range[cnt].rng_va, len);
2361 + hat_tlb_inval_range(hat, &range[cnt]);
2352 2362
2353 2363 if (cb != NULL) {
2354 2364 cb->hcb_start_addr = (caddr_t)range[cnt].rng_va;
2355 2365 cb->hcb_end_addr = cb->hcb_start_addr;
2356 - cb->hcb_end_addr += len;
2366 + cb->hcb_end_addr += range[cnt].rng_cnt <<
2367 + LEVEL_SHIFT(range[cnt].rng_level);
2357 2368 cb->hcb_function(cb);
2358 2369 }
2359 2370 }
2360 2371 }
2361 2372
2362 2373 /*
2363 2374 * Unload a given range of addresses (has optional callback)
2364 2375 *
2365 2376 * Flags:
2366 2377 * define HAT_UNLOAD 0x00
2367 2378 * define HAT_UNLOAD_NOSYNC 0x02
2368 2379 * define HAT_UNLOAD_UNLOCK 0x04
2369 2380 * define HAT_UNLOAD_OTHER 0x08 - not used
2370 2381 * define HAT_UNLOAD_UNMAP 0x10 - same as HAT_UNLOAD
2371 2382 */
2372 2383 #define MAX_UNLOAD_CNT (8)
2373 2384 void
2374 2385 hat_unload_callback(
2375 2386 hat_t *hat,
2376 2387 caddr_t addr,
2377 2388 size_t len,
2378 2389 uint_t flags,
2379 2390 hat_callback_t *cb)
2380 2391 {
2381 2392 uintptr_t vaddr = (uintptr_t)addr;
2382 2393 uintptr_t eaddr = vaddr + len;
2383 2394 htable_t *ht = NULL;
2384 2395 uint_t entry;
2385 2396 uintptr_t contig_va = (uintptr_t)-1L;
2386 2397 range_info_t r[MAX_UNLOAD_CNT];
2387 2398 uint_t r_cnt = 0;
2388 2399 x86pte_t old_pte;
2389 2400
2390 2401 XPV_DISALLOW_MIGRATE();
2391 2402 ASSERT(hat == kas.a_hat || eaddr <= _userlimit);
2392 2403 ASSERT(IS_PAGEALIGNED(vaddr));
2393 2404 ASSERT(IS_PAGEALIGNED(eaddr));
2394 2405
2395 2406 /*
2396 2407 * Special case a single page being unloaded for speed. This happens
2397 2408 * quite frequently, COW faults after a fork() for example.
2398 2409 */
2399 2410 if (cb == NULL && len == MMU_PAGESIZE) {
2400 2411 ht = htable_getpte(hat, vaddr, &entry, &old_pte, 0);
2401 2412 if (ht != NULL) {
2402 2413 if (PTE_ISVALID(old_pte)) {
2403 2414 hat_pte_unmap(ht, entry, flags, old_pte,
2404 2415 NULL, B_TRUE);
2405 2416 }
2406 2417 htable_release(ht);
2407 2418 }
2408 2419 XPV_ALLOW_MIGRATE();
2409 2420 return;
2410 2421 }
2411 2422
2412 2423 while (vaddr < eaddr) {
2413 2424 old_pte = htable_walk(hat, &ht, &vaddr, eaddr);
2414 2425 if (ht == NULL)
2415 2426 break;
2416 2427
2417 2428 ASSERT(!IN_VA_HOLE(vaddr));
2418 2429
2419 2430 if (vaddr < (uintptr_t)addr)
2420 2431 panic("hat_unload_callback(): unmap inside large page");
2421 2432
2422 2433 /*
2423 2434 * We'll do the call backs for contiguous ranges
2424 2435 */
2425 2436 if (vaddr != contig_va ||
2426 2437 (r_cnt > 0 && r[r_cnt - 1].rng_level != ht->ht_level)) {
2427 2438 if (r_cnt == MAX_UNLOAD_CNT) {
2428 2439 handle_ranges(hat, cb, r_cnt, r);
2429 2440 r_cnt = 0;
2430 2441 }
2431 2442 r[r_cnt].rng_va = vaddr;
2432 2443 r[r_cnt].rng_cnt = 0;
2433 2444 r[r_cnt].rng_level = ht->ht_level;
2434 2445 ++r_cnt;
2435 2446 }
2436 2447
2437 2448 /*
2438 2449 * Unload one mapping (for a single page) from the page tables.
2439 2450 * Note that we do not remove the mapping from the TLB yet,
2440 2451 * as indicated by the tlb=FALSE argument to hat_pte_unmap().
2441 2452 * handle_ranges() will clear the TLB entries with one call to
2442 2453 * hat_tlb_inval_range() per contiguous range. This is
2443 2454 * safe because the page can not be reused until the
2444 2455 * callback is made (or we return).
2445 2456 */
2446 2457 entry = htable_va2entry(vaddr, ht);
2447 2458 hat_pte_unmap(ht, entry, flags, old_pte, NULL, B_FALSE);
2448 2459 ASSERT(ht->ht_level <= mmu.max_page_level);
2449 2460 vaddr += LEVEL_SIZE(ht->ht_level);
2450 2461 contig_va = vaddr;
2451 2462 ++r[r_cnt - 1].rng_cnt;
2452 2463 }
2453 2464 if (ht)
2454 2465 htable_release(ht);
2455 2466
2456 2467 /*
2457 2468 * handle last range for callbacks
2458 2469 */
2459 2470 if (r_cnt > 0)
2460 2471 handle_ranges(hat, cb, r_cnt, r);
2461 2472 XPV_ALLOW_MIGRATE();
2462 2473 }
2463 2474
2464 2475 /*
2465 2476 * Invalidate a virtual address translation on a slave CPU during
2466 2477 * panic() dumps.
2467 2478 */
2468 2479 void
2469 2480 hat_flush_range(hat_t *hat, caddr_t va, size_t size)
2470 2481 {
2471 2482 ssize_t sz;
2472 2483 caddr_t endva = va + size;
2473 2484
2474 2485 while (va < endva) {
2475 2486 sz = hat_getpagesize(hat, va);
2476 2487 if (sz < 0) {
2477 2488 #ifdef __xpv
2478 2489 xen_flush_tlb();
2479 2490 #else
2480 2491 flush_all_tlb_entries();
2481 2492 #endif
2482 2493 break;
2483 2494 }
2484 2495 #ifdef __xpv
2485 2496 xen_flush_va(va);
2486 2497 #else
2487 2498 mmu_tlbflush_entry(va);
2488 2499 #endif
2489 2500 va += sz;
2490 2501 }
2491 2502 }
2492 2503
2493 2504 /*
2494 2505 * synchronize mapping with software data structures
2495 2506 *
2496 2507 * This interface is currently only used by the working set monitor
2497 2508 * driver.
2498 2509 */
2499 2510 /*ARGSUSED*/
2500 2511 void
2501 2512 hat_sync(hat_t *hat, caddr_t addr, size_t len, uint_t flags)
2502 2513 {
2503 2514 uintptr_t vaddr = (uintptr_t)addr;
2504 2515 uintptr_t eaddr = vaddr + len;
2505 2516 htable_t *ht = NULL;
2506 2517 uint_t entry;
2507 2518 x86pte_t pte;
2508 2519 x86pte_t save_pte;
2509 2520 x86pte_t new;
2510 2521 page_t *pp;
2511 2522
2512 2523 ASSERT(!IN_VA_HOLE(vaddr));
2513 2524 ASSERT(IS_PAGEALIGNED(vaddr));
2514 2525 ASSERT(IS_PAGEALIGNED(eaddr));
2515 2526 ASSERT(hat == kas.a_hat || eaddr <= _userlimit);
2516 2527
2517 2528 XPV_DISALLOW_MIGRATE();
2518 2529 for (; vaddr < eaddr; vaddr += LEVEL_SIZE(ht->ht_level)) {
2519 2530 try_again:
2520 2531 pte = htable_walk(hat, &ht, &vaddr, eaddr);
2521 2532 if (ht == NULL)
2522 2533 break;
2523 2534 entry = htable_va2entry(vaddr, ht);
2524 2535
2525 2536 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC ||
2526 2537 PTE_GET(pte, PT_REF | PT_MOD) == 0)
2527 2538 continue;
2528 2539
2529 2540 /*
2530 2541 * We need to acquire the mapping list lock to protect
2531 2542 * against hat_pageunload(), hat_unload(), etc.
2532 2543 */
2533 2544 pp = page_numtopp_nolock(PTE2PFN(pte, ht->ht_level));
2534 2545 if (pp == NULL)
2535 2546 break;
2536 2547 x86_hm_enter(pp);
2537 2548 save_pte = pte;
2538 2549 pte = x86pte_get(ht, entry);
2539 2550 if (pte != save_pte) {
2540 2551 x86_hm_exit(pp);
2541 2552 goto try_again;
2542 2553 }
2543 2554 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC ||
2544 2555 PTE_GET(pte, PT_REF | PT_MOD) == 0) {
2545 2556 x86_hm_exit(pp);
2546 2557 continue;
2547 2558 }
2548 2559
2549 2560 /*
2550 2561 * Need to clear ref or mod bits. We may compete with
2551 2562 * hardware updating the R/M bits and have to try again.
2552 2563 */
2553 2564 if (flags == HAT_SYNC_ZERORM) {
2554 2565 new = pte;
2555 2566 PTE_CLR(new, PT_REF | PT_MOD);
2556 2567 pte = hati_update_pte(ht, entry, pte, new);
2557 2568 if (pte != 0) {
2558 2569 x86_hm_exit(pp);
2559 2570 goto try_again;
2560 2571 }
2561 2572 } else {
2562 2573 /*
2563 2574 * sync the PTE to the page_t
2564 2575 */
2565 2576 hati_sync_pte_to_page(pp, save_pte, ht->ht_level);
2566 2577 }
2567 2578 x86_hm_exit(pp);
2568 2579 }
2569 2580 if (ht)
2570 2581 htable_release(ht);
2571 2582 XPV_ALLOW_MIGRATE();
2572 2583 }
2573 2584
2574 2585 /*
2575 2586 * void hat_map(hat, addr, len, flags)
2576 2587 */
2577 2588 /*ARGSUSED*/
2578 2589 void
2579 2590 hat_map(hat_t *hat, caddr_t addr, size_t len, uint_t flags)
2580 2591 {
2581 2592 /* does nothing */
2582 2593 }
2583 2594
2584 2595 /*
2585 2596 * uint_t hat_getattr(hat, addr, *attr)
2586 2597 * returns attr for <hat,addr> in *attr. returns 0 if there was a
2587 2598 * mapping and *attr is valid, nonzero if there was no mapping and
2588 2599 * *attr is not valid.
2589 2600 */
2590 2601 uint_t
2591 2602 hat_getattr(hat_t *hat, caddr_t addr, uint_t *attr)
2592 2603 {
2593 2604 uintptr_t vaddr = ALIGN2PAGE(addr);
2594 2605 htable_t *ht = NULL;
2595 2606 x86pte_t pte;
2596 2607
2597 2608 ASSERT(hat == kas.a_hat || vaddr <= _userlimit);
2598 2609
2599 2610 if (IN_VA_HOLE(vaddr))
2600 2611 return ((uint_t)-1);
2601 2612
2602 2613 ht = htable_getpte(hat, vaddr, NULL, &pte, mmu.max_page_level);
2603 2614 if (ht == NULL)
2604 2615 return ((uint_t)-1);
2605 2616
2606 2617 if (!PTE_ISVALID(pte) || !PTE_ISPAGE(pte, ht->ht_level)) {
2607 2618 htable_release(ht);
2608 2619 return ((uint_t)-1);
2609 2620 }
2610 2621
2611 2622 *attr = PROT_READ;
2612 2623 if (PTE_GET(pte, PT_WRITABLE))
2613 2624 *attr |= PROT_WRITE;
2614 2625 if (PTE_GET(pte, PT_USER))
2615 2626 *attr |= PROT_USER;
2616 2627 if (!PTE_GET(pte, mmu.pt_nx))
2617 2628 *attr |= PROT_EXEC;
2618 2629 if (PTE_GET(pte, PT_SOFTWARE) >= PT_NOSYNC)
2619 2630 *attr |= HAT_NOSYNC;
2620 2631 htable_release(ht);
2621 2632 return (0);
2622 2633 }
2623 2634
2624 2635 /*
2625 2636 * hat_updateattr() applies the given attribute change to an existing mapping
2626 2637 */
2627 2638 #define HAT_LOAD_ATTR 1
2628 2639 #define HAT_SET_ATTR 2
2629 2640 #define HAT_CLR_ATTR 3
2630 2641
2631 2642 static void
2632 2643 hat_updateattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr, int what)
2633 2644 {
2634 2645 uintptr_t vaddr = (uintptr_t)addr;
2635 2646 uintptr_t eaddr = (uintptr_t)addr + len;
2636 2647 htable_t *ht = NULL;
2637 2648 uint_t entry;
2638 2649 x86pte_t oldpte, newpte;
2639 2650 page_t *pp;
2640 2651
2641 2652 XPV_DISALLOW_MIGRATE();
2642 2653 ASSERT(IS_PAGEALIGNED(vaddr));
2643 2654 ASSERT(IS_PAGEALIGNED(eaddr));
2644 2655 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
2645 2656 for (; vaddr < eaddr; vaddr += LEVEL_SIZE(ht->ht_level)) {
2646 2657 try_again:
2647 2658 oldpte = htable_walk(hat, &ht, &vaddr, eaddr);
2648 2659 if (ht == NULL)
2649 2660 break;
2650 2661 if (PTE_GET(oldpte, PT_SOFTWARE) >= PT_NOCONSIST)
2651 2662 continue;
2652 2663
2653 2664 pp = page_numtopp_nolock(PTE2PFN(oldpte, ht->ht_level));
2654 2665 if (pp == NULL)
2655 2666 continue;
2656 2667 x86_hm_enter(pp);
2657 2668
2658 2669 newpte = oldpte;
2659 2670 /*
2660 2671 * We found a page table entry in the desired range,
2661 2672 * figure out the new attributes.
2662 2673 */
2663 2674 if (what == HAT_SET_ATTR || what == HAT_LOAD_ATTR) {
2664 2675 if ((attr & PROT_WRITE) &&
2665 2676 !PTE_GET(oldpte, PT_WRITABLE))
2666 2677 newpte |= PT_WRITABLE;
2667 2678
2668 2679 if ((attr & HAT_NOSYNC) &&
2669 2680 PTE_GET(oldpte, PT_SOFTWARE) < PT_NOSYNC)
2670 2681 newpte |= PT_NOSYNC;
2671 2682
2672 2683 if ((attr & PROT_EXEC) && PTE_GET(oldpte, mmu.pt_nx))
2673 2684 newpte &= ~mmu.pt_nx;
2674 2685 }
2675 2686
2676 2687 if (what == HAT_LOAD_ATTR) {
2677 2688 if (!(attr & PROT_WRITE) &&
2678 2689 PTE_GET(oldpte, PT_WRITABLE))
2679 2690 newpte &= ~PT_WRITABLE;
2680 2691
2681 2692 if (!(attr & HAT_NOSYNC) &&
2682 2693 PTE_GET(oldpte, PT_SOFTWARE) >= PT_NOSYNC)
2683 2694 newpte &= ~PT_SOFTWARE;
2684 2695
2685 2696 if (!(attr & PROT_EXEC) && !PTE_GET(oldpte, mmu.pt_nx))
2686 2697 newpte |= mmu.pt_nx;
2687 2698 }
2688 2699
2689 2700 if (what == HAT_CLR_ATTR) {
2690 2701 if ((attr & PROT_WRITE) && PTE_GET(oldpte, PT_WRITABLE))
2691 2702 newpte &= ~PT_WRITABLE;
2692 2703
2693 2704 if ((attr & HAT_NOSYNC) &&
2694 2705 PTE_GET(oldpte, PT_SOFTWARE) >= PT_NOSYNC)
2695 2706 newpte &= ~PT_SOFTWARE;
2696 2707
2697 2708 if ((attr & PROT_EXEC) && !PTE_GET(oldpte, mmu.pt_nx))
2698 2709 newpte |= mmu.pt_nx;
2699 2710 }
2700 2711
2701 2712 /*
2702 2713 * Ensure NOSYNC/NOCONSIST mappings have REF and MOD set.
2703 2714 * x86pte_set() depends on this.
2704 2715 */
2705 2716 if (PTE_GET(newpte, PT_SOFTWARE) >= PT_NOSYNC)
2706 2717 newpte |= PT_REF | PT_MOD;
2707 2718
2708 2719 /*
2709 2720 * what about PROT_READ or others? this code only handles:
2710 2721 * EXEC, WRITE, NOSYNC
2711 2722 */
2712 2723
2713 2724 /*
2714 2725 * If new PTE really changed, update the table.
2715 2726 */
2716 2727 if (newpte != oldpte) {
2717 2728 entry = htable_va2entry(vaddr, ht);
2718 2729 oldpte = hati_update_pte(ht, entry, oldpte, newpte);
2719 2730 if (oldpte != 0) {
2720 2731 x86_hm_exit(pp);
2721 2732 goto try_again;
2722 2733 }
2723 2734 }
2724 2735 x86_hm_exit(pp);
2725 2736 }
2726 2737 if (ht)
2727 2738 htable_release(ht);
2728 2739 XPV_ALLOW_MIGRATE();
2729 2740 }
2730 2741
2731 2742 /*
2732 2743 * Various wrappers for hat_updateattr()
2733 2744 */
2734 2745 void
2735 2746 hat_setattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr)
2736 2747 {
2737 2748 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit);
2738 2749 hat_updateattr(hat, addr, len, attr, HAT_SET_ATTR);
2739 2750 }
2740 2751
2741 2752 void
2742 2753 hat_clrattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr)
2743 2754 {
2744 2755 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit);
2745 2756 hat_updateattr(hat, addr, len, attr, HAT_CLR_ATTR);
2746 2757 }
2747 2758
2748 2759 void
2749 2760 hat_chgattr(hat_t *hat, caddr_t addr, size_t len, uint_t attr)
2750 2761 {
2751 2762 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit);
2752 2763 hat_updateattr(hat, addr, len, attr, HAT_LOAD_ATTR);
2753 2764 }
2754 2765
2755 2766 void
2756 2767 hat_chgprot(hat_t *hat, caddr_t addr, size_t len, uint_t vprot)
2757 2768 {
2758 2769 ASSERT(hat == kas.a_hat || (uintptr_t)addr + len <= _userlimit);
2759 2770 hat_updateattr(hat, addr, len, vprot & HAT_PROT_MASK, HAT_LOAD_ATTR);
2760 2771 }
2761 2772
2762 2773 /*
2763 2774 * size_t hat_getpagesize(hat, addr)
2764 2775 * returns pagesize in bytes for <hat, addr>. returns -1 of there is
2765 2776 * no mapping. This is an advisory call.
2766 2777 */
2767 2778 ssize_t
2768 2779 hat_getpagesize(hat_t *hat, caddr_t addr)
2769 2780 {
2770 2781 uintptr_t vaddr = ALIGN2PAGE(addr);
2771 2782 htable_t *ht;
2772 2783 size_t pagesize;
2773 2784
2774 2785 ASSERT(hat == kas.a_hat || vaddr <= _userlimit);
2775 2786 if (IN_VA_HOLE(vaddr))
2776 2787 return (-1);
2777 2788 ht = htable_getpage(hat, vaddr, NULL);
2778 2789 if (ht == NULL)
2779 2790 return (-1);
2780 2791 pagesize = LEVEL_SIZE(ht->ht_level);
2781 2792 htable_release(ht);
2782 2793 return (pagesize);
2783 2794 }
2784 2795
2785 2796
2786 2797
2787 2798 /*
2788 2799 * pfn_t hat_getpfnum(hat, addr)
2789 2800 * returns pfn for <hat, addr> or PFN_INVALID if mapping is invalid.
2790 2801 */
2791 2802 pfn_t
2792 2803 hat_getpfnum(hat_t *hat, caddr_t addr)
2793 2804 {
2794 2805 uintptr_t vaddr = ALIGN2PAGE(addr);
2795 2806 htable_t *ht;
2796 2807 uint_t entry;
2797 2808 pfn_t pfn = PFN_INVALID;
2798 2809
2799 2810 ASSERT(hat == kas.a_hat || vaddr <= _userlimit);
2800 2811 if (khat_running == 0)
2801 2812 return (PFN_INVALID);
2802 2813
2803 2814 if (IN_VA_HOLE(vaddr))
2804 2815 return (PFN_INVALID);
2805 2816
2806 2817 XPV_DISALLOW_MIGRATE();
2807 2818 /*
2808 2819 * A very common use of hat_getpfnum() is from the DDI for kernel pages.
2809 2820 * Use the kmap_ptes (which also covers the 32 bit heap) to speed
2810 2821 * this up.
2811 2822 */
2812 2823 if (mmu.kmap_addr <= vaddr && vaddr < mmu.kmap_eaddr) {
2813 2824 x86pte_t pte;
2814 2825 pgcnt_t pg_index;
2815 2826
2816 2827 pg_index = mmu_btop(vaddr - mmu.kmap_addr);
2817 2828 pte = GET_PTE(PT_INDEX_PTR(mmu.kmap_ptes, pg_index));
2818 2829 if (PTE_ISVALID(pte))
2819 2830 /*LINTED [use of constant 0 causes a lint warning] */
2820 2831 pfn = PTE2PFN(pte, 0);
2821 2832 XPV_ALLOW_MIGRATE();
2822 2833 return (pfn);
2823 2834 }
2824 2835
2825 2836 ht = htable_getpage(hat, vaddr, &entry);
2826 2837 if (ht == NULL) {
2827 2838 XPV_ALLOW_MIGRATE();
2828 2839 return (PFN_INVALID);
2829 2840 }
2830 2841 ASSERT(vaddr >= ht->ht_vaddr);
2831 2842 ASSERT(vaddr <= HTABLE_LAST_PAGE(ht));
2832 2843 pfn = PTE2PFN(x86pte_get(ht, entry), ht->ht_level);
2833 2844 if (ht->ht_level > 0)
2834 2845 pfn += mmu_btop(vaddr & LEVEL_OFFSET(ht->ht_level));
2835 2846 htable_release(ht);
2836 2847 XPV_ALLOW_MIGRATE();
2837 2848 return (pfn);
2838 2849 }
2839 2850
2840 2851 /*
2841 2852 * int hat_probe(hat, addr)
2842 2853 * return 0 if no valid mapping is present. Faster version
2843 2854 * of hat_getattr in certain architectures.
2844 2855 */
2845 2856 int
2846 2857 hat_probe(hat_t *hat, caddr_t addr)
2847 2858 {
2848 2859 uintptr_t vaddr = ALIGN2PAGE(addr);
2849 2860 uint_t entry;
2850 2861 htable_t *ht;
2851 2862 pgcnt_t pg_off;
2852 2863
2853 2864 ASSERT(hat == kas.a_hat || vaddr <= _userlimit);
2854 2865 ASSERT(hat == kas.a_hat || AS_LOCK_HELD(hat->hat_as));
2855 2866 if (IN_VA_HOLE(vaddr))
2856 2867 return (0);
2857 2868
2858 2869 /*
2859 2870 * Most common use of hat_probe is from segmap. We special case it
2860 2871 * for performance.
2861 2872 */
2862 2873 if (mmu.kmap_addr <= vaddr && vaddr < mmu.kmap_eaddr) {
2863 2874 pg_off = mmu_btop(vaddr - mmu.kmap_addr);
2864 2875 if (mmu.pae_hat)
2865 2876 return (PTE_ISVALID(mmu.kmap_ptes[pg_off]));
2866 2877 else
2867 2878 return (PTE_ISVALID(
2868 2879 ((x86pte32_t *)mmu.kmap_ptes)[pg_off]));
2869 2880 }
2870 2881
2871 2882 ht = htable_getpage(hat, vaddr, &entry);
2872 2883 htable_release(ht);
2873 2884 return (ht != NULL);
2874 2885 }
2875 2886
2876 2887 /*
2877 2888 * Find out if the segment for hat_share()/hat_unshare() is DISM or locked ISM.
2878 2889 */
2879 2890 static int
2880 2891 is_it_dism(hat_t *hat, caddr_t va)
2881 2892 {
2882 2893 struct seg *seg;
2883 2894 struct shm_data *shmd;
2884 2895 struct spt_data *sptd;
2885 2896
2886 2897 seg = as_findseg(hat->hat_as, va, 0);
2887 2898 ASSERT(seg != NULL);
2888 2899 ASSERT(seg->s_base <= va);
2889 2900 shmd = (struct shm_data *)seg->s_data;
2890 2901 ASSERT(shmd != NULL);
2891 2902 sptd = (struct spt_data *)shmd->shm_sptseg->s_data;
2892 2903 ASSERT(sptd != NULL);
2893 2904 if (sptd->spt_flags & SHM_PAGEABLE)
2894 2905 return (1);
2895 2906 return (0);
2896 2907 }
2897 2908
2898 2909 /*
2899 2910 * Simple implementation of ISM. hat_share() is similar to hat_memload_array(),
2900 2911 * except that we use the ism_hat's existing mappings to determine the pages
2901 2912 * and protections to use for this hat. If we find a full properly aligned
2902 2913 * and sized pagetable, we will attempt to share the pagetable itself.
2903 2914 */
2904 2915 /*ARGSUSED*/
2905 2916 int
2906 2917 hat_share(
2907 2918 hat_t *hat,
2908 2919 caddr_t addr,
2909 2920 hat_t *ism_hat,
2910 2921 caddr_t src_addr,
2911 2922 size_t len, /* almost useless value, see below.. */
2912 2923 uint_t ismszc)
2913 2924 {
2914 2925 uintptr_t vaddr_start = (uintptr_t)addr;
2915 2926 uintptr_t vaddr;
2916 2927 uintptr_t eaddr = vaddr_start + len;
2917 2928 uintptr_t ism_addr_start = (uintptr_t)src_addr;
2918 2929 uintptr_t ism_addr = ism_addr_start;
2919 2930 uintptr_t e_ism_addr = ism_addr + len;
2920 2931 htable_t *ism_ht = NULL;
2921 2932 htable_t *ht;
2922 2933 x86pte_t pte;
2923 2934 page_t *pp;
2924 2935 pfn_t pfn;
2925 2936 level_t l;
2926 2937 pgcnt_t pgcnt;
2927 2938 uint_t prot;
2928 2939 int is_dism;
2929 2940 int flags;
2930 2941
2931 2942 /*
2932 2943 * We might be asked to share an empty DISM hat by as_dup()
2933 2944 */
2934 2945 ASSERT(hat != kas.a_hat);
2935 2946 ASSERT(eaddr <= _userlimit);
2936 2947 if (!(ism_hat->hat_flags & HAT_SHARED)) {
2937 2948 ASSERT(hat_get_mapped_size(ism_hat) == 0);
2938 2949 return (0);
2939 2950 }
2940 2951 XPV_DISALLOW_MIGRATE();
2941 2952
2942 2953 /*
2943 2954 * The SPT segment driver often passes us a size larger than there are
2944 2955 * valid mappings. That's because it rounds the segment size up to a
2945 2956 * large pagesize, even if the actual memory mapped by ism_hat is less.
2946 2957 */
2947 2958 ASSERT(IS_PAGEALIGNED(vaddr_start));
2948 2959 ASSERT(IS_PAGEALIGNED(ism_addr_start));
2949 2960 ASSERT(ism_hat->hat_flags & HAT_SHARED);
2950 2961 is_dism = is_it_dism(hat, addr);
2951 2962 while (ism_addr < e_ism_addr) {
2952 2963 /*
2953 2964 * use htable_walk to get the next valid ISM mapping
2954 2965 */
2955 2966 pte = htable_walk(ism_hat, &ism_ht, &ism_addr, e_ism_addr);
2956 2967 if (ism_ht == NULL)
2957 2968 break;
2958 2969
2959 2970 /*
2960 2971 * First check to see if we already share the page table.
2961 2972 */
2962 2973 l = ism_ht->ht_level;
2963 2974 vaddr = vaddr_start + (ism_addr - ism_addr_start);
2964 2975 ht = htable_lookup(hat, vaddr, l);
2965 2976 if (ht != NULL) {
2966 2977 if (ht->ht_flags & HTABLE_SHARED_PFN)
2967 2978 goto shared;
2968 2979 htable_release(ht);
2969 2980 goto not_shared;
2970 2981 }
2971 2982
2972 2983 /*
2973 2984 * Can't ever share top table.
2974 2985 */
2975 2986 if (l == mmu.max_level)
2976 2987 goto not_shared;
2977 2988
2978 2989 /*
2979 2990 * Avoid level mismatches later due to DISM faults.
2980 2991 */
2981 2992 if (is_dism && l > 0)
2982 2993 goto not_shared;
2983 2994
2984 2995 /*
2985 2996 * addresses and lengths must align
2986 2997 * table must be fully populated
2987 2998 * no lower level page tables
2988 2999 */
2989 3000 if (ism_addr != ism_ht->ht_vaddr ||
2990 3001 (vaddr & LEVEL_OFFSET(l + 1)) != 0)
2991 3002 goto not_shared;
2992 3003
2993 3004 /*
2994 3005 * The range of address space must cover a full table.
2995 3006 */
2996 3007 if (e_ism_addr - ism_addr < LEVEL_SIZE(l + 1))
2997 3008 goto not_shared;
2998 3009
2999 3010 /*
3000 3011 * All entries in the ISM page table must be leaf PTEs.
3001 3012 */
3002 3013 if (l > 0) {
3003 3014 int e;
3004 3015
3005 3016 /*
3006 3017 * We know the 0th is from htable_walk() above.
3007 3018 */
3008 3019 for (e = 1; e < HTABLE_NUM_PTES(ism_ht); ++e) {
3009 3020 x86pte_t pte;
3010 3021 pte = x86pte_get(ism_ht, e);
3011 3022 if (!PTE_ISPAGE(pte, l))
3012 3023 goto not_shared;
3013 3024 }
3014 3025 }
3015 3026
3016 3027 /*
3017 3028 * share the page table
3018 3029 */
3019 3030 ht = htable_create(hat, vaddr, l, ism_ht);
3020 3031 shared:
3021 3032 ASSERT(ht->ht_flags & HTABLE_SHARED_PFN);
3022 3033 ASSERT(ht->ht_shares == ism_ht);
3023 3034 hat->hat_ism_pgcnt +=
3024 3035 (ism_ht->ht_valid_cnt - ht->ht_valid_cnt) <<
3025 3036 (LEVEL_SHIFT(ht->ht_level) - MMU_PAGESHIFT);
3026 3037 ht->ht_valid_cnt = ism_ht->ht_valid_cnt;
3027 3038 htable_release(ht);
3028 3039 ism_addr = ism_ht->ht_vaddr + LEVEL_SIZE(l + 1);
3029 3040 htable_release(ism_ht);
3030 3041 ism_ht = NULL;
3031 3042 continue;
3032 3043
3033 3044 not_shared:
3034 3045 /*
3035 3046 * Unable to share the page table. Instead we will
3036 3047 * create new mappings from the values in the ISM mappings.
3037 3048 * Figure out what level size mappings to use;
3038 3049 */
3039 3050 for (l = ism_ht->ht_level; l > 0; --l) {
3040 3051 if (LEVEL_SIZE(l) <= eaddr - vaddr &&
3041 3052 (vaddr & LEVEL_OFFSET(l)) == 0)
3042 3053 break;
3043 3054 }
3044 3055
3045 3056 /*
3046 3057 * The ISM mapping might be larger than the share area,
3047 3058 * be careful to truncate it if needed.
3048 3059 */
3049 3060 if (eaddr - vaddr >= LEVEL_SIZE(ism_ht->ht_level)) {
3050 3061 pgcnt = mmu_btop(LEVEL_SIZE(ism_ht->ht_level));
3051 3062 } else {
3052 3063 pgcnt = mmu_btop(eaddr - vaddr);
3053 3064 l = 0;
3054 3065 }
3055 3066
3056 3067 pfn = PTE2PFN(pte, ism_ht->ht_level);
3057 3068 ASSERT(pfn != PFN_INVALID);
3058 3069 while (pgcnt > 0) {
3059 3070 /*
3060 3071 * Make a new pte for the PFN for this level.
3061 3072 * Copy protections for the pte from the ISM pte.
3062 3073 */
3063 3074 pp = page_numtopp_nolock(pfn);
3064 3075 ASSERT(pp != NULL);
3065 3076
3066 3077 prot = PROT_USER | PROT_READ | HAT_UNORDERED_OK;
3067 3078 if (PTE_GET(pte, PT_WRITABLE))
3068 3079 prot |= PROT_WRITE;
3069 3080 if (!PTE_GET(pte, PT_NX))
3070 3081 prot |= PROT_EXEC;
3071 3082
3072 3083 flags = HAT_LOAD;
3073 3084 if (!is_dism)
3074 3085 flags |= HAT_LOAD_LOCK | HAT_LOAD_NOCONSIST;
3075 3086 while (hati_load_common(hat, vaddr, pp, prot, flags,
3076 3087 l, pfn) != 0) {
3077 3088 if (l == 0)
3078 3089 panic("hati_load_common() failure");
3079 3090 --l;
3080 3091 }
3081 3092
3082 3093 vaddr += LEVEL_SIZE(l);
3083 3094 ism_addr += LEVEL_SIZE(l);
3084 3095 pfn += mmu_btop(LEVEL_SIZE(l));
3085 3096 pgcnt -= mmu_btop(LEVEL_SIZE(l));
3086 3097 }
3087 3098 }
3088 3099 if (ism_ht != NULL)
3089 3100 htable_release(ism_ht);
3090 3101 XPV_ALLOW_MIGRATE();
3091 3102 return (0);
3092 3103 }
3093 3104
3094 3105
3095 3106 /*
3096 3107 * hat_unshare() is similar to hat_unload_callback(), but
3097 3108 * we have to look for empty shared pagetables. Note that
3098 3109 * hat_unshare() is always invoked against an entire segment.
3099 3110 */
3100 3111 /*ARGSUSED*/
3101 3112 void
3102 3113 hat_unshare(hat_t *hat, caddr_t addr, size_t len, uint_t ismszc)
3103 3114 {
3104 3115 uint64_t vaddr = (uintptr_t)addr;
3105 3116 uintptr_t eaddr = vaddr + len;
3106 3117 htable_t *ht = NULL;
3107 3118 uint_t need_demaps = 0;
3108 3119 int flags = HAT_UNLOAD_UNMAP;
3109 3120 level_t l;
3110 3121
3111 3122 ASSERT(hat != kas.a_hat);
3112 3123 ASSERT(eaddr <= _userlimit);
3113 3124 ASSERT(IS_PAGEALIGNED(vaddr));
3114 3125 ASSERT(IS_PAGEALIGNED(eaddr));
3115 3126 XPV_DISALLOW_MIGRATE();
3116 3127
3117 3128 /*
3118 3129 * First go through and remove any shared pagetables.
3119 3130 *
3120 3131 * Note that it's ok to delay the TLB shootdown till the entire range is
3121 3132 * finished, because if hat_pageunload() were to unload a shared
3122 3133 * pagetable page, its hat_tlb_inval() will do a global TLB invalidate.
3123 3134 */
3124 3135 l = mmu.max_page_level;
3125 3136 if (l == mmu.max_level)
3126 3137 --l;
3127 3138 for (; l >= 0; --l) {
3128 3139 for (vaddr = (uintptr_t)addr; vaddr < eaddr;
3129 3140 vaddr = (vaddr & LEVEL_MASK(l + 1)) + LEVEL_SIZE(l + 1)) {
3130 3141 ASSERT(!IN_VA_HOLE(vaddr));
3131 3142 /*
3132 3143 * find a pagetable that maps the current address
3133 3144 */
3134 3145 ht = htable_lookup(hat, vaddr, l);
3135 3146 if (ht == NULL)
3136 3147 continue;
3137 3148 if (ht->ht_flags & HTABLE_SHARED_PFN) {
3138 3149 /*
3139 3150 * clear page count, set valid_cnt to 0,
3140 3151 * let htable_release() finish the job
3141 3152 */
3142 3153 hat->hat_ism_pgcnt -= ht->ht_valid_cnt <<
3143 3154 (LEVEL_SHIFT(ht->ht_level) - MMU_PAGESHIFT);
3144 3155 ht->ht_valid_cnt = 0;
3145 3156 need_demaps = 1;
3146 3157 }
3147 3158 htable_release(ht);
3148 3159 }
3149 3160 }
3150 3161
3151 3162 /*
3152 3163 * flush the TLBs - since we're probably dealing with MANY mappings
3153 3164 * we do just one CR3 reload.
3154 3165 */
3155 3166 if (!(hat->hat_flags & HAT_FREEING) && need_demaps)
3156 3167 hat_tlb_inval(hat, DEMAP_ALL_ADDR);
3157 3168
3158 3169 /*
3159 3170 * Now go back and clean up any unaligned mappings that
3160 3171 * couldn't share pagetables.
3161 3172 */
3162 3173 if (!is_it_dism(hat, addr))
3163 3174 flags |= HAT_UNLOAD_UNLOCK;
3164 3175 hat_unload(hat, addr, len, flags);
3165 3176 XPV_ALLOW_MIGRATE();
3166 3177 }
3167 3178
3168 3179
3169 3180 /*
3170 3181 * hat_reserve() does nothing
3171 3182 */
3172 3183 /*ARGSUSED*/
3173 3184 void
3174 3185 hat_reserve(struct as *as, caddr_t addr, size_t len)
3175 3186 {
3176 3187 }
3177 3188
3178 3189
3179 3190 /*
3180 3191 * Called when all mappings to a page should have write permission removed.
3181 3192 * Mostly stolen from hat_pagesync()
3182 3193 */
3183 3194 static void
3184 3195 hati_page_clrwrt(struct page *pp)
3185 3196 {
3186 3197 hment_t *hm = NULL;
3187 3198 htable_t *ht;
3188 3199 uint_t entry;
3189 3200 x86pte_t old;
3190 3201 x86pte_t new;
3191 3202 uint_t pszc = 0;
3192 3203
3193 3204 XPV_DISALLOW_MIGRATE();
3194 3205 next_size:
3195 3206 /*
3196 3207 * walk thru the mapping list clearing write permission
3197 3208 */
3198 3209 x86_hm_enter(pp);
3199 3210 while ((hm = hment_walk(pp, &ht, &entry, hm)) != NULL) {
3200 3211 if (ht->ht_level < pszc)
3201 3212 continue;
3202 3213 old = x86pte_get(ht, entry);
3203 3214
3204 3215 for (;;) {
3205 3216 /*
3206 3217 * Is this mapping of interest?
3207 3218 */
3208 3219 if (PTE2PFN(old, ht->ht_level) != pp->p_pagenum ||
3209 3220 PTE_GET(old, PT_WRITABLE) == 0)
3210 3221 break;
3211 3222
3212 3223 /*
3213 3224 * Clear ref/mod writable bits. This requires cross
3214 3225 * calls to ensure any executing TLBs see cleared bits.
3215 3226 */
3216 3227 new = old;
3217 3228 PTE_CLR(new, PT_REF | PT_MOD | PT_WRITABLE);
3218 3229 old = hati_update_pte(ht, entry, old, new);
3219 3230 if (old != 0)
3220 3231 continue;
3221 3232
3222 3233 break;
3223 3234 }
3224 3235 }
3225 3236 x86_hm_exit(pp);
3226 3237 while (pszc < pp->p_szc) {
3227 3238 page_t *tpp;
3228 3239 pszc++;
3229 3240 tpp = PP_GROUPLEADER(pp, pszc);
3230 3241 if (pp != tpp) {
3231 3242 pp = tpp;
3232 3243 goto next_size;
3233 3244 }
3234 3245 }
3235 3246 XPV_ALLOW_MIGRATE();
3236 3247 }
3237 3248
3238 3249 /*
3239 3250 * void hat_page_setattr(pp, flag)
3240 3251 * void hat_page_clrattr(pp, flag)
3241 3252 * used to set/clr ref/mod bits.
3242 3253 */
3243 3254 void
3244 3255 hat_page_setattr(struct page *pp, uint_t flag)
3245 3256 {
3246 3257 vnode_t *vp = pp->p_vnode;
3247 3258 kmutex_t *vphm = NULL;
3248 3259 page_t **listp;
3249 3260 int noshuffle;
3250 3261
3251 3262 noshuffle = flag & P_NSH;
3252 3263 flag &= ~P_NSH;
3253 3264
3254 3265 if (PP_GETRM(pp, flag) == flag)
3255 3266 return;
3256 3267
3257 3268 if ((flag & P_MOD) != 0 && vp != NULL && IS_VMODSORT(vp) &&
3258 3269 !noshuffle) {
3259 3270 vphm = page_vnode_mutex(vp);
3260 3271 mutex_enter(vphm);
3261 3272 }
3262 3273
3263 3274 PP_SETRM(pp, flag);
3264 3275
3265 3276 if (vphm != NULL) {
3266 3277
3267 3278 /*
3268 3279 * Some File Systems examine v_pages for NULL w/o
3269 3280 * grabbing the vphm mutex. Must not let it become NULL when
3270 3281 * pp is the only page on the list.
3271 3282 */
3272 3283 if (pp->p_vpnext != pp) {
3273 3284 page_vpsub(&vp->v_pages, pp);
3274 3285 if (vp->v_pages != NULL)
3275 3286 listp = &vp->v_pages->p_vpprev->p_vpnext;
3276 3287 else
3277 3288 listp = &vp->v_pages;
3278 3289 page_vpadd(listp, pp);
3279 3290 }
3280 3291 mutex_exit(vphm);
3281 3292 }
3282 3293 }
3283 3294
3284 3295 void
3285 3296 hat_page_clrattr(struct page *pp, uint_t flag)
3286 3297 {
3287 3298 vnode_t *vp = pp->p_vnode;
3288 3299 ASSERT(!(flag & ~(P_MOD | P_REF | P_RO)));
3289 3300
3290 3301 /*
3291 3302 * Caller is expected to hold page's io lock for VMODSORT to work
3292 3303 * correctly with pvn_vplist_dirty() and pvn_getdirty() when mod
3293 3304 * bit is cleared.
3294 3305 * We don't have assert to avoid tripping some existing third party
3295 3306 * code. The dirty page is moved back to top of the v_page list
3296 3307 * after IO is done in pvn_write_done().
3297 3308 */
3298 3309 PP_CLRRM(pp, flag);
3299 3310
3300 3311 if ((flag & P_MOD) != 0 && vp != NULL && IS_VMODSORT(vp)) {
3301 3312
3302 3313 /*
3303 3314 * VMODSORT works by removing write permissions and getting
3304 3315 * a fault when a page is made dirty. At this point
3305 3316 * we need to remove write permission from all mappings
3306 3317 * to this page.
3307 3318 */
3308 3319 hati_page_clrwrt(pp);
3309 3320 }
3310 3321 }
3311 3322
3312 3323 /*
3313 3324 * If flag is specified, returns 0 if attribute is disabled
3314 3325 * and non zero if enabled. If flag specifes multiple attributes
3315 3326 * then returns 0 if ALL attributes are disabled. This is an advisory
3316 3327 * call.
3317 3328 */
3318 3329 uint_t
3319 3330 hat_page_getattr(struct page *pp, uint_t flag)
3320 3331 {
3321 3332 return (PP_GETRM(pp, flag));
3322 3333 }
3323 3334
3324 3335
3325 3336 /*
3326 3337 * common code used by hat_pageunload() and hment_steal()
3327 3338 */
3328 3339 hment_t *
3329 3340 hati_page_unmap(page_t *pp, htable_t *ht, uint_t entry)
3330 3341 {
3331 3342 x86pte_t old_pte;
3332 3343 pfn_t pfn = pp->p_pagenum;
3333 3344 hment_t *hm;
3334 3345
3335 3346 /*
3336 3347 * We need to acquire a hold on the htable in order to
3337 3348 * do the invalidate. We know the htable must exist, since
3338 3349 * unmap's don't release the htable until after removing any
3339 3350 * hment. Having x86_hm_enter() keeps that from proceeding.
3340 3351 */
3341 3352 htable_acquire(ht);
3342 3353
3343 3354 /*
3344 3355 * Invalidate the PTE and remove the hment.
3345 3356 */
3346 3357 old_pte = x86pte_inval(ht, entry, 0, NULL, B_TRUE);
3347 3358 if (PTE2PFN(old_pte, ht->ht_level) != pfn) {
3348 3359 panic("x86pte_inval() failure found PTE = " FMT_PTE
3349 3360 " pfn being unmapped is %lx ht=0x%lx entry=0x%x",
3350 3361 old_pte, pfn, (uintptr_t)ht, entry);
3351 3362 }
3352 3363
3353 3364 /*
3354 3365 * Clean up all the htable information for this mapping
3355 3366 */
3356 3367 ASSERT(ht->ht_valid_cnt > 0);
3357 3368 HTABLE_DEC(ht->ht_valid_cnt);
3358 3369 PGCNT_DEC(ht->ht_hat, ht->ht_level);
3359 3370
3360 3371 /*
3361 3372 * sync ref/mod bits to the page_t
3362 3373 */
3363 3374 if (PTE_GET(old_pte, PT_SOFTWARE) < PT_NOSYNC)
3364 3375 hati_sync_pte_to_page(pp, old_pte, ht->ht_level);
3365 3376
3366 3377 /*
3367 3378 * Remove the mapping list entry for this page.
3368 3379 */
3369 3380 hm = hment_remove(pp, ht, entry);
3370 3381
3371 3382 /*
3372 3383 * drop the mapping list lock so that we might free the
3373 3384 * hment and htable.
3374 3385 */
3375 3386 x86_hm_exit(pp);
3376 3387 htable_release(ht);
3377 3388 return (hm);
3378 3389 }
3379 3390
3380 3391 extern int vpm_enable;
3381 3392 /*
3382 3393 * Unload all translations to a page. If the page is a subpage of a large
3383 3394 * page, the large page mappings are also removed.
3384 3395 *
3385 3396 * The forceflags are unused.
3386 3397 */
3387 3398
3388 3399 /*ARGSUSED*/
3389 3400 static int
3390 3401 hati_pageunload(struct page *pp, uint_t pg_szcd, uint_t forceflag)
3391 3402 {
3392 3403 page_t *cur_pp = pp;
3393 3404 hment_t *hm;
3394 3405 hment_t *prev;
3395 3406 htable_t *ht;
3396 3407 uint_t entry;
3397 3408 level_t level;
3398 3409
3399 3410 XPV_DISALLOW_MIGRATE();
3400 3411
3401 3412 /*
3402 3413 * prevent recursion due to kmem_free()
3403 3414 */
3404 3415 ++curthread->t_hatdepth;
3405 3416 ASSERT(curthread->t_hatdepth < 16);
3406 3417
3407 3418 #if defined(__amd64)
3408 3419 /*
3409 3420 * clear the vpm ref.
3410 3421 */
3411 3422 if (vpm_enable) {
3412 3423 pp->p_vpmref = 0;
3413 3424 }
3414 3425 #endif
3415 3426 /*
3416 3427 * The loop with next_size handles pages with multiple pagesize mappings
3417 3428 */
3418 3429 next_size:
3419 3430 for (;;) {
3420 3431
3421 3432 /*
3422 3433 * Get a mapping list entry
3423 3434 */
3424 3435 x86_hm_enter(cur_pp);
3425 3436 for (prev = NULL; ; prev = hm) {
3426 3437 hm = hment_walk(cur_pp, &ht, &entry, prev);
3427 3438 if (hm == NULL) {
3428 3439 x86_hm_exit(cur_pp);
3429 3440
3430 3441 /*
3431 3442 * If not part of a larger page, we're done.
3432 3443 */
3433 3444 if (cur_pp->p_szc <= pg_szcd) {
3434 3445 ASSERT(curthread->t_hatdepth > 0);
3435 3446 --curthread->t_hatdepth;
3436 3447 XPV_ALLOW_MIGRATE();
3437 3448 return (0);
3438 3449 }
3439 3450
3440 3451 /*
3441 3452 * Else check the next larger page size.
3442 3453 * hat_page_demote() may decrease p_szc
3443 3454 * but that's ok we'll just take an extra
3444 3455 * trip discover there're no larger mappings
3445 3456 * and return.
3446 3457 */
3447 3458 ++pg_szcd;
3448 3459 cur_pp = PP_GROUPLEADER(cur_pp, pg_szcd);
3449 3460 goto next_size;
3450 3461 }
3451 3462
3452 3463 /*
3453 3464 * If this mapping size matches, remove it.
3454 3465 */
3455 3466 level = ht->ht_level;
3456 3467 if (level == pg_szcd)
3457 3468 break;
3458 3469 }
3459 3470
3460 3471 /*
3461 3472 * Remove the mapping list entry for this page.
3462 3473 * Note this does the x86_hm_exit() for us.
3463 3474 */
3464 3475 hm = hati_page_unmap(cur_pp, ht, entry);
3465 3476 if (hm != NULL)
3466 3477 hment_free(hm);
3467 3478 }
3468 3479 }
3469 3480
3470 3481 int
3471 3482 hat_pageunload(struct page *pp, uint_t forceflag)
3472 3483 {
3473 3484 ASSERT(PAGE_EXCL(pp));
3474 3485 return (hati_pageunload(pp, 0, forceflag));
3475 3486 }
3476 3487
3477 3488 /*
3478 3489 * Unload all large mappings to pp and reduce by 1 p_szc field of every large
3479 3490 * page level that included pp.
3480 3491 *
3481 3492 * pp must be locked EXCL. Even though no other constituent pages are locked
3482 3493 * it's legal to unload large mappings to pp because all constituent pages of
3483 3494 * large locked mappings have to be locked SHARED. therefore if we have EXCL
3484 3495 * lock on one of constituent pages none of the large mappings to pp are
3485 3496 * locked.
3486 3497 *
3487 3498 * Change (always decrease) p_szc field starting from the last constituent
3488 3499 * page and ending with root constituent page so that root's pszc always shows
3489 3500 * the area where hat_page_demote() may be active.
3490 3501 *
3491 3502 * This mechanism is only used for file system pages where it's not always
3492 3503 * possible to get EXCL locks on all constituent pages to demote the size code
3493 3504 * (as is done for anonymous or kernel large pages).
3494 3505 */
3495 3506 void
3496 3507 hat_page_demote(page_t *pp)
3497 3508 {
3498 3509 uint_t pszc;
3499 3510 uint_t rszc;
3500 3511 uint_t szc;
3501 3512 page_t *rootpp;
3502 3513 page_t *firstpp;
3503 3514 page_t *lastpp;
3504 3515 pgcnt_t pgcnt;
3505 3516
3506 3517 ASSERT(PAGE_EXCL(pp));
3507 3518 ASSERT(!PP_ISFREE(pp));
3508 3519 ASSERT(page_szc_lock_assert(pp));
3509 3520
3510 3521 if (pp->p_szc == 0)
3511 3522 return;
3512 3523
3513 3524 rootpp = PP_GROUPLEADER(pp, 1);
3514 3525 (void) hati_pageunload(rootpp, 1, HAT_FORCE_PGUNLOAD);
3515 3526
3516 3527 /*
3517 3528 * all large mappings to pp are gone
3518 3529 * and no new can be setup since pp is locked exclusively.
3519 3530 *
3520 3531 * Lock the root to make sure there's only one hat_page_demote()
3521 3532 * outstanding within the area of this root's pszc.
3522 3533 *
3523 3534 * Second potential hat_page_demote() is already eliminated by upper
3524 3535 * VM layer via page_szc_lock() but we don't rely on it and use our
3525 3536 * own locking (so that upper layer locking can be changed without
3526 3537 * assumptions that hat depends on upper layer VM to prevent multiple
3527 3538 * hat_page_demote() to be issued simultaneously to the same large
3528 3539 * page).
3529 3540 */
3530 3541 again:
3531 3542 pszc = pp->p_szc;
3532 3543 if (pszc == 0)
3533 3544 return;
3534 3545 rootpp = PP_GROUPLEADER(pp, pszc);
3535 3546 x86_hm_enter(rootpp);
3536 3547 /*
3537 3548 * If root's p_szc is different from pszc we raced with another
3538 3549 * hat_page_demote(). Drop the lock and try to find the root again.
3539 3550 * If root's p_szc is greater than pszc previous hat_page_demote() is
3540 3551 * not done yet. Take and release mlist lock of root's root to wait
3541 3552 * for previous hat_page_demote() to complete.
3542 3553 */
3543 3554 if ((rszc = rootpp->p_szc) != pszc) {
3544 3555 x86_hm_exit(rootpp);
3545 3556 if (rszc > pszc) {
3546 3557 /* p_szc of a locked non free page can't increase */
3547 3558 ASSERT(pp != rootpp);
3548 3559
3549 3560 rootpp = PP_GROUPLEADER(rootpp, rszc);
3550 3561 x86_hm_enter(rootpp);
3551 3562 x86_hm_exit(rootpp);
3552 3563 }
3553 3564 goto again;
3554 3565 }
3555 3566 ASSERT(pp->p_szc == pszc);
3556 3567
3557 3568 /*
3558 3569 * Decrement by 1 p_szc of every constituent page of a region that
3559 3570 * covered pp. For example if original szc is 3 it gets changed to 2
3560 3571 * everywhere except in region 2 that covered pp. Region 2 that
3561 3572 * covered pp gets demoted to 1 everywhere except in region 1 that
3562 3573 * covered pp. The region 1 that covered pp is demoted to region
3563 3574 * 0. It's done this way because from region 3 we removed level 3
3564 3575 * mappings, from region 2 that covered pp we removed level 2 mappings
3565 3576 * and from region 1 that covered pp we removed level 1 mappings. All
3566 3577 * changes are done from from high pfn's to low pfn's so that roots
3567 3578 * are changed last allowing one to know the largest region where
3568 3579 * hat_page_demote() is stil active by only looking at the root page.
3569 3580 *
3570 3581 * This algorithm is implemented in 2 while loops. First loop changes
3571 3582 * p_szc of pages to the right of pp's level 1 region and second
3572 3583 * loop changes p_szc of pages of level 1 region that covers pp
3573 3584 * and all pages to the left of level 1 region that covers pp.
3574 3585 * In the first loop p_szc keeps dropping with every iteration
3575 3586 * and in the second loop it keeps increasing with every iteration.
3576 3587 *
3577 3588 * First loop description: Demote pages to the right of pp outside of
3578 3589 * level 1 region that covers pp. In every iteration of the while
3579 3590 * loop below find the last page of szc region and the first page of
3580 3591 * (szc - 1) region that is immediately to the right of (szc - 1)
3581 3592 * region that covers pp. From last such page to first such page
3582 3593 * change every page's szc to szc - 1. Decrement szc and continue
3583 3594 * looping until szc is 1. If pp belongs to the last (szc - 1) region
3584 3595 * of szc region skip to the next iteration.
3585 3596 */
3586 3597 szc = pszc;
3587 3598 while (szc > 1) {
3588 3599 lastpp = PP_GROUPLEADER(pp, szc);
3589 3600 pgcnt = page_get_pagecnt(szc);
3590 3601 lastpp += pgcnt - 1;
3591 3602 firstpp = PP_GROUPLEADER(pp, (szc - 1));
3592 3603 pgcnt = page_get_pagecnt(szc - 1);
3593 3604 if (lastpp - firstpp < pgcnt) {
3594 3605 szc--;
3595 3606 continue;
3596 3607 }
3597 3608 firstpp += pgcnt;
3598 3609 while (lastpp != firstpp) {
3599 3610 ASSERT(lastpp->p_szc == pszc);
3600 3611 lastpp->p_szc = szc - 1;
3601 3612 lastpp--;
3602 3613 }
3603 3614 firstpp->p_szc = szc - 1;
3604 3615 szc--;
3605 3616 }
3606 3617
3607 3618 /*
3608 3619 * Second loop description:
3609 3620 * First iteration changes p_szc to 0 of every
3610 3621 * page of level 1 region that covers pp.
3611 3622 * Subsequent iterations find last page of szc region
3612 3623 * immediately to the left of szc region that covered pp
3613 3624 * and first page of (szc + 1) region that covers pp.
3614 3625 * From last to first page change p_szc of every page to szc.
3615 3626 * Increment szc and continue looping until szc is pszc.
3616 3627 * If pp belongs to the fist szc region of (szc + 1) region
3617 3628 * skip to the next iteration.
3618 3629 *
3619 3630 */
3620 3631 szc = 0;
3621 3632 while (szc < pszc) {
3622 3633 firstpp = PP_GROUPLEADER(pp, (szc + 1));
3623 3634 if (szc == 0) {
3624 3635 pgcnt = page_get_pagecnt(1);
3625 3636 lastpp = firstpp + (pgcnt - 1);
3626 3637 } else {
3627 3638 lastpp = PP_GROUPLEADER(pp, szc);
3628 3639 if (firstpp == lastpp) {
3629 3640 szc++;
3630 3641 continue;
3631 3642 }
3632 3643 lastpp--;
3633 3644 pgcnt = page_get_pagecnt(szc);
3634 3645 }
3635 3646 while (lastpp != firstpp) {
3636 3647 ASSERT(lastpp->p_szc == pszc);
3637 3648 lastpp->p_szc = szc;
3638 3649 lastpp--;
3639 3650 }
3640 3651 firstpp->p_szc = szc;
3641 3652 if (firstpp == rootpp)
3642 3653 break;
3643 3654 szc++;
3644 3655 }
3645 3656 x86_hm_exit(rootpp);
3646 3657 }
3647 3658
3648 3659 /*
3649 3660 * get hw stats from hardware into page struct and reset hw stats
3650 3661 * returns attributes of page
3651 3662 * Flags for hat_pagesync, hat_getstat, hat_sync
3652 3663 *
3653 3664 * define HAT_SYNC_ZERORM 0x01
3654 3665 *
3655 3666 * Additional flags for hat_pagesync
3656 3667 *
3657 3668 * define HAT_SYNC_STOPON_REF 0x02
3658 3669 * define HAT_SYNC_STOPON_MOD 0x04
3659 3670 * define HAT_SYNC_STOPON_RM 0x06
3660 3671 * define HAT_SYNC_STOPON_SHARED 0x08
3661 3672 */
3662 3673 uint_t
3663 3674 hat_pagesync(struct page *pp, uint_t flags)
3664 3675 {
3665 3676 hment_t *hm = NULL;
3666 3677 htable_t *ht;
3667 3678 uint_t entry;
3668 3679 x86pte_t old, save_old;
3669 3680 x86pte_t new;
3670 3681 uchar_t nrmbits = P_REF|P_MOD|P_RO;
3671 3682 extern ulong_t po_share;
3672 3683 page_t *save_pp = pp;
3673 3684 uint_t pszc = 0;
3674 3685
3675 3686 ASSERT(PAGE_LOCKED(pp) || panicstr);
3676 3687
3677 3688 if (PP_ISRO(pp) && (flags & HAT_SYNC_STOPON_MOD))
3678 3689 return (pp->p_nrm & nrmbits);
3679 3690
3680 3691 if ((flags & HAT_SYNC_ZERORM) == 0) {
3681 3692
3682 3693 if ((flags & HAT_SYNC_STOPON_REF) != 0 && PP_ISREF(pp))
3683 3694 return (pp->p_nrm & nrmbits);
3684 3695
3685 3696 if ((flags & HAT_SYNC_STOPON_MOD) != 0 && PP_ISMOD(pp))
3686 3697 return (pp->p_nrm & nrmbits);
3687 3698
3688 3699 if ((flags & HAT_SYNC_STOPON_SHARED) != 0 &&
3689 3700 hat_page_getshare(pp) > po_share) {
3690 3701 if (PP_ISRO(pp))
3691 3702 PP_SETREF(pp);
3692 3703 return (pp->p_nrm & nrmbits);
3693 3704 }
3694 3705 }
3695 3706
3696 3707 XPV_DISALLOW_MIGRATE();
3697 3708 next_size:
3698 3709 /*
3699 3710 * walk thru the mapping list syncing (and clearing) ref/mod bits.
3700 3711 */
3701 3712 x86_hm_enter(pp);
3702 3713 while ((hm = hment_walk(pp, &ht, &entry, hm)) != NULL) {
3703 3714 if (ht->ht_level < pszc)
3704 3715 continue;
3705 3716 old = x86pte_get(ht, entry);
3706 3717 try_again:
3707 3718
3708 3719 ASSERT(PTE2PFN(old, ht->ht_level) == pp->p_pagenum);
3709 3720
3710 3721 if (PTE_GET(old, PT_REF | PT_MOD) == 0)
3711 3722 continue;
3712 3723
3713 3724 save_old = old;
3714 3725 if ((flags & HAT_SYNC_ZERORM) != 0) {
3715 3726
3716 3727 /*
3717 3728 * Need to clear ref or mod bits. Need to demap
3718 3729 * to make sure any executing TLBs see cleared bits.
3719 3730 */
3720 3731 new = old;
3721 3732 PTE_CLR(new, PT_REF | PT_MOD);
3722 3733 old = hati_update_pte(ht, entry, old, new);
3723 3734 if (old != 0)
3724 3735 goto try_again;
3725 3736
3726 3737 old = save_old;
3727 3738 }
3728 3739
3729 3740 /*
3730 3741 * Sync the PTE
3731 3742 */
3732 3743 if (!(flags & HAT_SYNC_ZERORM) &&
3733 3744 PTE_GET(old, PT_SOFTWARE) <= PT_NOSYNC)
3734 3745 hati_sync_pte_to_page(pp, old, ht->ht_level);
3735 3746
3736 3747 /*
3737 3748 * can stop short if we found a ref'd or mod'd page
3738 3749 */
3739 3750 if ((flags & HAT_SYNC_STOPON_MOD) && PP_ISMOD(save_pp) ||
3740 3751 (flags & HAT_SYNC_STOPON_REF) && PP_ISREF(save_pp)) {
3741 3752 x86_hm_exit(pp);
3742 3753 goto done;
3743 3754 }
3744 3755 }
3745 3756 x86_hm_exit(pp);
3746 3757 while (pszc < pp->p_szc) {
3747 3758 page_t *tpp;
3748 3759 pszc++;
3749 3760 tpp = PP_GROUPLEADER(pp, pszc);
3750 3761 if (pp != tpp) {
3751 3762 pp = tpp;
3752 3763 goto next_size;
3753 3764 }
3754 3765 }
3755 3766 done:
3756 3767 XPV_ALLOW_MIGRATE();
3757 3768 return (save_pp->p_nrm & nrmbits);
3758 3769 }
3759 3770
3760 3771 /*
3761 3772 * returns approx number of mappings to this pp. A return of 0 implies
3762 3773 * there are no mappings to the page.
3763 3774 */
3764 3775 ulong_t
3765 3776 hat_page_getshare(page_t *pp)
3766 3777 {
3767 3778 uint_t cnt;
3768 3779 cnt = hment_mapcnt(pp);
3769 3780 #if defined(__amd64)
3770 3781 if (vpm_enable && pp->p_vpmref) {
3771 3782 cnt += 1;
3772 3783 }
3773 3784 #endif
3774 3785 return (cnt);
3775 3786 }
3776 3787
3777 3788 /*
3778 3789 * Return 1 the number of mappings exceeds sh_thresh. Return 0
3779 3790 * otherwise.
3780 3791 */
3781 3792 int
3782 3793 hat_page_checkshare(page_t *pp, ulong_t sh_thresh)
3783 3794 {
3784 3795 return (hat_page_getshare(pp) > sh_thresh);
3785 3796 }
3786 3797
3787 3798 /*
3788 3799 * hat_softlock isn't supported anymore
3789 3800 */
3790 3801 /*ARGSUSED*/
3791 3802 faultcode_t
3792 3803 hat_softlock(
3793 3804 hat_t *hat,
3794 3805 caddr_t addr,
3795 3806 size_t *len,
3796 3807 struct page **page_array,
3797 3808 uint_t flags)
3798 3809 {
3799 3810 return (FC_NOSUPPORT);
3800 3811 }
3801 3812
3802 3813
3803 3814
3804 3815 /*
3805 3816 * Routine to expose supported HAT features to platform independent code.
3806 3817 */
3807 3818 /*ARGSUSED*/
3808 3819 int
3809 3820 hat_supported(enum hat_features feature, void *arg)
3810 3821 {
3811 3822 switch (feature) {
3812 3823
3813 3824 case HAT_SHARED_PT: /* this is really ISM */
3814 3825 return (1);
3815 3826
3816 3827 case HAT_DYNAMIC_ISM_UNMAP:
3817 3828 return (0);
3818 3829
3819 3830 case HAT_VMODSORT:
3820 3831 return (1);
3821 3832
3822 3833 case HAT_SHARED_REGIONS:
3823 3834 return (0);
3824 3835
3825 3836 default:
3826 3837 panic("hat_supported() - unknown feature");
3827 3838 }
3828 3839 return (0);
3829 3840 }
3830 3841
3831 3842 /*
3832 3843 * Called when a thread is exiting and has been switched to the kernel AS
3833 3844 */
3834 3845 void
3835 3846 hat_thread_exit(kthread_t *thd)
3836 3847 {
3837 3848 ASSERT(thd->t_procp->p_as == &kas);
3838 3849 XPV_DISALLOW_MIGRATE();
3839 3850 hat_switch(thd->t_procp->p_as->a_hat);
3840 3851 XPV_ALLOW_MIGRATE();
3841 3852 }
3842 3853
3843 3854 /*
3844 3855 * Setup the given brand new hat structure as the new HAT on this cpu's mmu.
3845 3856 */
3846 3857 /*ARGSUSED*/
3847 3858 void
3848 3859 hat_setup(hat_t *hat, int flags)
3849 3860 {
3850 3861 XPV_DISALLOW_MIGRATE();
3851 3862 kpreempt_disable();
3852 3863
3853 3864 hat_switch(hat);
3854 3865
3855 3866 kpreempt_enable();
3856 3867 XPV_ALLOW_MIGRATE();
3857 3868 }
3858 3869
3859 3870 /*
3860 3871 * Prepare for a CPU private mapping for the given address.
3861 3872 *
3862 3873 * The address can only be used from a single CPU and can be remapped
3863 3874 * using hat_mempte_remap(). Return the address of the PTE.
3864 3875 *
3865 3876 * We do the htable_create() if necessary and increment the valid count so
3866 3877 * the htable can't disappear. We also hat_devload() the page table into
3867 3878 * kernel so that the PTE is quickly accessed.
3868 3879 */
3869 3880 hat_mempte_t
3870 3881 hat_mempte_setup(caddr_t addr)
3871 3882 {
3872 3883 uintptr_t va = (uintptr_t)addr;
3873 3884 htable_t *ht;
3874 3885 uint_t entry;
3875 3886 x86pte_t oldpte;
3876 3887 hat_mempte_t p;
3877 3888
3878 3889 ASSERT(IS_PAGEALIGNED(va));
3879 3890 ASSERT(!IN_VA_HOLE(va));
3880 3891 ++curthread->t_hatdepth;
3881 3892 XPV_DISALLOW_MIGRATE();
3882 3893 ht = htable_getpte(kas.a_hat, va, &entry, &oldpte, 0);
3883 3894 if (ht == NULL) {
3884 3895 ht = htable_create(kas.a_hat, va, 0, NULL);
3885 3896 entry = htable_va2entry(va, ht);
3886 3897 ASSERT(ht->ht_level == 0);
3887 3898 oldpte = x86pte_get(ht, entry);
3888 3899 }
3889 3900 if (PTE_ISVALID(oldpte))
3890 3901 panic("hat_mempte_setup(): address already mapped"
3891 3902 "ht=%p, entry=%d, pte=" FMT_PTE, (void *)ht, entry, oldpte);
3892 3903
3893 3904 /*
3894 3905 * increment ht_valid_cnt so that the pagetable can't disappear
3895 3906 */
3896 3907 HTABLE_INC(ht->ht_valid_cnt);
3897 3908
3898 3909 /*
3899 3910 * return the PTE physical address to the caller.
3900 3911 */
3901 3912 htable_release(ht);
3902 3913 XPV_ALLOW_MIGRATE();
3903 3914 p = PT_INDEX_PHYSADDR(pfn_to_pa(ht->ht_pfn), entry);
3904 3915 --curthread->t_hatdepth;
3905 3916 return (p);
3906 3917 }
3907 3918
3908 3919 /*
3909 3920 * Release a CPU private mapping for the given address.
3910 3921 * We decrement the htable valid count so it might be destroyed.
3911 3922 */
3912 3923 /*ARGSUSED1*/
3913 3924 void
3914 3925 hat_mempte_release(caddr_t addr, hat_mempte_t pte_pa)
3915 3926 {
3916 3927 htable_t *ht;
3917 3928
3918 3929 XPV_DISALLOW_MIGRATE();
3919 3930 /*
3920 3931 * invalidate any left over mapping and decrement the htable valid count
3921 3932 */
3922 3933 #ifdef __xpv
3923 3934 if (HYPERVISOR_update_va_mapping((uintptr_t)addr, 0,
3924 3935 UVMF_INVLPG | UVMF_LOCAL))
3925 3936 panic("HYPERVISOR_update_va_mapping() failed");
3926 3937 #else
3927 3938 {
3928 3939 x86pte_t *pteptr;
3929 3940
3930 3941 pteptr = x86pte_mapin(mmu_btop(pte_pa),
3931 3942 (pte_pa & MMU_PAGEOFFSET) >> mmu.pte_size_shift, NULL);
3932 3943 if (mmu.pae_hat)
3933 3944 *pteptr = 0;
3934 3945 else
3935 3946 *(x86pte32_t *)pteptr = 0;
3936 3947 mmu_tlbflush_entry(addr);
3937 3948 x86pte_mapout();
3938 3949 }
3939 3950 #endif
3940 3951
3941 3952 ht = htable_getpte(kas.a_hat, ALIGN2PAGE(addr), NULL, NULL, 0);
3942 3953 if (ht == NULL)
3943 3954 panic("hat_mempte_release(): invalid address");
3944 3955 ASSERT(ht->ht_level == 0);
3945 3956 HTABLE_DEC(ht->ht_valid_cnt);
3946 3957 htable_release(ht);
3947 3958 XPV_ALLOW_MIGRATE();
3948 3959 }
3949 3960
3950 3961 /*
3951 3962 * Apply a temporary CPU private mapping to a page. We flush the TLB only
3952 3963 * on this CPU, so this ought to have been called with preemption disabled.
3953 3964 */
3954 3965 void
3955 3966 hat_mempte_remap(
3956 3967 pfn_t pfn,
3957 3968 caddr_t addr,
3958 3969 hat_mempte_t pte_pa,
3959 3970 uint_t attr,
3960 3971 uint_t flags)
3961 3972 {
3962 3973 uintptr_t va = (uintptr_t)addr;
3963 3974 x86pte_t pte;
3964 3975
3965 3976 /*
3966 3977 * Remap the given PTE to the new page's PFN. Invalidate only
3967 3978 * on this CPU.
3968 3979 */
3969 3980 #ifdef DEBUG
3970 3981 htable_t *ht;
3971 3982 uint_t entry;
3972 3983
3973 3984 ASSERT(IS_PAGEALIGNED(va));
3974 3985 ASSERT(!IN_VA_HOLE(va));
3975 3986 ht = htable_getpte(kas.a_hat, va, &entry, NULL, 0);
3976 3987 ASSERT(ht != NULL);
3977 3988 ASSERT(ht->ht_level == 0);
3978 3989 ASSERT(ht->ht_valid_cnt > 0);
3979 3990 ASSERT(ht->ht_pfn == mmu_btop(pte_pa));
3980 3991 htable_release(ht);
3981 3992 #endif
3982 3993 XPV_DISALLOW_MIGRATE();
3983 3994 pte = hati_mkpte(pfn, attr, 0, flags);
3984 3995 #ifdef __xpv
3985 3996 if (HYPERVISOR_update_va_mapping(va, pte, UVMF_INVLPG | UVMF_LOCAL))
3986 3997 panic("HYPERVISOR_update_va_mapping() failed");
3987 3998 #else
3988 3999 {
3989 4000 x86pte_t *pteptr;
3990 4001
3991 4002 pteptr = x86pte_mapin(mmu_btop(pte_pa),
3992 4003 (pte_pa & MMU_PAGEOFFSET) >> mmu.pte_size_shift, NULL);
3993 4004 if (mmu.pae_hat)
3994 4005 *(x86pte_t *)pteptr = pte;
3995 4006 else
3996 4007 *(x86pte32_t *)pteptr = (x86pte32_t)pte;
3997 4008 mmu_tlbflush_entry(addr);
3998 4009 x86pte_mapout();
3999 4010 }
4000 4011 #endif
4001 4012 XPV_ALLOW_MIGRATE();
4002 4013 }
4003 4014
4004 4015
4005 4016
4006 4017 /*
4007 4018 * Hat locking functions
4008 4019 * XXX - these two functions are currently being used by hatstats
4009 4020 * they can be removed by using a per-as mutex for hatstats.
4010 4021 */
4011 4022 void
4012 4023 hat_enter(hat_t *hat)
4013 4024 {
4014 4025 mutex_enter(&hat->hat_mutex);
4015 4026 }
4016 4027
4017 4028 void
4018 4029 hat_exit(hat_t *hat)
4019 4030 {
4020 4031 mutex_exit(&hat->hat_mutex);
4021 4032 }
4022 4033
4023 4034 /*
4024 4035 * HAT part of cpu initialization.
4025 4036 */
4026 4037 void
4027 4038 hat_cpu_online(struct cpu *cpup)
4028 4039 {
4029 4040 if (cpup != CPU) {
4030 4041 x86pte_cpu_init(cpup);
4031 4042 hat_vlp_setup(cpup);
4032 4043 }
4033 4044 CPUSET_ATOMIC_ADD(khat_cpuset, cpup->cpu_id);
4034 4045 }
4035 4046
4036 4047 /*
4037 4048 * HAT part of cpu deletion.
4038 4049 * (currently, we only call this after the cpu is safely passivated.)
4039 4050 */
4040 4051 void
4041 4052 hat_cpu_offline(struct cpu *cpup)
4042 4053 {
4043 4054 ASSERT(cpup != CPU);
4044 4055
4045 4056 CPUSET_ATOMIC_DEL(khat_cpuset, cpup->cpu_id);
4046 4057 hat_vlp_teardown(cpup);
4047 4058 x86pte_cpu_fini(cpup);
4048 4059 }
4049 4060
4050 4061 /*
4051 4062 * Function called after all CPUs are brought online.
4052 4063 * Used to remove low address boot mappings.
4053 4064 */
4054 4065 void
4055 4066 clear_boot_mappings(uintptr_t low, uintptr_t high)
4056 4067 {
4057 4068 uintptr_t vaddr = low;
4058 4069 htable_t *ht = NULL;
4059 4070 level_t level;
4060 4071 uint_t entry;
4061 4072 x86pte_t pte;
4062 4073
4063 4074 /*
4064 4075 * On 1st CPU we can unload the prom mappings, basically we blow away
4065 4076 * all virtual mappings under _userlimit.
4066 4077 */
4067 4078 while (vaddr < high) {
4068 4079 pte = htable_walk(kas.a_hat, &ht, &vaddr, high);
4069 4080 if (ht == NULL)
4070 4081 break;
4071 4082
4072 4083 level = ht->ht_level;
4073 4084 entry = htable_va2entry(vaddr, ht);
4074 4085 ASSERT(level <= mmu.max_page_level);
4075 4086 ASSERT(PTE_ISPAGE(pte, level));
4076 4087
4077 4088 /*
4078 4089 * Unload the mapping from the page tables.
4079 4090 */
4080 4091 (void) x86pte_inval(ht, entry, 0, NULL, B_TRUE);
4081 4092 ASSERT(ht->ht_valid_cnt > 0);
4082 4093 HTABLE_DEC(ht->ht_valid_cnt);
4083 4094 PGCNT_DEC(ht->ht_hat, ht->ht_level);
4084 4095
4085 4096 vaddr += LEVEL_SIZE(ht->ht_level);
4086 4097 }
4087 4098 if (ht)
4088 4099 htable_release(ht);
4089 4100 }
4090 4101
4091 4102 /*
4092 4103 * Atomically update a new translation for a single page. If the
4093 4104 * currently installed PTE doesn't match the value we expect to find,
4094 4105 * it's not updated and we return the PTE we found.
4095 4106 *
4096 4107 * If activating nosync or NOWRITE and the page was modified we need to sync
4097 4108 * with the page_t. Also sync with page_t if clearing ref/mod bits.
4098 4109 */
4099 4110 static x86pte_t
4100 4111 hati_update_pte(htable_t *ht, uint_t entry, x86pte_t expected, x86pte_t new)
4101 4112 {
4102 4113 page_t *pp;
4103 4114 uint_t rm = 0;
4104 4115 x86pte_t replaced;
4105 4116
4106 4117 if (PTE_GET(expected, PT_SOFTWARE) < PT_NOSYNC &&
4107 4118 PTE_GET(expected, PT_MOD | PT_REF) &&
4108 4119 (PTE_GET(new, PT_NOSYNC) || !PTE_GET(new, PT_WRITABLE) ||
4109 4120 !PTE_GET(new, PT_MOD | PT_REF))) {
4110 4121
4111 4122 ASSERT(!pfn_is_foreign(PTE2PFN(expected, ht->ht_level)));
4112 4123 pp = page_numtopp_nolock(PTE2PFN(expected, ht->ht_level));
4113 4124 ASSERT(pp != NULL);
4114 4125 if (PTE_GET(expected, PT_MOD))
4115 4126 rm |= P_MOD;
4116 4127 if (PTE_GET(expected, PT_REF))
4117 4128 rm |= P_REF;
4118 4129 PTE_CLR(new, PT_MOD | PT_REF);
4119 4130 }
4120 4131
4121 4132 replaced = x86pte_update(ht, entry, expected, new);
4122 4133 if (replaced != expected)
4123 4134 return (replaced);
4124 4135
4125 4136 if (rm) {
4126 4137 /*
4127 4138 * sync to all constituent pages of a large page
4128 4139 */
4129 4140 pgcnt_t pgcnt = page_get_pagecnt(ht->ht_level);
4130 4141 ASSERT(IS_P2ALIGNED(pp->p_pagenum, pgcnt));
4131 4142 while (pgcnt-- > 0) {
4132 4143 /*
4133 4144 * hat_page_demote() can't decrease
4134 4145 * pszc below this mapping size
4135 4146 * since large mapping existed after we
4136 4147 * took mlist lock.
4137 4148 */
4138 4149 ASSERT(pp->p_szc >= ht->ht_level);
4139 4150 hat_page_setattr(pp, rm);
4140 4151 ++pp;
4141 4152 }
4142 4153 }
4143 4154
4144 4155 return (0);
4145 4156 }
4146 4157
4147 4158 /* ARGSUSED */
4148 4159 void
4149 4160 hat_join_srd(struct hat *hat, vnode_t *evp)
4150 4161 {
4151 4162 }
4152 4163
4153 4164 /* ARGSUSED */
4154 4165 hat_region_cookie_t
4155 4166 hat_join_region(struct hat *hat,
4156 4167 caddr_t r_saddr,
4157 4168 size_t r_size,
4158 4169 void *r_obj,
4159 4170 u_offset_t r_objoff,
4160 4171 uchar_t r_perm,
4161 4172 uchar_t r_pgszc,
4162 4173 hat_rgn_cb_func_t r_cb_function,
4163 4174 uint_t flags)
4164 4175 {
4165 4176 panic("No shared region support on x86");
4166 4177 return (HAT_INVALID_REGION_COOKIE);
4167 4178 }
4168 4179
4169 4180 /* ARGSUSED */
4170 4181 void
4171 4182 hat_leave_region(struct hat *hat, hat_region_cookie_t rcookie, uint_t flags)
4172 4183 {
4173 4184 panic("No shared region support on x86");
4174 4185 }
4175 4186
4176 4187 /* ARGSUSED */
4177 4188 void
4178 4189 hat_dup_region(struct hat *hat, hat_region_cookie_t rcookie)
4179 4190 {
4180 4191 panic("No shared region support on x86");
4181 4192 }
4182 4193
4183 4194
4184 4195 /*
4185 4196 * Kernel Physical Mapping (kpm) facility
4186 4197 *
4187 4198 * Most of the routines needed to support segkpm are almost no-ops on the
4188 4199 * x86 platform. We map in the entire segment when it is created and leave
4189 4200 * it mapped in, so there is no additional work required to set up and tear
4190 4201 * down individual mappings. All of these routines were created to support
4191 4202 * SPARC platforms that have to avoid aliasing in their virtually indexed
4192 4203 * caches.
4193 4204 *
4194 4205 * Most of the routines have sanity checks in them (e.g. verifying that the
4195 4206 * passed-in page is locked). We don't actually care about most of these
4196 4207 * checks on x86, but we leave them in place to identify problems in the
4197 4208 * upper levels.
4198 4209 */
4199 4210
4200 4211 /*
4201 4212 * Map in a locked page and return the vaddr.
4202 4213 */
4203 4214 /*ARGSUSED*/
4204 4215 caddr_t
4205 4216 hat_kpm_mapin(struct page *pp, struct kpme *kpme)
4206 4217 {
4207 4218 caddr_t vaddr;
4208 4219
4209 4220 #ifdef DEBUG
4210 4221 if (kpm_enable == 0) {
4211 4222 cmn_err(CE_WARN, "hat_kpm_mapin: kpm_enable not set\n");
4212 4223 return ((caddr_t)NULL);
4213 4224 }
4214 4225
4215 4226 if (pp == NULL || PAGE_LOCKED(pp) == 0) {
4216 4227 cmn_err(CE_WARN, "hat_kpm_mapin: pp zero or not locked\n");
4217 4228 return ((caddr_t)NULL);
4218 4229 }
4219 4230 #endif
4220 4231
4221 4232 vaddr = hat_kpm_page2va(pp, 1);
4222 4233
4223 4234 return (vaddr);
4224 4235 }
4225 4236
4226 4237 /*
4227 4238 * Mapout a locked page.
4228 4239 */
4229 4240 /*ARGSUSED*/
4230 4241 void
4231 4242 hat_kpm_mapout(struct page *pp, struct kpme *kpme, caddr_t vaddr)
4232 4243 {
4233 4244 #ifdef DEBUG
4234 4245 if (kpm_enable == 0) {
4235 4246 cmn_err(CE_WARN, "hat_kpm_mapout: kpm_enable not set\n");
4236 4247 return;
4237 4248 }
4238 4249
4239 4250 if (IS_KPM_ADDR(vaddr) == 0) {
4240 4251 cmn_err(CE_WARN, "hat_kpm_mapout: no kpm address\n");
4241 4252 return;
4242 4253 }
4243 4254
4244 4255 if (pp == NULL || PAGE_LOCKED(pp) == 0) {
4245 4256 cmn_err(CE_WARN, "hat_kpm_mapout: page zero or not locked\n");
4246 4257 return;
4247 4258 }
4248 4259 #endif
4249 4260 }
4250 4261
4251 4262 /*
4252 4263 * hat_kpm_mapin_pfn is used to obtain a kpm mapping for physical
4253 4264 * memory addresses that are not described by a page_t. It can
4254 4265 * also be used for normal pages that are not locked, but beware
4255 4266 * this is dangerous - no locking is performed, so the identity of
4256 4267 * the page could change. hat_kpm_mapin_pfn is not supported when
4257 4268 * vac_colors > 1, because the chosen va depends on the page identity,
4258 4269 * which could change.
4259 4270 * The caller must only pass pfn's for valid physical addresses; violation
4260 4271 * of this rule will cause panic.
4261 4272 */
4262 4273 caddr_t
4263 4274 hat_kpm_mapin_pfn(pfn_t pfn)
4264 4275 {
4265 4276 caddr_t paddr, vaddr;
4266 4277
4267 4278 if (kpm_enable == 0)
4268 4279 return ((caddr_t)NULL);
4269 4280
4270 4281 paddr = (caddr_t)ptob(pfn);
4271 4282 vaddr = (uintptr_t)kpm_vbase + paddr;
4272 4283
4273 4284 return ((caddr_t)vaddr);
4274 4285 }
4275 4286
4276 4287 /*ARGSUSED*/
4277 4288 void
4278 4289 hat_kpm_mapout_pfn(pfn_t pfn)
4279 4290 {
4280 4291 /* empty */
4281 4292 }
4282 4293
4283 4294 /*
4284 4295 * Return the kpm virtual address for a specific pfn
4285 4296 */
4286 4297 caddr_t
4287 4298 hat_kpm_pfn2va(pfn_t pfn)
4288 4299 {
4289 4300 uintptr_t vaddr = (uintptr_t)kpm_vbase + mmu_ptob(pfn);
4290 4301
4291 4302 ASSERT(!pfn_is_foreign(pfn));
4292 4303 return ((caddr_t)vaddr);
4293 4304 }
4294 4305
4295 4306 /*
4296 4307 * Return the kpm virtual address for the page at pp.
4297 4308 */
4298 4309 /*ARGSUSED*/
4299 4310 caddr_t
4300 4311 hat_kpm_page2va(struct page *pp, int checkswap)
4301 4312 {
4302 4313 return (hat_kpm_pfn2va(pp->p_pagenum));
4303 4314 }
4304 4315
4305 4316 /*
4306 4317 * Return the page frame number for the kpm virtual address vaddr.
4307 4318 */
4308 4319 pfn_t
4309 4320 hat_kpm_va2pfn(caddr_t vaddr)
4310 4321 {
4311 4322 pfn_t pfn;
4312 4323
4313 4324 ASSERT(IS_KPM_ADDR(vaddr));
4314 4325
4315 4326 pfn = (pfn_t)btop(vaddr - kpm_vbase);
4316 4327
4317 4328 return (pfn);
4318 4329 }
4319 4330
4320 4331
4321 4332 /*
4322 4333 * Return the page for the kpm virtual address vaddr.
4323 4334 */
4324 4335 page_t *
4325 4336 hat_kpm_vaddr2page(caddr_t vaddr)
4326 4337 {
4327 4338 pfn_t pfn;
4328 4339
4329 4340 ASSERT(IS_KPM_ADDR(vaddr));
4330 4341
4331 4342 pfn = hat_kpm_va2pfn(vaddr);
4332 4343
4333 4344 return (page_numtopp_nolock(pfn));
4334 4345 }
4335 4346
4336 4347 /*
4337 4348 * hat_kpm_fault is called from segkpm_fault when we take a page fault on a
4338 4349 * KPM page. This should never happen on x86
4339 4350 */
4340 4351 int
4341 4352 hat_kpm_fault(hat_t *hat, caddr_t vaddr)
4342 4353 {
4343 4354 panic("pagefault in seg_kpm. hat: 0x%p vaddr: 0x%p",
4344 4355 (void *)hat, (void *)vaddr);
4345 4356
4346 4357 return (0);
4347 4358 }
4348 4359
4349 4360 /*ARGSUSED*/
4350 4361 void
4351 4362 hat_kpm_mseghash_clear(int nentries)
4352 4363 {}
4353 4364
4354 4365 /*ARGSUSED*/
4355 4366 void
4356 4367 hat_kpm_mseghash_update(pgcnt_t inx, struct memseg *msp)
4357 4368 {}
4358 4369
4359 4370 #ifndef __xpv
4360 4371 void
4361 4372 hat_kpm_addmem_mseg_update(struct memseg *msp, pgcnt_t nkpmpgs,
4362 4373 offset_t kpm_pages_off)
4363 4374 {
4364 4375 _NOTE(ARGUNUSED(nkpmpgs, kpm_pages_off));
4365 4376 pfn_t base, end;
4366 4377
4367 4378 /*
4368 4379 * kphysm_add_memory_dynamic() does not set nkpmpgs
4369 4380 * when page_t memory is externally allocated. That
4370 4381 * code must properly calculate nkpmpgs in all cases
4371 4382 * if nkpmpgs needs to be used at some point.
4372 4383 */
4373 4384
4374 4385 /*
4375 4386 * The meta (page_t) pages for dynamically added memory are allocated
4376 4387 * either from the incoming memory itself or from existing memory.
4377 4388 * In the former case the base of the incoming pages will be different
4378 4389 * than the base of the dynamic segment so call memseg_get_start() to
4379 4390 * get the actual base of the incoming memory for each case.
4380 4391 */
4381 4392
4382 4393 base = memseg_get_start(msp);
4383 4394 end = msp->pages_end;
4384 4395
4385 4396 hat_devload(kas.a_hat, kpm_vbase + mmu_ptob(base),
4386 4397 mmu_ptob(end - base), base, PROT_READ | PROT_WRITE,
4387 4398 HAT_LOAD | HAT_LOAD_LOCK | HAT_LOAD_NOCONSIST);
4388 4399 }
4389 4400
4390 4401 void
4391 4402 hat_kpm_addmem_mseg_insert(struct memseg *msp)
4392 4403 {
4393 4404 _NOTE(ARGUNUSED(msp));
4394 4405 }
4395 4406
4396 4407 void
4397 4408 hat_kpm_addmem_memsegs_update(struct memseg *msp)
4398 4409 {
4399 4410 _NOTE(ARGUNUSED(msp));
4400 4411 }
4401 4412
4402 4413 /*
4403 4414 * Return end of metadata for an already setup memseg.
4404 4415 * X86 platforms don't need per-page meta data to support kpm.
4405 4416 */
4406 4417 caddr_t
4407 4418 hat_kpm_mseg_reuse(struct memseg *msp)
4408 4419 {
4409 4420 return ((caddr_t)msp->epages);
4410 4421 }
4411 4422
4412 4423 void
4413 4424 hat_kpm_delmem_mseg_update(struct memseg *msp, struct memseg **mspp)
4414 4425 {
4415 4426 _NOTE(ARGUNUSED(msp, mspp));
4416 4427 ASSERT(0);
4417 4428 }
4418 4429
4419 4430 void
4420 4431 hat_kpm_split_mseg_update(struct memseg *msp, struct memseg **mspp,
4421 4432 struct memseg *lo, struct memseg *mid, struct memseg *hi)
4422 4433 {
4423 4434 _NOTE(ARGUNUSED(msp, mspp, lo, mid, hi));
4424 4435 ASSERT(0);
4425 4436 }
4426 4437
4427 4438 /*
4428 4439 * Walk the memsegs chain, applying func to each memseg span.
4429 4440 */
4430 4441 void
4431 4442 hat_kpm_walk(void (*func)(void *, void *, size_t), void *arg)
4432 4443 {
4433 4444 pfn_t pbase, pend;
4434 4445 void *base;
4435 4446 size_t size;
4436 4447 struct memseg *msp;
4437 4448
4438 4449 for (msp = memsegs; msp; msp = msp->next) {
4439 4450 pbase = msp->pages_base;
4440 4451 pend = msp->pages_end;
4441 4452 base = ptob(pbase) + kpm_vbase;
4442 4453 size = ptob(pend - pbase);
4443 4454 func(arg, base, size);
4444 4455 }
4445 4456 }
4446 4457
4447 4458 #else /* __xpv */
4448 4459
4449 4460 /*
4450 4461 * There are specific Hypervisor calls to establish and remove mappings
4451 4462 * to grant table references and the privcmd driver. We have to ensure
4452 4463 * that a page table actually exists.
4453 4464 */
4454 4465 void
4455 4466 hat_prepare_mapping(hat_t *hat, caddr_t addr, uint64_t *pte_ma)
4456 4467 {
4457 4468 maddr_t base_ma;
4458 4469 htable_t *ht;
4459 4470 uint_t entry;
4460 4471
4461 4472 ASSERT(IS_P2ALIGNED((uintptr_t)addr, MMU_PAGESIZE));
4462 4473 XPV_DISALLOW_MIGRATE();
4463 4474 ht = htable_create(hat, (uintptr_t)addr, 0, NULL);
4464 4475
4465 4476 /*
4466 4477 * if an address for pte_ma is passed in, return the MA of the pte
4467 4478 * for this specific address. This address is only valid as long
4468 4479 * as the htable stays locked.
4469 4480 */
4470 4481 if (pte_ma != NULL) {
4471 4482 entry = htable_va2entry((uintptr_t)addr, ht);
4472 4483 base_ma = pa_to_ma(ptob(ht->ht_pfn));
4473 4484 *pte_ma = base_ma + (entry << mmu.pte_size_shift);
4474 4485 }
4475 4486 XPV_ALLOW_MIGRATE();
4476 4487 }
4477 4488
4478 4489 void
4479 4490 hat_release_mapping(hat_t *hat, caddr_t addr)
4480 4491 {
4481 4492 htable_t *ht;
4482 4493
4483 4494 ASSERT(IS_P2ALIGNED((uintptr_t)addr, MMU_PAGESIZE));
4484 4495 XPV_DISALLOW_MIGRATE();
4485 4496 ht = htable_lookup(hat, (uintptr_t)addr, 0);
4486 4497 ASSERT(ht != NULL);
4487 4498 ASSERT(ht->ht_busy >= 2);
4488 4499 htable_release(ht);
4489 4500 htable_release(ht);
4490 4501 XPV_ALLOW_MIGRATE();
4491 4502 }
4492 4503 #endif /* __xpv */
↓ open down ↓ |
2126 lines elided |
↑ open up ↑ |
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX