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--- old/usr/src/uts/sun4v/ml/hcall.s
+++ new/usr/src/uts/sun4v/ml/hcall.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 */
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25 25
26 26 /*
27 27 * Hypervisor calls
28 28 */
29 29
30 30 #include <sys/asm_linkage.h>
31 31 #include <sys/machasi.h>
32 32 #include <sys/machparam.h>
33 33 #include <sys/hypervisor_api.h>
34 34
35 -#if defined(lint) || defined(__lint)
36 -
37 -/*ARGSUSED*/
38 -uint64_t
39 -hv_mach_exit(uint64_t exit_code)
40 -{ return (0); }
41 -
42 -uint64_t
43 -hv_mach_sir(void)
44 -{ return (0); }
45 -
46 -/*ARGSUSED*/
47 -uint64_t
48 -hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg)
49 -{ return (0); }
50 -
51 -/*ARGSUSED*/
52 -uint64_t
53 -hv_cpu_stop(uint64_t cpuid)
54 -{ return (0); }
55 -
56 -/*ARGSUSED*/
57 -uint64_t
58 -hv_cpu_set_rtba(uint64_t *rtba)
59 -{ return (0); }
60 -
61 -/*ARGSUSED*/
62 -int64_t
63 -hv_cnputchar(uint8_t ch)
64 -{ return (0); }
65 -
66 -/*ARGSUSED*/
67 -int64_t
68 -hv_cngetchar(uint8_t *ch)
69 -{ return (0); }
70 -
71 -/*ARGSUSED*/
72 -uint64_t
73 -hv_tod_get(uint64_t *seconds)
74 -{ return (0); }
75 -
76 -/*ARGSUSED*/
77 -uint64_t
78 -hv_tod_set(uint64_t seconds)
79 -{ return (0);}
80 -
81 -/*ARGSUSED*/
82 -uint64_t
83 -hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags)
84 -{ return (0); }
85 -
86 -/*ARGSUSED */
87 -uint64_t
88 -hv_mmu_fault_area_conf(void *raddr)
89 -{ return (0); }
90 -
91 -/*ARGSUSED*/
92 -uint64_t
93 -hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags)
94 -{ return (0); }
95 -
96 -/*ARGSUSED*/
97 -uint64_t
98 -hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra)
99 -{ return (0); }
100 -
101 -/*ARGSUSED*/
102 -uint64_t
103 -hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra)
104 -{ return (0); }
105 -
106 -#ifdef SET_MMU_STATS
107 -/*ARGSUSED*/
108 -uint64_t
109 -hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size)
110 -{ return (0); }
111 -#endif /* SET_MMU_STATS */
112 -
113 -/*ARGSUSED*/
114 -uint64_t
115 -hv_cpu_qconf(int queue, uint64_t paddr, int size)
116 -{ return (0); }
117 -
118 -/*ARGSUSED*/
119 -uint64_t
120 -hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino)
121 -{ return (0); }
122 -
123 -/*ARGSUSED*/
124 -uint64_t
125 -hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state)
126 -{ return (0); }
127 -
128 -/*ARGSUSED*/
129 -uint64_t
130 -hvio_intr_setvalid(uint64_t sysino, int intr_valid_state)
131 -{ return (0); }
132 -
133 -/*ARGSUSED*/
134 -uint64_t
135 -hvio_intr_getstate(uint64_t sysino, int *intr_state)
136 -{ return (0); }
137 -
138 -/*ARGSUSED*/
139 -uint64_t
140 -hvio_intr_setstate(uint64_t sysino, int intr_state)
141 -{ return (0); }
142 -
143 -/*ARGSUSED*/
144 -uint64_t
145 -hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid)
146 -{ return (0); }
147 -
148 -/*ARGSUSED*/
149 -uint64_t
150 -hvio_intr_settarget(uint64_t sysino, uint32_t cpuid)
151 -{ return (0); }
152 -
153 -uint64_t
154 -hv_cpu_yield(void)
155 -{ return (0); }
156 -
157 -/*ARGSUSED*/
158 -uint64_t
159 -hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state)
160 -{ return (0); }
161 -
162 -/*ARGSUSED*/
163 -uint64_t
164 -hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize)
165 -{ return (0); }
166 -
167 -/*ARGSUSED*/
168 -uint64_t
169 -hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len)
170 -{ return (0); }
171 -
172 -/*ARGSUSED*/
173 -uint64_t
174 -hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len)
175 -{ return (0); }
176 -
177 -/*ARGSUSED*/
178 -uint64_t
179 -hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1)
180 -{ return (0); }
181 -
182 -/*ARGSUSED*/
183 -uint64_t
184 -hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size)
185 -{ return (0); }
186 -
187 -/*ARGSUSED*/
188 -uint64_t
189 -hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable)
190 -{ return (0); }
191 -
192 -/*ARGSUSED*/
193 -uint64_t
194 -hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze)
195 -{ return (0); }
196 -
197 -/*ARGSUSED*/
198 -uint64_t
199 -hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep)
200 -{ return (0); }
201 -
202 -/*ARGSUSED*/
203 -uint64_t
204 -hv_ra2pa(uint64_t ra)
205 -{ return (0); }
206 -
207 -/*ARGSUSED*/
208 -uint64_t
209 -hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3)
210 -{ return (0); }
211 -
212 -/*ARGSUSED*/
213 -uint64_t
214 -hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries)
215 -{ return (0); }
216 -
217 -/*ARGSUSED*/
218 -uint64_t
219 -hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries)
220 -{ return (0); }
221 -
222 -/*ARGSUSED*/
223 -uint64_t
224 -hv_ldc_tx_get_state(uint64_t channel,
225 - uint64_t *headp, uint64_t *tailp, uint64_t *state)
226 -{ return (0); }
227 -
228 -/*ARGSUSED*/
229 -uint64_t
230 -hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail)
231 -{ return (0); }
232 -
233 -/*ARGSUSED*/
234 -uint64_t
235 -hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries)
236 -{ return (0); }
237 -
238 -/*ARGSUSED*/
239 -uint64_t
240 -hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries)
241 -{ return (0); }
242 -
243 -/*ARGSUSED*/
244 -uint64_t
245 -hv_ldc_rx_get_state(uint64_t channel,
246 - uint64_t *headp, uint64_t *tailp, uint64_t *state)
247 -{ return (0); }
248 -
249 -/*ARGSUSED*/
250 -uint64_t
251 -hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head)
252 -{ return (0); }
253 -
254 -/*ARGSUSED*/
255 -uint64_t
256 -hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra)
257 -{ return (0); }
258 -
259 -/*ARGSUSED*/
260 -uint64_t
261 -hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries)
262 -{ return (0); }
263 -
264 -/*ARGSUSED*/
265 -uint64_t
266 -hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie,
267 - uint64_t raddr, uint64_t length, uint64_t *lengthp)
268 -{ return (0); }
269 -
270 -/*ARGSUSED*/
271 -uint64_t
272 -hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie)
273 -{ return (0); }
274 -
275 -/*ARGSUSED*/
276 -uint64_t
277 -hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie)
278 -{ return (0); }
279 -
280 -/*ARGSUSED*/
281 -uint64_t
282 -hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state)
283 -{ return (0); }
284 -
285 -/*ARGSUSED*/
286 -uint64_t
287 -hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state)
288 -{ return (0); }
289 -
290 -/*ARGSUSED*/
291 -uint64_t
292 -hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state)
293 -{ return (0); }
294 -
295 -/*ARGSUSED*/
296 -uint64_t
297 -hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state)
298 -{ return (0); }
299 -
300 -/*ARGSUSED*/
301 -uint64_t
302 -hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid)
303 -{ return (0); }
304 -
305 -/*ARGSUSED*/
306 -uint64_t
307 -hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid)
308 -{ return (0); }
309 -
310 -/*ARGSUSED*/
311 -uint64_t
312 -hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp)
313 -{ return (0); }
314 -
315 -/*ARGSUSED*/
316 -uint64_t
317 -hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor,
318 - uint64_t *supported_minor)
319 -{ return (0); }
320 -
321 -/*ARGSUSED*/
322 -uint64_t
323 -hv_tm_enable(uint64_t enable)
324 -{ return (0); }
325 -
326 -/*ARGSUSED*/
327 -uint64_t
328 -hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining)
329 -{ return (0); }
330 -
331 -/*ARGSUSED*/
332 -int64_t
333 -hv_cnwrite(uint64_t buf_ra, uint64_t count, uint64_t *retcount)
334 -{ return (0); }
335 -
336 -/*ARGSUSED*/
337 -int64_t
338 -hv_cnread(uint64_t buf_ra, uint64_t count, int64_t *retcount)
339 -{ return (0); }
340 -
341 -/*ARGSUSED*/
342 -uint64_t
343 -hv_soft_state_set(uint64_t state, uint64_t string)
344 -{ return (0); }
345 -
346 -/*ARGSUSED*/
347 -uint64_t
348 -hv_soft_state_get(uint64_t string, uint64_t *state)
349 -{ return (0); }uint64_t
350 -hv_guest_suspend(void)
351 -{ return (0); }
352 -
353 -/*ARGSUSED*/
354 -uint64_t
355 -hv_tick_set_npt(uint64_t npt)
356 -{ return (0); }
357 -
358 -/*ARGSUSED*/
359 -uint64_t
360 -hv_stick_set_npt(uint64_t npt)
361 -{ return (0); }
362 -
363 -/*ARGSUSED*/
364 -uint64_t
365 -hv_reboot_data_set(uint64_t buffer_ra, uint64_t buffer_len)
366 -{ return (0); }
367 -
368 -#else /* lint || __lint */
369 -
370 35 /*
371 36 * int hv_mach_exit(uint64_t exit_code)
372 37 */
373 38 ENTRY(hv_mach_exit)
374 39 mov HV_MACH_EXIT, %o5
375 40 ta FAST_TRAP
376 41 retl
377 42 nop
378 43 SET_SIZE(hv_mach_exit)
379 44
380 45 /*
381 46 * uint64_t hv_mach_sir(void)
382 47 */
383 48 ENTRY(hv_mach_sir)
384 49 mov HV_MACH_SIR, %o5
385 50 ta FAST_TRAP
386 51 retl
387 52 nop
388 53 SET_SIZE(hv_mach_sir)
389 54
390 55 /*
391 56 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba,
392 57 * uint64_t arg)
393 58 */
394 59 ENTRY(hv_cpu_start)
395 60 mov HV_CPU_START, %o5
396 61 ta FAST_TRAP
397 62 retl
398 63 nop
399 64 SET_SIZE(hv_cpu_start)
400 65
401 66 /*
402 67 * hv_cpu_stop(uint64_t cpuid)
403 68 */
404 69 ENTRY(hv_cpu_stop)
405 70 mov HV_CPU_STOP, %o5
406 71 ta FAST_TRAP
407 72 retl
408 73 nop
409 74 SET_SIZE(hv_cpu_stop)
410 75
411 76 /*
412 77 * hv_cpu_set_rtba(uint64_t *rtba)
413 78 */
414 79 ENTRY(hv_cpu_set_rtba)
415 80 mov %o0, %o2
416 81 ldx [%o2], %o0
417 82 mov HV_CPU_SET_RTBA, %o5
418 83 ta FAST_TRAP
419 84 stx %o1, [%o2]
420 85 retl
421 86 nop
422 87 SET_SIZE(hv_cpu_set_rtba)
423 88
424 89 /*
425 90 * int64_t hv_cnputchar(uint8_t ch)
426 91 */
427 92 ENTRY(hv_cnputchar)
428 93 mov CONS_PUTCHAR, %o5
429 94 ta FAST_TRAP
430 95 retl
431 96 nop
432 97 SET_SIZE(hv_cnputchar)
433 98
434 99 /*
435 100 * int64_t hv_cngetchar(uint8_t *ch)
436 101 */
437 102 ENTRY(hv_cngetchar)
438 103 mov %o0, %o2
439 104 mov CONS_GETCHAR, %o5
440 105 ta FAST_TRAP
441 106 brnz,a %o0, 1f ! failure, just return error
442 107 nop
443 108
444 109 cmp %o1, H_BREAK
445 110 be 1f
446 111 mov %o1, %o0
447 112
448 113 cmp %o1, H_HUP
449 114 be 1f
450 115 mov %o1, %o0
451 116
452 117 stb %o1, [%o2] ! success, save character and return 0
453 118 mov 0, %o0
454 119 1:
455 120 retl
456 121 nop
457 122 SET_SIZE(hv_cngetchar)
458 123
459 124 ENTRY(hv_tod_get)
460 125 mov %o0, %o4
461 126 mov TOD_GET, %o5
462 127 ta FAST_TRAP
463 128 retl
464 129 stx %o1, [%o4]
465 130 SET_SIZE(hv_tod_get)
466 131
467 132 ENTRY(hv_tod_set)
468 133 mov TOD_SET, %o5
469 134 ta FAST_TRAP
470 135 retl
471 136 nop
472 137 SET_SIZE(hv_tod_set)
473 138
474 139 /*
475 140 * Map permanent address
476 141 * arg0 vaddr (%o0)
477 142 * arg1 context (%o1)
478 143 * arg2 tte (%o2)
479 144 * arg3 flags (%o3) 0x1=d 0x2=i
480 145 */
481 146 ENTRY(hv_mmu_map_perm_addr)
482 147 mov MAP_PERM_ADDR, %o5
483 148 ta FAST_TRAP
484 149 retl
485 150 nop
486 151 SET_SIZE(hv_mmu_map_perm_addr)
487 152
488 153 /*
489 154 * hv_mmu_fault_area_conf(void *raddr)
490 155 */
491 156 ENTRY(hv_mmu_fault_area_conf)
492 157 mov %o0, %o2
493 158 ldx [%o2], %o0
494 159 mov MMU_SET_INFOPTR, %o5
495 160 ta FAST_TRAP
496 161 stx %o1, [%o2]
497 162 retl
498 163 nop
499 164 SET_SIZE(hv_mmu_fault_area_conf)
500 165
501 166 /*
502 167 * Unmap permanent address
503 168 * arg0 vaddr (%o0)
504 169 * arg1 context (%o1)
505 170 * arg2 flags (%o2) 0x1=d 0x2=i
506 171 */
507 172 ENTRY(hv_mmu_unmap_perm_addr)
508 173 mov UNMAP_PERM_ADDR, %o5
509 174 ta FAST_TRAP
510 175 retl
511 176 nop
512 177 SET_SIZE(hv_mmu_unmap_perm_addr)
513 178
514 179 /*
515 180 * Set TSB for context 0
516 181 * arg0 ntsb_descriptor (%o0)
517 182 * arg1 desc_ra (%o1)
518 183 */
519 184 ENTRY(hv_set_ctx0)
520 185 mov MMU_TSB_CTX0, %o5
521 186 ta FAST_TRAP
522 187 retl
523 188 nop
524 189 SET_SIZE(hv_set_ctx0)
525 190
526 191 /*
527 192 * Set TSB for context non0
528 193 * arg0 ntsb_descriptor (%o0)
529 194 * arg1 desc_ra (%o1)
530 195 */
531 196 ENTRY(hv_set_ctxnon0)
532 197 mov MMU_TSB_CTXNON0, %o5
533 198 ta FAST_TRAP
534 199 retl
535 200 nop
536 201 SET_SIZE(hv_set_ctxnon0)
537 202
538 203 #ifdef SET_MMU_STATS
539 204 /*
540 205 * Returns old stat area on success
541 206 */
542 207 ENTRY(hv_mmu_set_stat_area)
543 208 mov MMU_STAT_AREA, %o5
544 209 ta FAST_TRAP
545 210 retl
546 211 nop
547 212 SET_SIZE(hv_mmu_set_stat_area)
548 213 #endif /* SET_MMU_STATS */
549 214
550 215 /*
551 216 * CPU Q Configure
552 217 * arg0 queue (%o0)
553 218 * arg1 Base address RA (%o1)
554 219 * arg2 Size (%o2)
555 220 */
556 221 ENTRY(hv_cpu_qconf)
557 222 mov HV_CPU_QCONF, %o5
558 223 ta FAST_TRAP
559 224 retl
560 225 nop
561 226 SET_SIZE(hv_cpu_qconf)
562 227
563 228 /*
564 229 * arg0 - devhandle
565 230 * arg1 - devino
566 231 *
567 232 * ret0 - status
568 233 * ret1 - sysino
569 234 */
570 235 ENTRY(hvio_intr_devino_to_sysino)
571 236 mov HVIO_INTR_DEVINO2SYSINO, %o5
572 237 ta FAST_TRAP
573 238 brz,a %o0, 1f
574 239 stx %o1, [%o2]
575 240 1: retl
576 241 nop
577 242 SET_SIZE(hvio_intr_devino_to_sysino)
578 243
579 244 /*
580 245 * arg0 - sysino
581 246 *
582 247 * ret0 - status
583 248 * ret1 - intr_valid_state
584 249 */
585 250 ENTRY(hvio_intr_getvalid)
586 251 mov %o1, %o2
587 252 mov HVIO_INTR_GETVALID, %o5
588 253 ta FAST_TRAP
589 254 brz,a %o0, 1f
590 255 stuw %o1, [%o2]
591 256 1: retl
592 257 nop
593 258 SET_SIZE(hvio_intr_getvalid)
594 259
595 260 /*
596 261 * arg0 - sysino
597 262 * arg1 - intr_valid_state
598 263 *
599 264 * ret0 - status
600 265 */
601 266 ENTRY(hvio_intr_setvalid)
602 267 mov HVIO_INTR_SETVALID, %o5
603 268 ta FAST_TRAP
604 269 retl
605 270 nop
606 271 SET_SIZE(hvio_intr_setvalid)
607 272
608 273 /*
609 274 * arg0 - sysino
610 275 *
611 276 * ret0 - status
612 277 * ret1 - intr_state
613 278 */
614 279 ENTRY(hvio_intr_getstate)
615 280 mov %o1, %o2
616 281 mov HVIO_INTR_GETSTATE, %o5
617 282 ta FAST_TRAP
618 283 brz,a %o0, 1f
619 284 stuw %o1, [%o2]
620 285 1: retl
621 286 nop
622 287 SET_SIZE(hvio_intr_getstate)
623 288
624 289 /*
625 290 * arg0 - sysino
626 291 * arg1 - intr_state
627 292 *
628 293 * ret0 - status
629 294 */
630 295 ENTRY(hvio_intr_setstate)
631 296 mov HVIO_INTR_SETSTATE, %o5
632 297 ta FAST_TRAP
633 298 retl
634 299 nop
635 300 SET_SIZE(hvio_intr_setstate)
636 301
637 302 /*
638 303 * arg0 - sysino
639 304 *
640 305 * ret0 - status
641 306 * ret1 - cpu_id
642 307 */
643 308 ENTRY(hvio_intr_gettarget)
644 309 mov %o1, %o2
645 310 mov HVIO_INTR_GETTARGET, %o5
646 311 ta FAST_TRAP
647 312 brz,a %o0, 1f
648 313 stuw %o1, [%o2]
649 314 1: retl
650 315 nop
651 316 SET_SIZE(hvio_intr_gettarget)
652 317
653 318 /*
654 319 * arg0 - sysino
655 320 * arg1 - cpu_id
656 321 *
657 322 * ret0 - status
658 323 */
659 324 ENTRY(hvio_intr_settarget)
660 325 mov HVIO_INTR_SETTARGET, %o5
661 326 ta FAST_TRAP
662 327 retl
663 328 nop
664 329 SET_SIZE(hvio_intr_settarget)
665 330
666 331 /*
667 332 * hv_cpu_yield(void)
668 333 */
669 334 ENTRY(hv_cpu_yield)
670 335 mov HV_CPU_YIELD, %o5
671 336 ta FAST_TRAP
672 337 retl
673 338 nop
674 339 SET_SIZE(hv_cpu_yield)
675 340
676 341 /*
677 342 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state);
678 343 */
679 344 ENTRY(hv_cpu_state)
680 345 mov %o1, %o4 ! save datap
681 346 mov HV_CPU_STATE, %o5
682 347 ta FAST_TRAP
683 348 brz,a %o0, 1f
684 349 stx %o1, [%o4]
685 350 1:
686 351 retl
687 352 nop
688 353 SET_SIZE(hv_cpu_state)
689 354
690 355 /*
691 356 * HV state dump zone Configure
692 357 * arg0 real adrs of dump buffer (%o0)
693 358 * arg1 size of dump buffer (%o1)
694 359 * ret0 status (%o0)
695 360 * ret1 size of buffer on success and min size on EINVAL (%o1)
696 361 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size)
697 362 */
698 363 ENTRY(hv_dump_buf_update)
699 364 mov DUMP_BUF_UPDATE, %o5
700 365 ta FAST_TRAP
701 366 retl
702 367 stx %o1, [%o2]
703 368 SET_SIZE(hv_dump_buf_update)
704 369
705 370 /*
706 371 * arg0 - timeout value (%o0)
707 372 *
708 373 * ret0 - status (%o0)
709 374 * ret1 - time_remaining (%o1)
710 375 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining)
711 376 */
712 377 ENTRY(hv_mach_set_watchdog)
713 378 mov %o1, %o2
714 379 mov MACH_SET_WATCHDOG, %o5
715 380 ta FAST_TRAP
716 381 retl
717 382 stx %o1, [%o2]
718 383 SET_SIZE(hv_mach_set_watchdog)
719 384
720 385 /*
721 386 * For memory scrub
722 387 * int hv_mem_scrub(uint64_t real_addr, uint64_t length,
723 388 * uint64_t *scrubbed_len);
724 389 * Retun %o0 -- status
725 390 * %o1 -- bytes scrubbed
726 391 */
727 392 ENTRY(hv_mem_scrub)
728 393 mov %o2, %o4
729 394 mov HV_MEM_SCRUB, %o5
730 395 ta FAST_TRAP
731 396 retl
732 397 stx %o1, [%o4]
733 398 SET_SIZE(hv_mem_scrub)
734 399
735 400 /*
736 401 * Flush ecache
737 402 * int hv_mem_sync(uint64_t real_addr, uint64_t length,
738 403 * uint64_t *flushed_len);
739 404 * Retun %o0 -- status
740 405 * %o1 -- bytes flushed
741 406 */
742 407 ENTRY(hv_mem_sync)
743 408 mov %o2, %o4
744 409 mov HV_MEM_SYNC, %o5
745 410 ta FAST_TRAP
746 411 retl
747 412 stx %o1, [%o4]
748 413 SET_SIZE(hv_mem_sync)
749 414
750 415 /*
751 416 * uint64_t hv_tm_enable(uint64_t enable)
752 417 */
753 418 ENTRY(hv_tm_enable)
754 419 mov HV_TM_ENABLE, %o5
755 420 ta FAST_TRAP
756 421 retl
757 422 nop
758 423 SET_SIZE(hv_tm_enable)
759 424
760 425 /*
761 426 * TTRACE_BUF_CONF Configure
762 427 * arg0 RA base of buffer (%o0)
763 428 * arg1 buf size in no. of entries (%o1)
764 429 * ret0 status (%o0)
765 430 * ret1 minimum size in no. of entries on failure,
766 431 * actual size in no. of entries on success (%o1)
767 432 */
768 433 ENTRY(hv_ttrace_buf_conf)
769 434 mov TTRACE_BUF_CONF, %o5
770 435 ta FAST_TRAP
771 436 retl
772 437 stx %o1, [%o2]
773 438 SET_SIZE(hv_ttrace_buf_conf)
774 439
775 440 /*
776 441 * TTRACE_BUF_INFO
777 442 * ret0 status (%o0)
778 443 * ret1 RA base of buffer (%o1)
779 444 * ret2 size in no. of entries (%o2)
780 445 */
781 446 ENTRY(hv_ttrace_buf_info)
782 447 mov %o0, %o3
783 448 mov %o1, %o4
784 449 mov TTRACE_BUF_INFO, %o5
785 450 ta FAST_TRAP
786 451 stx %o1, [%o3]
787 452 retl
788 453 stx %o2, [%o4]
789 454 SET_SIZE(hv_ttrace_buf_info)
790 455
791 456 /*
792 457 * TTRACE_ENABLE
793 458 * arg0 enable/ disable (%o0)
794 459 * ret0 status (%o0)
795 460 * ret1 previous enable state (%o1)
796 461 */
797 462 ENTRY(hv_ttrace_enable)
798 463 mov %o1, %o2
799 464 mov TTRACE_ENABLE, %o5
800 465 ta FAST_TRAP
801 466 retl
802 467 stx %o1, [%o2]
803 468 SET_SIZE(hv_ttrace_enable)
804 469
805 470 /*
806 471 * TTRACE_FREEZE
807 472 * arg0 enable/ freeze (%o0)
808 473 * ret0 status (%o0)
809 474 * ret1 previous freeze state (%o1)
810 475 */
811 476 ENTRY(hv_ttrace_freeze)
812 477 mov %o1, %o2
813 478 mov TTRACE_FREEZE, %o5
814 479 ta FAST_TRAP
815 480 retl
816 481 stx %o1, [%o2]
817 482 SET_SIZE(hv_ttrace_freeze)
818 483
819 484 /*
820 485 * MACH_DESC
821 486 * arg0 buffer real address
822 487 * arg1 pointer to uint64_t for size of buffer
823 488 * ret0 status
824 489 * ret1 return required size of buffer / returned data size
825 490 */
826 491 ENTRY(hv_mach_desc)
827 492 mov %o1, %o4 ! save datap
828 493 ldx [%o1], %o1
829 494 mov HV_MACH_DESC, %o5
830 495 ta FAST_TRAP
831 496 retl
832 497 stx %o1, [%o4]
833 498 SET_SIZE(hv_mach_desc)
834 499
835 500 /*
836 501 * hv_ra2pa(uint64_t ra)
837 502 *
838 503 * MACH_DESC
839 504 * arg0 Real address to convert
840 505 * ret0 Returned physical address or -1 on error
841 506 */
842 507 ENTRY(hv_ra2pa)
843 508 mov HV_RA2PA, %o5
844 509 ta FAST_TRAP
845 510 cmp %o0, 0
846 511 move %xcc, %o1, %o0
847 512 movne %xcc, -1, %o0
848 513 retl
849 514 nop
850 515 SET_SIZE(hv_ra2pa)
851 516
852 517 /*
853 518 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3)
854 519 *
855 520 * MACH_DESC
856 521 * arg0 OS function to call
857 522 * arg1 First arg to OS function
858 523 * arg2 Second arg to OS function
859 524 * arg3 Third arg to OS function
860 525 * ret0 Returned value from function
861 526 */
862 527
863 528 ENTRY(hv_hpriv)
864 529 mov HV_HPRIV, %o5
865 530 ta FAST_TRAP
866 531 retl
867 532 nop
868 533 SET_SIZE(hv_hpriv)
869 534
870 535 /*
871 536 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base,
872 537 * uint64_t nentries);
873 538 */
874 539 ENTRY(hv_ldc_tx_qconf)
875 540 mov LDC_TX_QCONF, %o5
876 541 ta FAST_TRAP
877 542 retl
878 543 nop
879 544 SET_SIZE(hv_ldc_tx_qconf)
880 545
881 546
882 547 /*
883 548 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base,
884 549 * uint64_t *nentries);
885 550 */
886 551 ENTRY(hv_ldc_tx_qinfo)
887 552 mov %o1, %g1
888 553 mov %o2, %g2
889 554 mov LDC_TX_QINFO, %o5
890 555 ta FAST_TRAP
891 556 stx %o1, [%g1]
892 557 retl
893 558 stx %o2, [%g2]
894 559 SET_SIZE(hv_ldc_tx_qinfo)
895 560
896 561
897 562 /*
898 563 * hv_ldc_tx_get_state(uint64_t channel,
899 564 * uint64_t *headp, uint64_t *tailp, uint64_t *state);
900 565 */
901 566 ENTRY(hv_ldc_tx_get_state)
902 567 mov LDC_TX_GET_STATE, %o5
903 568 mov %o1, %g1
904 569 mov %o2, %g2
905 570 mov %o3, %g3
906 571 ta FAST_TRAP
907 572 stx %o1, [%g1]
908 573 stx %o2, [%g2]
909 574 retl
910 575 stx %o3, [%g3]
911 576 SET_SIZE(hv_ldc_tx_get_state)
912 577
913 578
914 579 /*
915 580 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail)
916 581 */
917 582 ENTRY(hv_ldc_tx_set_qtail)
918 583 mov LDC_TX_SET_QTAIL, %o5
919 584 ta FAST_TRAP
920 585 retl
921 586 SET_SIZE(hv_ldc_tx_set_qtail)
922 587
923 588
924 589 /*
925 590 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base,
926 591 * uint64_t nentries);
927 592 */
928 593 ENTRY(hv_ldc_rx_qconf)
929 594 mov LDC_RX_QCONF, %o5
930 595 ta FAST_TRAP
931 596 retl
932 597 nop
933 598 SET_SIZE(hv_ldc_rx_qconf)
934 599
935 600
936 601 /*
937 602 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base,
938 603 * uint64_t *nentries);
939 604 */
940 605 ENTRY(hv_ldc_rx_qinfo)
941 606 mov %o1, %g1
942 607 mov %o2, %g2
943 608 mov LDC_RX_QINFO, %o5
944 609 ta FAST_TRAP
945 610 stx %o1, [%g1]
946 611 retl
947 612 stx %o2, [%g2]
948 613 SET_SIZE(hv_ldc_rx_qinfo)
949 614
950 615
951 616 /*
952 617 * hv_ldc_rx_get_state(uint64_t channel,
953 618 * uint64_t *headp, uint64_t *tailp, uint64_t *state);
954 619 */
955 620 ENTRY(hv_ldc_rx_get_state)
956 621 mov LDC_RX_GET_STATE, %o5
957 622 mov %o1, %g1
958 623 mov %o2, %g2
959 624 mov %o3, %g3
960 625 ta FAST_TRAP
961 626 stx %o1, [%g1]
962 627 stx %o2, [%g2]
963 628 retl
964 629 stx %o3, [%g3]
965 630 SET_SIZE(hv_ldc_rx_get_state)
966 631
967 632
968 633 /*
969 634 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head)
970 635 */
971 636 ENTRY(hv_ldc_rx_set_qhead)
972 637 mov LDC_RX_SET_QHEAD, %o5
973 638 ta FAST_TRAP
974 639 retl
975 640 SET_SIZE(hv_ldc_rx_set_qhead)
976 641
977 642 /*
978 643 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra,
979 644 * uint64_t tbl_entries)
980 645 */
981 646 ENTRY(hv_ldc_set_map_table)
982 647 mov LDC_SET_MAP_TABLE, %o5
983 648 ta FAST_TRAP
984 649 retl
985 650 nop
986 651 SET_SIZE(hv_ldc_set_map_table)
987 652
988 653
989 654 /*
990 655 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra,
991 656 * uint64_t *tbl_entries)
992 657 */
993 658 ENTRY(hv_ldc_get_map_table)
994 659 mov %o1, %g1
995 660 mov %o2, %g2
996 661 mov LDC_GET_MAP_TABLE, %o5
997 662 ta FAST_TRAP
998 663 stx %o1, [%g1]
999 664 retl
1000 665 stx %o2, [%g2]
1001 666 SET_SIZE(hv_ldc_get_map_table)
1002 667
1003 668
1004 669 /*
1005 670 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie,
1006 671 * uint64_t raddr, uint64_t length, uint64_t *lengthp);
1007 672 */
1008 673 ENTRY(hv_ldc_copy)
1009 674 mov %o5, %g1
1010 675 mov LDC_COPY, %o5
1011 676 ta FAST_TRAP
1012 677 retl
1013 678 stx %o1, [%g1]
1014 679 SET_SIZE(hv_ldc_copy)
1015 680
1016 681
1017 682 /*
1018 683 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr,
1019 684 * uint64_t *perm)
1020 685 */
1021 686 ENTRY(hv_ldc_mapin)
1022 687 mov %o2, %g1
1023 688 mov %o3, %g2
1024 689 mov LDC_MAPIN, %o5
1025 690 ta FAST_TRAP
1026 691 stx %o1, [%g1]
1027 692 retl
1028 693 stx %o2, [%g2]
1029 694 SET_SIZE(hv_ldc_mapin)
1030 695
1031 696
1032 697 /*
1033 698 * hv_ldc_unmap(uint64_t raddr)
1034 699 */
1035 700 ENTRY(hv_ldc_unmap)
1036 701 mov LDC_UNMAP, %o5
1037 702 ta FAST_TRAP
1038 703 retl
1039 704 nop
1040 705 SET_SIZE(hv_ldc_unmap)
1041 706
1042 707
1043 708 /*
1044 709 * hv_ldc_revoke(uint64_t channel, uint64_t cookie,
1045 710 * uint64_t revoke_cookie
1046 711 */
1047 712 ENTRY(hv_ldc_revoke)
1048 713 mov LDC_REVOKE, %o5
1049 714 ta FAST_TRAP
1050 715 retl
1051 716 nop
1052 717 SET_SIZE(hv_ldc_revoke)
1053 718
1054 719 /*
1055 720 * hv_ldc_mapin_size_max(uint64_t tbl_type, uint64_t *sz)
1056 721 */
1057 722 ENTRY(hv_ldc_mapin_size_max)
1058 723 mov %o1, %g1
1059 724 mov LDC_MAPIN_SIZE_MAX, %o5
1060 725 ta FAST_TRAP
1061 726 retl
1062 727 stx %o1, [%g1]
1063 728 SET_SIZE(hv_ldc_mapin_size_max)
1064 729
1065 730 /*
1066 731 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino,
1067 732 * uint64_t *cookie);
1068 733 */
1069 734 ENTRY(hvldc_intr_getcookie)
1070 735 mov %o2, %g1
1071 736 mov VINTR_GET_COOKIE, %o5
1072 737 ta FAST_TRAP
1073 738 retl
1074 739 stx %o1, [%g1]
1075 740 SET_SIZE(hvldc_intr_getcookie)
1076 741
1077 742 /*
1078 743 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino,
1079 744 * uint64_t cookie);
1080 745 */
1081 746 ENTRY(hvldc_intr_setcookie)
1082 747 mov VINTR_SET_COOKIE, %o5
1083 748 ta FAST_TRAP
1084 749 retl
1085 750 nop
1086 751 SET_SIZE(hvldc_intr_setcookie)
1087 752
1088 753
1089 754 /*
1090 755 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino,
1091 756 * int *intr_valid_state);
1092 757 */
1093 758 ENTRY(hvldc_intr_getvalid)
1094 759 mov %o2, %g1
1095 760 mov VINTR_GET_VALID, %o5
1096 761 ta FAST_TRAP
1097 762 retl
1098 763 stuw %o1, [%g1]
1099 764 SET_SIZE(hvldc_intr_getvalid)
1100 765
1101 766 /*
1102 767 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino,
1103 768 * int intr_valid_state);
1104 769 */
1105 770 ENTRY(hvldc_intr_setvalid)
1106 771 mov VINTR_SET_VALID, %o5
1107 772 ta FAST_TRAP
1108 773 retl
1109 774 nop
1110 775 SET_SIZE(hvldc_intr_setvalid)
1111 776
1112 777 /*
1113 778 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino,
1114 779 * int *intr_state);
1115 780 */
1116 781 ENTRY(hvldc_intr_getstate)
1117 782 mov %o2, %g1
1118 783 mov VINTR_GET_STATE, %o5
1119 784 ta FAST_TRAP
1120 785 retl
1121 786 stuw %o1, [%g1]
1122 787 SET_SIZE(hvldc_intr_getstate)
1123 788
1124 789 /*
1125 790 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino,
1126 791 * int intr_state);
1127 792 */
1128 793 ENTRY(hvldc_intr_setstate)
1129 794 mov VINTR_SET_STATE, %o5
1130 795 ta FAST_TRAP
1131 796 retl
1132 797 nop
1133 798 SET_SIZE(hvldc_intr_setstate)
1134 799
1135 800 /*
1136 801 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino,
1137 802 * uint32_t *cpuid);
1138 803 */
1139 804 ENTRY(hvldc_intr_gettarget)
1140 805 mov %o2, %g1
1141 806 mov VINTR_GET_TARGET, %o5
1142 807 ta FAST_TRAP
1143 808 retl
1144 809 stuw %o1, [%g1]
1145 810 SET_SIZE(hvldc_intr_gettarget)
1146 811
1147 812 /*
1148 813 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino,
1149 814 * uint32_t cpuid);
1150 815 */
1151 816 ENTRY(hvldc_intr_settarget)
1152 817 mov VINTR_SET_TARGET, %o5
1153 818 ta FAST_TRAP
1154 819 retl
1155 820 nop
1156 821 SET_SIZE(hvldc_intr_settarget)
1157 822
1158 823 /*
1159 824 * hv_api_get_version(uint64_t api_group, uint64_t *majorp,
1160 825 * uint64_t *minorp)
1161 826 *
1162 827 * API_GET_VERSION
1163 828 * arg0 API group
1164 829 * ret0 status
1165 830 * ret1 major number
1166 831 * ret2 minor number
1167 832 */
1168 833 ENTRY(hv_api_get_version)
1169 834 mov %o1, %o3
1170 835 mov %o2, %o4
1171 836 mov API_GET_VERSION, %o5
1172 837 ta CORE_TRAP
1173 838 stx %o1, [%o3]
1174 839 retl
1175 840 stx %o2, [%o4]
1176 841 SET_SIZE(hv_api_get_version)
1177 842
1178 843 /*
1179 844 * hv_api_set_version(uint64_t api_group, uint64_t major,
1180 845 * uint64_t minor, uint64_t *supported_minor)
1181 846 *
1182 847 * API_SET_VERSION
1183 848 * arg0 API group
1184 849 * arg1 major number
1185 850 * arg2 requested minor number
1186 851 * ret0 status
1187 852 * ret1 actual minor number
1188 853 */
1189 854 ENTRY(hv_api_set_version)
1190 855 mov %o3, %o4
1191 856 mov API_SET_VERSION, %o5
1192 857 ta CORE_TRAP
1193 858 retl
1194 859 stx %o1, [%o4]
1195 860 SET_SIZE(hv_api_set_version)
1196 861
1197 862 /*
1198 863 * %o0 - buffer real address
1199 864 * %o1 - buffer size
1200 865 * %o2 - &characters written
1201 866 * returns
1202 867 * status
1203 868 */
1204 869 ENTRY(hv_cnwrite)
1205 870 mov CONS_WRITE, %o5
1206 871 ta FAST_TRAP
1207 872 retl
1208 873 stx %o1, [%o2]
1209 874 SET_SIZE(hv_cnwrite)
1210 875
1211 876 /*
1212 877 * %o0 character buffer ra
1213 878 * %o1 buffer size
1214 879 * %o2 pointer to returned size
1215 880 * return values:
1216 881 * 0 success
1217 882 * hv_errno failure
1218 883 */
1219 884 ENTRY(hv_cnread)
1220 885 mov CONS_READ, %o5
1221 886 ta FAST_TRAP
1222 887 brnz,a %o0, 1f ! failure, just return error
1223 888 nop
1224 889
1225 890 cmp %o1, H_BREAK
1226 891 be 1f
1227 892 mov %o1, %o0
1228 893
1229 894 cmp %o1, H_HUP
1230 895 be 1f
1231 896 mov %o1, %o0
1232 897
1233 898 stx %o1, [%o2] ! success, save count and return 0
1234 899 mov 0, %o0
1235 900 1:
1236 901 retl
1237 902 nop
1238 903 SET_SIZE(hv_cnread)
1239 904
1240 905 /*
1241 906 * SOFT_STATE_SET
1242 907 * arg0 state (%o0)
1243 908 * arg1 string (%o1)
1244 909 * ret0 status (%o0)
1245 910 */
1246 911 ENTRY(hv_soft_state_set)
1247 912 mov SOFT_STATE_SET, %o5
1248 913 ta FAST_TRAP
1249 914 retl
1250 915 nop
1251 916 SET_SIZE(hv_soft_state_set)
1252 917
1253 918 /*
1254 919 * SOFT_STATE_GET
1255 920 * arg0 string buffer (%o0)
1256 921 * ret0 status (%o0)
1257 922 * ret1 current state (%o1)
1258 923 */
1259 924 ENTRY(hv_soft_state_get)
1260 925 mov %o1, %o2
1261 926 mov SOFT_STATE_GET, %o5
1262 927 ta FAST_TRAP
1263 928 retl
1264 929 stx %o1, [%o2]
1265 930 SET_SIZE(hv_soft_state_get)
1266 931
1267 932 ENTRY(hv_guest_suspend)
1268 933 mov GUEST_SUSPEND, %o5
1269 934 ta FAST_TRAP
1270 935 retl
1271 936 nop
1272 937 SET_SIZE(hv_guest_suspend)
1273 938
1274 939 ENTRY(hv_tick_set_npt)
1275 940 mov TICK_SET_NPT, %o5
1276 941 ta FAST_TRAP
1277 942 retl
1278 943 nop
1279 944 SET_SIZE(hv_tick_set_npt)
1280 945
1281 946 ENTRY(hv_stick_set_npt)
1282 947 mov STICK_SET_NPT, %o5
1283 948 ta FAST_TRAP
1284 949 retl
1285 950 nop
1286 951 SET_SIZE(hv_stick_set_npt)
1287 952
1288 953 /*
1289 954 * REBOOT_DATA_SET
1290 955 * arg0 buffer real address
|
↓ open down ↓ |
911 lines elided |
↑ open up ↑ |
1291 956 * arg1 buffer length
1292 957 * ret0 status
1293 958 */
1294 959 ENTRY(hv_reboot_data_set)
1295 960 mov HV_REBOOT_DATA_SET, %o5
1296 961 ta FAST_TRAP
1297 962 retl
1298 963 nop
1299 964 SET_SIZE(hv_reboot_data_set)
1300 965
1301 -#endif /* lint || __lint */
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