1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27 /* 28 * Hypervisor calls called by px nexus driver. 29 */ 30 31 #include <sys/asm_linkage.h> 32 #include <sys/hypervisor_api.h> 33 #include <sys/dditypes.h> 34 #include <px_ioapi.h> 35 #include "px_lib4v.h" 36 37 /* 38 * arg0 - devhandle 39 * arg1 - tsbid 40 * arg2 - pages 41 * arg3 - io_attributes 42 * arg4 - io_page_list_p 43 * 44 * ret1 - pages_mapped 45 */ 46 ENTRY(hvio_iommu_map) 47 save %sp, -SA(MINFRAME64), %sp 48 mov %i0, %o0 49 mov %i1, %o1 50 mov %i2, %o2 51 mov %i3, %o3 52 mov %i4, %o4 53 mov HVIO_IOMMU_MAP, %o5 54 ta FAST_TRAP 55 brnz %o0, 1f 56 mov %o0, %i0 57 stuw %o1, [%i5] 58 1: 59 ret 60 restore 61 SET_SIZE(hvio_iommu_map) 62 63 /* 64 * arg0 - devhandle 65 * arg1 - tsbid 66 * arg2 - pages 67 * 68 * ret1 - pages_demapped 69 */ 70 ENTRY(hvio_iommu_demap) 71 mov HVIO_IOMMU_DEMAP, %o5 72 ta FAST_TRAP 73 brz,a %o0, 1f 74 stuw %o1, [%o3] 75 1: retl 76 nop 77 SET_SIZE(hvio_iommu_demap) 78 79 /* 80 * arg0 - devhandle 81 * arg1 - tsbid 82 * 83 * 84 * ret0 - status 85 * ret1 - io_attributes 86 * ret2 - r_addr 87 */ 88 ENTRY(hvio_iommu_getmap) 89 mov %o2, %o4 90 mov HVIO_IOMMU_GETMAP, %o5 91 ta FAST_TRAP 92 brnz %o0, 1f 93 nop 94 stx %o2, [%o3] 95 st %o1, [%o4] 96 1: 97 retl 98 nop 99 SET_SIZE(hvio_iommu_getmap) 100 101 /* 102 * arg0 - devhandle 103 * arg1 - r_addr 104 * arg2 - io_attributes 105 * 106 * 107 * ret0 - status 108 * ret1 - io_addr 109 */ 110 ENTRY(hvio_iommu_getbypass) 111 mov HVIO_IOMMU_GETBYPASS, %o5 112 ta FAST_TRAP 113 brz,a %o0, 1f 114 stx %o1, [%o3] 115 1: retl 116 nop 117 SET_SIZE(hvio_iommu_getbypass) 118 119 /* 120 * arg0 - devhandle 121 * arg1 - r_addr 122 * arg2 - size 123 * 124 * ret1 - error_flag 125 * ret2 - data 126 */ 127 ENTRY(hvio_peek) 128 mov HVIO_PEEK, %o5 129 ta FAST_TRAP 130 brnz %o0, 1f 131 nop 132 stx %o2, [%o4] 133 st %o1, [%o3] 134 1: 135 retl 136 nop 137 SET_SIZE(hvio_peek) 138 139 /* 140 * arg0 - devhandle 141 * arg1 - r_addr 142 * arg2 - sizes 143 * arg3 - data 144 * arg4 - r_addr2 145 * 146 * ret1 - error_flag 147 */ 148 ENTRY(hvio_poke) 149 save %sp, -SA(MINFRAME64), %sp 150 mov %i0, %o0 151 mov %i1, %o1 152 mov %i2, %o2 153 mov %i3, %o3 154 mov %i4, %o4 155 mov HVIO_POKE, %o5 156 ta FAST_TRAP 157 brnz %o0, 1f 158 mov %o0, %i0 159 stuw %o1, [%i5] 160 1: 161 ret 162 restore 163 SET_SIZE(hvio_poke) 164 165 /* 166 * arg0 - devhandle 167 * arg1 - r_addr 168 * arg2 - num_bytes 169 * arg3 - io_sync_direction 170 * 171 * ret0 - status 172 * ret1 - bytes_synched 173 */ 174 ENTRY(hvio_dma_sync) 175 mov HVIO_DMA_SYNC, %o5 176 ta FAST_TRAP 177 brz,a %o0, 1f 178 stx %o1, [%o4] 179 1: retl 180 nop 181 SET_SIZE(hvio_dma_sync) 182 183 /* 184 * arg0 - devhandle 185 * arg1 - msiq_id 186 * arg2 - r_addr 187 * arg3 - nentries 188 * 189 * ret0 - status 190 */ 191 ENTRY(hvio_msiq_conf) 192 mov HVIO_MSIQ_CONF, %o5 193 ta FAST_TRAP 194 retl 195 nop 196 SET_SIZE(hvio_msiq_conf) 197 198 /* 199 * arg0 - devhandle 200 * arg1 - msiq_id 201 * 202 * ret0 - status 203 * ret1 - r_addr 204 * ret1 - nentries 205 */ 206 ENTRY(hvio_msiq_info) 207 mov %o2, %o4 208 mov HVIO_MSIQ_INFO, %o5 209 ta FAST_TRAP 210 brnz %o0, 1f 211 nop 212 stx %o1, [%o4] 213 stuw %o2, [%o3] 214 1: retl 215 nop 216 SET_SIZE(hvio_msiq_info) 217 218 /* 219 * arg0 - devhandle 220 * arg1 - msiq_id 221 * 222 * ret0 - status 223 * ret1 - msiq_valid_state 224 */ 225 ENTRY(hvio_msiq_getvalid) 226 mov HVIO_MSIQ_GETVALID, %o5 227 ta FAST_TRAP 228 brz,a %o0, 1f 229 stuw %o1, [%o2] 230 1: retl 231 nop 232 SET_SIZE(hvio_msiq_getvalid) 233 234 /* 235 * arg0 - devhandle 236 * arg1 - msiq_id 237 * arg2 - msiq_valid_state 238 * 239 * ret0 - status 240 */ 241 ENTRY(hvio_msiq_setvalid) 242 mov HVIO_MSIQ_SETVALID, %o5 243 ta FAST_TRAP 244 retl 245 nop 246 SET_SIZE(hvio_msiq_setvalid) 247 248 /* 249 * arg0 - devhandle 250 * arg1 - msiq_id 251 * 252 * ret0 - status 253 * ret1 - msiq_state 254 */ 255 ENTRY(hvio_msiq_getstate) 256 mov HVIO_MSIQ_GETSTATE, %o5 257 ta FAST_TRAP 258 brz,a %o0, 1f 259 stuw %o1, [%o2] 260 1: retl 261 nop 262 SET_SIZE(hvio_msiq_getstate) 263 264 /* 265 * arg0 - devhandle 266 * arg1 - msiq_id 267 * arg2 - msiq_state 268 * 269 * ret0 - status 270 */ 271 ENTRY(hvio_msiq_setstate) 272 mov HVIO_MSIQ_SETSTATE, %o5 273 ta FAST_TRAP 274 retl 275 nop 276 SET_SIZE(hvio_msiq_setstate) 277 278 /* 279 * arg0 - devhandle 280 * arg1 - msiq_id 281 * 282 * ret0 - status 283 * ret1 - msiq_head 284 */ 285 ENTRY(hvio_msiq_gethead) 286 mov HVIO_MSIQ_GETHEAD, %o5 287 ta FAST_TRAP 288 brz,a %o0, 1f 289 stx %o1, [%o2] 290 1: retl 291 nop 292 SET_SIZE(hvio_msiq_gethead) 293 294 /* 295 * arg0 - devhandle 296 * arg1 - msiq_id 297 * arg2 - msiq_head 298 * 299 * ret0 - status 300 */ 301 ENTRY(hvio_msiq_sethead) 302 mov HVIO_MSIQ_SETHEAD, %o5 303 ta FAST_TRAP 304 retl 305 nop 306 SET_SIZE(hvio_msiq_sethead) 307 308 /* 309 * arg0 - devhandle 310 * arg1 - msiq_id 311 * 312 * ret0 - status 313 * ret1 - msiq_tail 314 */ 315 ENTRY(hvio_msiq_gettail) 316 mov HVIO_MSIQ_GETTAIL, %o5 317 ta FAST_TRAP 318 brz,a %o0, 1f 319 stx %o1, [%o2] 320 1: retl 321 nop 322 SET_SIZE(hvio_msiq_gettail) 323 324 /* 325 * arg0 - devhandle 326 * arg1 - msi_num 327 * 328 * ret0 - status 329 * ret1 - msiq_id 330 */ 331 ENTRY(hvio_msi_getmsiq) 332 mov HVIO_MSI_GETMSIQ, %o5 333 ta FAST_TRAP 334 brz,a %o0, 1f 335 stuw %o1, [%o2] 336 1: retl 337 nop 338 SET_SIZE(hvio_msi_getmsiq) 339 340 /* 341 * arg0 - devhandle 342 * arg1 - msi_num 343 * arg2 - msiq_id 344 * arg2 - msitype 345 * 346 * ret0 - status 347 */ 348 ENTRY(hvio_msi_setmsiq) 349 mov HVIO_MSI_SETMSIQ, %o5 350 ta FAST_TRAP 351 retl 352 nop 353 SET_SIZE(hvio_msi_setmsiq) 354 355 /* 356 * arg0 - devhandle 357 * arg1 - msi_num 358 * 359 * ret0 - status 360 * ret1 - msi_valid_state 361 */ 362 ENTRY(hvio_msi_getvalid) 363 mov HVIO_MSI_GETVALID, %o5 364 ta FAST_TRAP 365 brz,a %o0, 1f 366 stuw %o1, [%o2] 367 1: retl 368 nop 369 SET_SIZE(hvio_msi_getvalid) 370 371 /* 372 * arg0 - devhandle 373 * arg1 - msi_num 374 * arg2 - msi_valid_state 375 * 376 * ret0 - status 377 */ 378 ENTRY(hvio_msi_setvalid) 379 mov HVIO_MSI_SETVALID, %o5 380 ta FAST_TRAP 381 retl 382 nop 383 SET_SIZE(hvio_msi_setvalid) 384 385 /* 386 * arg0 - devhandle 387 * arg1 - msi_num 388 * 389 * ret0 - status 390 * ret1 - msi_state 391 */ 392 ENTRY(hvio_msi_getstate) 393 mov HVIO_MSI_GETSTATE, %o5 394 ta FAST_TRAP 395 brz,a %o0, 1f 396 stuw %o1, [%o2] 397 1: retl 398 nop 399 SET_SIZE(hvio_msi_getstate) 400 401 /* 402 * arg0 - devhandle 403 * arg1 - msi_num 404 * arg2 - msi_state 405 * 406 * ret0 - status 407 */ 408 ENTRY(hvio_msi_setstate) 409 mov HVIO_MSI_SETSTATE, %o5 410 ta FAST_TRAP 411 retl 412 nop 413 SET_SIZE(hvio_msi_setstate) 414 415 /* 416 * arg0 - devhandle 417 * arg1 - msg_type 418 * 419 * ret0 - status 420 * ret1 - msiq_id 421 */ 422 ENTRY(hvio_msg_getmsiq) 423 mov HVIO_MSG_GETMSIQ, %o5 424 ta FAST_TRAP 425 brz,a %o0, 1f 426 stuw %o1, [%o2] 427 1: retl 428 nop 429 SET_SIZE(hvio_msg_getmsiq) 430 431 /* 432 * arg0 - devhandle 433 * arg1 - msg_type 434 * arg2 - msiq_id 435 * 436 * ret0 - status 437 */ 438 ENTRY(hvio_msg_setmsiq) 439 mov HVIO_MSG_SETMSIQ, %o5 440 ta FAST_TRAP 441 retl 442 nop 443 SET_SIZE(hvio_msg_setmsiq) 444 445 /* 446 * arg0 - devhandle 447 * arg1 - msg_type 448 * 449 * ret0 - status 450 * ret1 - msg_valid_state 451 */ 452 ENTRY(hvio_msg_getvalid) 453 mov HVIO_MSG_GETVALID, %o5 454 ta FAST_TRAP 455 brz,a %o0, 1f 456 stuw %o1, [%o2] 457 1: retl 458 nop 459 SET_SIZE(hvio_msg_getvalid) 460 461 /* 462 * arg0 - devhandle 463 * arg1 - msg_type 464 * arg2 - msg_valid_state 465 * 466 * ret0 - status 467 */ 468 ENTRY(hvio_msg_setvalid) 469 mov HVIO_MSG_SETVALID, %o5 470 ta FAST_TRAP 471 retl 472 nop 473 SET_SIZE(hvio_msg_setvalid) 474 475 /* 476 * arg0 - devhandle 477 * arg1 - devino 478 * arg2 - pci_device 479 * 480 * ret0 - status 481 */ 482 ENTRY(pci_error_send) 483 mov PCI_ERROR_SEND, %o5 484 ta FAST_TRAP 485 retl 486 nop 487 SET_SIZE(pci_error_send) 488 489 #define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3 490 491 ! px_phys_acc_4v: Do physical address read. 492 ! 493 ! After SHIFT_REGS: 494 ! %o0 is "from" address 495 ! %o1 is "to" address 496 ! 497 ! Assumes 8 byte data and that alignment is correct. 498 ! 499 ! Always returns success (0) in %o0 500 501 ! px_phys_acc_4v must not be split across pages. 502 ! 503 ! ATTN: Be sure that the alignment value is larger than the size of 504 ! the px_phys_acc_4v function. 505 ! 506 .align 0x40 507 508 ENTRY(px_phys_acc_4v) 509 510 SHIFT_REGS 511 ldx [%o0], %g1 512 stx %g1, [%o1] 513 membar #Sync ! Make sure the loads take 514 mov %g0, %o0 515 done 516 SET_SIZE(px_phys_acc_4v) 517 518 /* 519 * arg0 - devhandle 520 * 521 * ret0 - status 522 */ 523 ENTRY(pci_iov_root_configured) 524 mov PCI_IOV_ROOT_CONFIGURED, %o5 525 ta FAST_TRAP 526 retl 527 nop 528 SET_SIZE(pci_iov_root_configured) 529