Print this page
de-linting of .s files
| Split |
Close |
| Expand all |
| Collapse all |
--- old/usr/src/uts/sun4v/cpu/niagara_asm.s
+++ new/usr/src/uts/sun4v/cpu/niagara_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
|
↓ open down ↓ |
15 lines elided |
↑ open up ↑ |
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 -#pragma ident "%Z%%M% %I% %E% SMI"
27 -
28 -#if !defined(lint)
29 26 #include "assym.h"
30 -#endif
31 27
32 28 /*
33 29 * Niagara processor specific assembly routines
34 30 */
35 31
36 32 #include <sys/asm_linkage.h>
37 33 #include <sys/machasi.h>
38 34 #include <sys/machparam.h>
39 35 #include <sys/hypervisor_api.h>
40 36 #include <sys/niagararegs.h>
41 37 #include <sys/machasi.h>
42 38 #include <sys/niagaraasi.h>
43 39 #include <vm/hat_sfmmu.h>
44 40
45 -#if defined(lint)
46 -/*ARGSUSED*/
47 -uint64_t
48 -hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
49 -{ return (0); }
50 -
51 -/*ARGSUSED*/
52 -uint64_t
53 -hv_niagara_setperf(uint64_t perfreg, uint64_t data)
54 -{ return (0); }
55 -
56 -#else /* lint */
57 -
58 41 /*
59 42 * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
60 43 */
61 44 ENTRY(hv_niagara_getperf)
62 45 mov %o1, %o4 ! save datap
63 46 mov HV_NIAGARA_GETPERF, %o5
64 47 ta FAST_TRAP
65 48 brz,a %o0, 1f
66 49 stx %o1, [%o4]
67 50 1:
68 51 retl
69 52 nop
70 53 SET_SIZE(hv_niagara_getperf)
71 54
|
↓ open down ↓ |
4 lines elided |
↑ open up ↑ |
72 55 /*
73 56 * hv_niagara_setperf(uint64_t perfreg, uint64_t data)
74 57 */
75 58 ENTRY(hv_niagara_setperf)
76 59 mov HV_NIAGARA_SETPERF, %o5
77 60 ta FAST_TRAP
78 61 retl
79 62 nop
80 63 SET_SIZE(hv_niagara_setperf)
81 64
82 -#endif /* !lint */
83 -
84 -#if defined (lint)
85 -/*
86 - * Invalidate all of the entries within the TSB, by setting the inv bit
87 - * in the tte_tag field of each tsbe.
88 - *
89 - * We take advantage of the fact that the TSBs are page aligned and a
90 - * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI.
91 - *
92 - * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice
93 - * (in short, we set all bits in the upper word of the tag, and we give the
94 - * invalid bit precedence over other tag bits in both places).
95 - */
96 -/*ARGSUSED*/
97 -void
98 -cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
99 -{}
100 -
101 -#else /* lint */
102 -
103 65 ENTRY(cpu_inv_tsb)
104 66
105 67 /*
106 68 * The following code assumes that the tsb_base (%o0) is 256 bytes
107 69 * aligned and the tsb_bytes count is multiple of 256 bytes.
108 70 */
109 71
110 72 wr %g0, ASI_BLK_INIT_ST_QUAD_LDD_P, %asi
111 73 set TSBTAG_INVALID, %o2
112 74 sllx %o2, 32, %o2 ! INV bit in upper 32 bits of the tag
113 75 1:
114 76 stxa %o2, [%o0+0x0]%asi
115 77 stxa %o2, [%o0+0x40]%asi
116 78 stxa %o2, [%o0+0x80]%asi
117 79 stxa %o2, [%o0+0xc0]%asi
118 80
119 81 stxa %o2, [%o0+0x10]%asi
120 82 stxa %o2, [%o0+0x20]%asi
121 83 stxa %o2, [%o0+0x30]%asi
122 84
123 85 stxa %o2, [%o0+0x50]%asi
124 86 stxa %o2, [%o0+0x60]%asi
125 87 stxa %o2, [%o0+0x70]%asi
126 88
127 89 stxa %o2, [%o0+0x90]%asi
128 90 stxa %o2, [%o0+0xa0]%asi
129 91 stxa %o2, [%o0+0xb0]%asi
130 92
131 93 stxa %o2, [%o0+0xd0]%asi
132 94 stxa %o2, [%o0+0xe0]%asi
133 95 stxa %o2, [%o0+0xf0]%asi
|
↓ open down ↓ |
21 lines elided |
↑ open up ↑ |
134 96
135 97 subcc %o1, 0x100, %o1
136 98 bgu,pt %ncc, 1b
137 99 add %o0, 0x100, %o0
138 100
139 101 membar #Sync
140 102 retl
141 103 nop
142 104
143 105 SET_SIZE(cpu_inv_tsb)
144 -#endif /* lint */
145 106
146 -#if defined(lint)
147 -/*ARGSUSED*/
148 -uint64_t
149 -hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf)
150 -{ return (0); }
151 -
152 -/*ARGSUSED*/
153 -uint64_t
154 -hv_niagara_mmustat_info(uint64_t *buf)
155 -{ return (0); }
156 -
157 -#else /* lint */
158 -
159 107 /*
160 108 * hv_niagara_mmustat_conf(uint64_t buf, uint64_t *prev_buf)
161 109 */
162 110 ENTRY(hv_niagara_mmustat_conf)
163 111 mov %o1, %o4 ! save prev_buf
164 112 mov HV_NIAGARA_MMUSTAT_CONF, %o5
165 113 ta FAST_TRAP
166 114 retl
167 115 stx %o1, [%o4]
168 116 SET_SIZE(hv_niagara_mmustat_conf)
169 117
170 118 /*
|
↓ open down ↓ |
2 lines elided |
↑ open up ↑ |
171 119 * hv_niagara_mmustat_info(uint64_t *buf)
172 120 */
173 121 ENTRY(hv_niagara_mmustat_info)
174 122 mov %o0, %o4 ! save buf
175 123 mov HV_NIAGARA_MMUSTAT_INFO, %o5
176 124 ta FAST_TRAP
177 125 retl
178 126 stx %o1, [%o4]
179 127 SET_SIZE(hv_niagara_mmustat_info)
180 128
181 -#endif /* !lint */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX