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--- old/usr/src/uts/sun4u/io/panther_asm.s
+++ new/usr/src/uts/sun4u/io/panther_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
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18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 *
25 25 * Assembly code support for the Cheetah+ module
26 26 */
27 27
28 -#pragma ident "%Z%%M% %I% %E% SMI"
29 -
30 -#if !defined(lint)
31 28 #include "assym.h"
32 -#endif /* lint */
33 29
34 30 #include <sys/asm_linkage.h>
35 31 #include <sys/mmu.h>
36 32 #include <vm/hat_sfmmu.h>
37 33 #include <sys/machparam.h>
38 34 #include <sys/machcpuvar.h>
39 35 #include <sys/machthread.h>
40 36 #include <sys/machtrap.h>
41 37 #include <sys/privregs.h>
42 38 #include <sys/asm_linkage.h>
43 39 #include <sys/trap.h>
44 40 #include <sys/cheetahregs.h>
45 41 #include <sys/xc_impl.h>
46 42 #include <sys/intreg.h>
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47 43 #include <sys/async.h>
48 44 #include <sys/clock.h>
49 45 #include <sys/cheetahasm.h>
50 46 #include <sys/cmpregs.h>
51 47
52 48 #ifdef TRAPTRACE
53 49 #include <sys/traptrace.h>
54 50 #endif /* TRAPTRACE */
55 51
56 52
57 -#if !defined(lint)
58 -
59 53 .global retire_l2_start
60 54 .global retire_l2_end
61 55 .global unretire_l2_start
62 56 .global unretire_l2_end
63 57 .global retire_l3_start
64 58 .global retire_l3_end
65 59 .global unretire_l3_start
66 60 .global unretire_l3_end
67 61
68 62 /*
69 63 * Panther version to reflush a line from both the L2 cache and L3
70 64 * cache by the respective indexes. Flushes all ways of the line from
71 65 * each cache.
72 66 *
73 67 * l2_index Index into the L2$ of the line to be flushed. This
74 68 * register will not be modified by this routine.
75 69 * l3_index Index into the L3$ of the line to be flushed. This
76 70 * register will not be modified by this routine.
77 71 * scr2 scratch register.
78 72 * scr3 scratch register.
79 73 *
80 74 */
81 75 #define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \
82 76 set PN_L2_MAX_SET, scr2; \
83 77 set PN_L2_SET_SIZE, scr3; \
84 78 1: \
85 79 ldxa [l2_index + scr2]ASI_L2_TAG, %g0; \
86 80 cmp scr2, %g0; \
87 81 bg,a 1b; \
88 82 sub scr2, scr3, scr2; \
89 83 mov 6, scr2; \
90 84 6: \
91 85 cmp scr2, %g0; \
92 86 bg,a 6b; \
93 87 sub scr2, 1, scr2; \
94 88 set PN_L3_MAX_SET, scr2; \
95 89 set PN_L3_SET_SIZE, scr3; \
96 90 2: \
97 91 ldxa [l3_index + scr2]ASI_EC_DIAG, %g0; \
98 92 cmp scr2, %g0; \
99 93 bg,a 2b; \
100 94 sub scr2, scr3, scr2;
101 95
102 96 /*
103 97 * Panther version of ecache_flush_line. Flushes the line corresponding
104 98 * to physaddr from both the L2 cache and the L3 cache.
105 99 *
106 100 * physaddr Input: Physical address to flush.
107 101 * Output: Physical address to flush (preserved).
108 102 * l2_idx_out Input: scratch register.
109 103 * Output: Index into the L2$ of the line to be flushed.
110 104 * l3_idx_out Input: scratch register.
111 105 * Output: Index into the L3$ of the line to be flushed.
112 106 * scr3 scratch register.
113 107 * scr4 scratch register.
114 108 *
115 109 */
116 110 #define PN_ECACHE_FLUSH_LINE(physaddr, l2_idx_out, l3_idx_out, scr3, scr4) \
117 111 set PN_L3_SET_SIZE, l2_idx_out; \
118 112 sub l2_idx_out, 1, l2_idx_out; \
119 113 and physaddr, l2_idx_out, l3_idx_out; \
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120 114 set PN_L3_IDX_DISP_FLUSH, l2_idx_out; \
121 115 or l2_idx_out, l3_idx_out, l3_idx_out; \
122 116 set PN_L2_SET_SIZE, l2_idx_out; \
123 117 sub l2_idx_out, 1, l2_idx_out; \
124 118 and physaddr, l2_idx_out, l2_idx_out; \
125 119 set PN_L2_IDX_DISP_FLUSH, scr3; \
126 120 or l2_idx_out, scr3, l2_idx_out; \
127 121 PN_ECACHE_REFLUSH_LINE(l2_idx_out, l3_idx_out, scr3, scr4)
128 122
129 123
130 -#endif /* !lint */
131 -
132 -#if defined(lint)
133 -
134 -/*ARGSUSED*/
135 -int
136 -retire_l2(uint64_t tag_addr, uint64_t pattern)
137 -{return 0;}
138 -
139 -#else
140 124 .align 4096
141 125 ENTRY(retire_l2)
142 126 retire_l2_start:
143 127
144 128 ! since we disable interrupts, we don't need to do kpreempt_disable()
145 129 rdpr %pstate, %o2
146 130 andn %o2, PSTATE_IE, %g1
147 131 wrpr %g0, %g1, %pstate ! disable interrupts
148 132 /*
149 133 * Save current DCU state. Turn off IPS
150 134 */
151 135 setx DCU_IPS_MASK, %g2, %o3
152 136 ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
153 137 andn %g1, %o3, %g4
154 138 stxa %g4, [%g0]ASI_DCU
155 139 flush %g0
156 140 PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
157 141 clr %o5 ! assume success
158 142 8:
159 143 PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %g2, %g3)
160 144 1:
161 145 ! Check if line is invalid; if so, NA it.
162 146 ldxa [%o0]ASI_L2_TAG, %o3
163 147 btst 0x7, %o3
164 148 bnz %xcc, 2f
165 149 nop
166 150 stxa %o1, [%o0]ASI_L2_TAG
167 151 membar #Sync ! still on same cache line
168 152 ! now delay 15 cycles so we don't have hazard when we return
169 153 mov 16, %o1
170 154 1:
171 155 brnz,pt %o1, 1b
172 156 dec %o1
173 157 9:
174 158 ! UNPARK-SIBLING_CORE is 7 instructions, so we cross a cache boundary
175 159 UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
176 160 /*
177 161 * Restore the DCU
178 162 */
179 163 stxa %g1, [%g0]ASI_DCU
180 164 flush %g0
181 165 wrpr %g0, %o2, %pstate !restore pstate
182 166 retl
183 167 mov %o5, %o0
184 168 2:
185 169 ! It is OK to have STATE as NA (if so, nothing to do!)
186 170 and %o3, 0x7, %o3
187 171 cmp %o3, 0x5
188 172 be,a,pt %xcc, 9b
189 173 mov 1, %o5 ! indicate was already NA
190 174 ! Hmm. Not INV, not NA.
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191 175 cmp %o5, 0
192 176 be,a,pt %xcc, 8b ! Flush the cacheline again
193 177 mov 2, %o5 ! indicate retry was done
194 178 ! We already Flushed cacheline second time. Return -1
195 179 clr %o5
196 180 ba 9b
197 181 dec %o5
198 182 retire_l2_end:
199 183 SET_SIZE(retire_l2)
200 184
201 -#endif /* lint */
202 -
203 -#if defined(lint)
204 -
205 -/*
206 - */
207 -/*ARGSUSED*/
208 -int
209 -unretire_l2(uint64_t tag_addr, uint64_t pattern)
210 -{return 0;}
211 -
212 -#else
213 185 ENTRY(unretire_l2)
214 186 unretire_l2_start:
215 187
216 188 ! since we disable interrupts, we don't need to do kpreempt_disable()
217 189 rdpr %pstate, %o2
218 190 andn %o2, PSTATE_IE, %g1
219 191 wrpr %g0, %g1, %pstate ! disable interrupts
220 192 /*
221 193 * Save current DCU state. Turn off IPS
222 194 */
223 195 setx DCU_IPS_MASK, %g2, %o3
224 196 ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
225 197 andn %g1, %o3, %g4
226 198 stxa %g4, [%g0]ASI_DCU
227 199 flush %g0 /* flush required after changing the IC bit */
228 200 PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
229 201
230 202 PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %o5, %g2)
231 203 1:
232 204 clr %o5 ! assume success
233 205 ! Check that line is in NA state; if so, INV it.
234 206 ldxa [%o0]ASI_L2_TAG, %o3
235 207 and %o3, 0x7, %o3
236 208 cmp %o3, 0x5
237 209 bne,a,pt %xcc, 9f ! Wasn't NA, so something is wrong
238 210 dec %o5 ! indicate not NA
239 211 stxa %g0, [%o0]ASI_L2_TAG
240 212 membar #Sync
241 213 ! now delay 15 cycles so we don't have hazard when we return
242 214 mov 16, %o1
243 215 1:
244 216 brnz,pt %o1, 1b
245 217 dec %o1
246 218 9:
247 219 ! UNPARK-SIBLING_CORE is 7 instructions
248 220 UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
249 221 /*
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250 222 * Restore the DCU
251 223 */
252 224 stxa %g1, [%g0]ASI_DCU
253 225 flush %g0
254 226 wrpr %g0, %o2, %pstate !restore pstate
255 227 retl
256 228 mov %o5, %o0
257 229 unretire_l2_end:
258 230 SET_SIZE(unretire_l2)
259 231
260 -#endif /* lint */
261 -
262 -#if defined(lint)
263 -
264 -/*ARGSUSED*/
265 -int
266 -retire_l3(uint64_t tag_addr, uint64_t pattern)
267 -{return 0;}
268 -
269 -#else
270 232 ENTRY(retire_l3)
271 233 retire_l3_start:
272 234
273 235 ! since we disable interrupts, we don't need to do kpreempt_disable()
274 236 rdpr %pstate, %o2
275 237 andn %o2, PSTATE_IE, %g1
276 238 wrpr %g0, %g1, %pstate ! disable interrupts
277 239 /*
278 240 * Save current DCU state. Turn off IPS
279 241 */
280 242 setx DCU_IPS_MASK, %g2, %o3
281 243 ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
282 244 andn %g1, %o3, %g4
283 245 stxa %g4, [%g0]ASI_DCU
284 246 flush %g0 /* flush required after changing the IC bit */
285 247 PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
286 248
287 249 ! PN-ECACHE-FLUSH_LINE is 30 instructions
288 250 PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %o5, %g2)
289 251 1:
290 252 clr %o5 ! assume success
291 253 ! Check if line is invalid; if so, NA it.
292 254 ldxa [%o0]ASI_EC_DIAG, %o3
293 255 btst 0x7, %o3
294 256 bnz %xcc, 2f
295 257 nop
296 258 stxa %o1, [%o0]ASI_EC_DIAG
297 259 membar #Sync ! still on same cache line
298 260 ! now delay 15 cycles so we don't have hazard when we return
299 261 mov 16, %o1
300 262 1:
301 263 brnz,pt %o1, 1b
302 264 dec %o1
303 265 9:
304 266 ! UNPARK-SIBLING_CORE is 7 instructions, so we cross a cache boundary
305 267 UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
306 268 /*
307 269 * Restore the DCU
308 270 */
309 271 stxa %g1, [%g0]ASI_DCU
310 272 flush %g0
311 273 wrpr %g0, %o2, %pstate !restore pstate
312 274 retl
313 275 mov %o5, %o0
314 276 2:
315 277 ! It is OK to have STATE as NA (if so, nothing to do!)
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316 278 and %o3, 0x7, %o3
317 279 cmp %o3, 0x5
318 280 be,a,pt %xcc, 9b
319 281 inc %o5 ! indicate was already NA
320 282 ! Hmm. Not INV, not NA
321 283 ba 9b
322 284 dec %o5
323 285 retire_l3_end:
324 286 SET_SIZE(retire_l3)
325 287
326 -#endif /* lint */
327 -
328 -#if defined(lint)
329 -
330 -/*
331 - */
332 -/*ARGSUSED*/
333 -int
334 -unretire_l3(uint64_t tag_addr, uint64_t pattern)
335 -{return 0;}
336 -
337 -#else
338 288 ENTRY(unretire_l3)
339 289 unretire_l3_start:
340 290
341 291 ! since we disable interrupts, we don't need to do kpreempt_disable()
342 292 rdpr %pstate, %o2
343 293 andn %o2, PSTATE_IE, %g1
344 294 wrpr %g0, %g1, %pstate ! disable interrupts
345 295 /*
346 296 * Save current DCU state. Turn off IPS
347 297 */
348 298 setx DCU_IPS_MASK, %g2, %o3
349 299 ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
350 300 andn %g1, %o3, %g4
351 301 stxa %g4, [%g0]ASI_DCU
352 302 flush %g0 /* flush required after changing the IC bit */
353 303 PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
354 304
355 305 PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %o5, %g2)
356 306 1:
357 307 clr %o5 ! assume success
358 308 ! Check that line is in NA state; if so, INV it.
359 309 ldxa [%o0]ASI_EC_DIAG, %o3
360 310 and %o3, 0x7, %o3
361 311 cmp %o3, 0x5
362 312 bne,a,pt %xcc, 9f ! Wasn't NA, so something is wrong
363 313 dec %o5 ! indicate not NA
364 314 stxa %g0, [%o0]ASI_EC_DIAG
365 315 membar #Sync
366 316 ! now delay 15 cycles so we don't have hazard when we return
367 317 mov 16, %o1
368 318 1:
369 319 brnz,pt %o1, 1b
370 320 dec %o1
371 321 9:
372 322 ! UNPARK-SIBLING_CORE is 7 instructions
373 323 UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
374 324 /*
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375 325 * Restore the DCU
376 326 */
377 327 stxa %g1, [%g0]ASI_DCU
378 328 flush %g0
379 329 wrpr %g0, %o2, %pstate !restore pstate
380 330 retl
381 331 mov %o5, %o0
382 332 unretire_l3_end:
383 333 SET_SIZE(unretire_l3)
384 334
385 -#endif /* lint */
386 -
387 -#if defined(lint)
388 -
389 -/*ARGSUSED*/
390 -int
391 -retire_l2_alternate(uint64_t tag_addr, uint64_t pattern)
392 -{return 0;}
393 -
394 -#else
395 335 .align 2048
396 336
397 337 ENTRY(retire_l2_alternate)
398 338
399 339 ! since we disable interrupts, we don't need to do kpreempt_disable()
400 340 rdpr %pstate, %o2
401 341 andn %o2, PSTATE_IE, %g1
402 342 wrpr %g0, %g1, %pstate ! disable interrupts
403 343 /*
404 344 * Save current DCU state. Turn off IPS
405 345 */
406 346 setx DCU_IPS_MASK, %g2, %o3
407 347 ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
408 348 andn %g1, %o3, %g4
409 349 stxa %g4, [%g0]ASI_DCU
410 350 flush %g0
411 351 PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
412 352 clr %o5 ! assume success
413 353 8:
414 354 PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %g2, %g3)
415 355 1:
416 356 ! Check if line is invalid; if so, NA it.
417 357 ldxa [%o0]ASI_L2_TAG, %o3
418 358 btst 0x7, %o3
419 359 bnz %xcc, 2f
420 360 nop
421 361 stxa %o1, [%o0]ASI_L2_TAG
422 362 membar #Sync ! still on same cache line
423 363 ! now delay 15 cycles so we don't have hazard when we return
424 364 mov 16, %o1
425 365 1:
426 366 brnz,pt %o1, 1b
427 367 dec %o1
428 368 9:
429 369 ! UNPARK-SIBLING_CORE is 7 instructions, so we cross a cache boundary
430 370 UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
431 371 /*
432 372 * Restore the DCU
433 373 */
434 374 stxa %g1, [%g0]ASI_DCU
435 375 flush %g0
436 376 wrpr %g0, %o2, %pstate !restore pstate
437 377 retl
438 378 mov %o5, %o0
439 379 2:
440 380 ! It is OK to have STATE as NA (if so, nothing to do!)
441 381 and %o3, 0x7, %o3
442 382 cmp %o3, 0x5
443 383 be,a,pt %xcc, 9b
444 384 mov 1, %o5 ! indicate was already NA
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445 385 ! Hmm. Not INV, not NA.
446 386 cmp %o5, 0
447 387 be,a,pt %xcc, 8b ! Flush the cacheline again
448 388 mov 2, %o5 ! indicate retry was done
449 389 ! We already Flushed cacheline second time. Return -1
450 390 clr %o5
451 391 ba 9b
452 392 dec %o5
453 393 SET_SIZE(retire_l2_alternate)
454 394
455 -#endif /* lint */
456 -
457 -#if defined(lint)
458 -
459 -/*
460 - */
461 -/*ARGSUSED*/
462 -int
463 -unretire_l2_alternate(uint64_t tag_addr, uint64_t pattern)
464 -{return 0;}
465 -
466 -#else
467 395 ENTRY(unretire_l2_alternate)
468 396
469 397 ! since we disable interrupts, we don't need to do kpreempt_disable()
470 398 rdpr %pstate, %o2
471 399 andn %o2, PSTATE_IE, %g1
472 400 wrpr %g0, %g1, %pstate ! disable interrupts
473 401 /*
474 402 * Save current DCU state. Turn off IPS
475 403 */
476 404 setx DCU_IPS_MASK, %g2, %o3
477 405 ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
478 406 andn %g1, %o3, %g4
479 407 stxa %g4, [%g0]ASI_DCU
480 408 flush %g0 /* flush required after changing the IC bit */
481 409 PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
482 410
483 411 PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %o5, %g2)
484 412 1:
485 413 clr %o5 ! assume success
486 414 ! Check that line is in NA state; if so, INV it.
487 415 ldxa [%o0]ASI_L2_TAG, %o3
488 416 and %o3, 0x7, %o3
489 417 cmp %o3, 0x5
490 418 bne,a,pt %xcc, 9f ! Wasn't NA, so something is wrong
491 419 dec %o5 ! indicate not NA
492 420 stxa %g0, [%o0]ASI_L2_TAG
493 421 membar #Sync
494 422 ! now delay 15 cycles so we don't have hazard when we return
495 423 mov 16, %o1
496 424 1:
497 425 brnz,pt %o1, 1b
498 426 dec %o1
499 427 9:
500 428 ! UNPARK-SIBLING_CORE is 7 instructions
501 429 UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
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502 430 /*
503 431 * Restore the DCU
504 432 */
505 433 stxa %g1, [%g0]ASI_DCU
506 434 flush %g0
507 435 wrpr %g0, %o2, %pstate !restore pstate
508 436 retl
509 437 mov %o5, %o0
510 438 SET_SIZE(unretire_l2_alternate)
511 439
512 -#endif /* lint */
513 -
514 -#if defined(lint)
515 -
516 -/*ARGSUSED*/
517 -int
518 -retire_l3_alternate(uint64_t tag_addr, uint64_t pattern)
519 -{return 0;}
520 -
521 -#else
522 440 ENTRY(retire_l3_alternate)
523 441
524 442 ! since we disable interrupts, we don't need to do kpreempt_disable()
525 443 rdpr %pstate, %o2
526 444 andn %o2, PSTATE_IE, %g1
527 445 wrpr %g0, %g1, %pstate ! disable interrupts
528 446 /*
529 447 * Save current DCU state. Turn off IPS
530 448 */
531 449 setx DCU_IPS_MASK, %g2, %o3
532 450 ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
533 451 andn %g1, %o3, %g4
534 452 stxa %g4, [%g0]ASI_DCU
535 453 flush %g0 /* flush required after changing the IC bit */
536 454 PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
537 455
538 456 ! PN-ECACHE-FLUSH_LINE is 30 instructions
539 457 PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %o5, %g2)
540 458 1:
541 459 clr %o5 ! assume success
542 460 ! Check if line is invalid; if so, NA it.
543 461 ldxa [%o0]ASI_EC_DIAG, %o3
544 462 btst 0x7, %o3
545 463 bnz %xcc, 2f
546 464 nop
547 465 stxa %o1, [%o0]ASI_EC_DIAG
548 466 membar #Sync ! still on same cache line
549 467 ! now delay 15 cycles so we don't have hazard when we return
550 468 mov 16, %o1
551 469 1:
552 470 brnz,pt %o1, 1b
553 471 dec %o1
554 472 9:
555 473 ! UNPARK-SIBLING_CORE is 7 instructions, so we cross a cache boundary
556 474 UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
557 475 /*
558 476 * Restore the DCU
559 477 */
560 478 stxa %g1, [%g0]ASI_DCU
561 479 flush %g0
562 480 wrpr %g0, %o2, %pstate !restore pstate
563 481 retl
564 482 mov %o5, %o0
565 483 2:
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566 484 ! It is OK to have STATE as NA (if so, nothing to do!)
567 485 and %o3, 0x7, %o3
568 486 cmp %o3, 0x5
569 487 be,a,pt %xcc, 9b
570 488 inc %o5 ! indicate was already NA
571 489 ! Hmm. Not INV, not NA
572 490 ba 9b
573 491 dec %o5
574 492 SET_SIZE(retire_l3_alternate)
575 493
576 -#endif /* lint */
577 -
578 -#if defined(lint)
579 -
580 -/*
581 - */
582 -/*ARGSUSED*/
583 -int
584 -unretire_l3_alternate(uint64_t tag_addr, uint64_t pattern)
585 -{return 0;}
586 -
587 -#else
588 494 ENTRY(unretire_l3_alternate)
589 495
590 496 ! since we disable interrupts, we don't need to do kpreempt_disable()
591 497 rdpr %pstate, %o2
592 498 andn %o2, PSTATE_IE, %g1
593 499 wrpr %g0, %g1, %pstate ! disable interrupts
594 500 /*
595 501 * Save current DCU state. Turn off IPS
596 502 */
597 503 setx DCU_IPS_MASK, %g2, %o3
598 504 ldxa [%g0]ASI_DCU, %g1 ! save DCU in %g1
599 505 andn %g1, %o3, %g4
600 506 stxa %g4, [%g0]ASI_DCU
601 507 flush %g0 /* flush required after changing the IC bit */
602 508 PARK_SIBLING_CORE(%g1, %o3, %o4) ! %g1 has DCU value
603 509
604 510 PN_ECACHE_FLUSH_LINE(%o0, %o3, %o4, %o5, %g2)
605 511 1:
606 512 clr %o5 ! assume success
607 513 ! Check that line is in NA state; if so, INV it.
608 514 ldxa [%o0]ASI_EC_DIAG, %o3
609 515 and %o3, 0x7, %o3
610 516 cmp %o3, 0x5
611 517 bne,a,pt %xcc, 9f ! Wasn't NA, so something is wrong
612 518 dec %o5 ! indicate not NA
613 519 stxa %g0, [%o0]ASI_EC_DIAG
614 520 membar #Sync
615 521 ! now delay 15 cycles so we don't have hazard when we return
616 522 mov 16, %o1
617 523 1:
618 524 brnz,pt %o1, 1b
619 525 dec %o1
620 526 9:
621 527 ! UNPARK-SIBLING_CORE is 7 instructions
622 528 UNPARK_SIBLING_CORE(%g1, %o3, %o4) ! 7 instructions
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623 529 /*
624 530 * Restore the DCU
625 531 */
626 532 stxa %g1, [%g0]ASI_DCU
627 533 flush %g0
628 534 wrpr %g0, %o2, %pstate !restore pstate
629 535 retl
630 536 mov %o5, %o0
631 537 SET_SIZE(unretire_l3_alternate)
632 538
633 -#endif /* lint */
634 -
635 -#if defined(lint)
636 -
637 -/*ARGSUSED*/
638 -void
639 -get_ecache_dtags_tl1(uint64_t afar, ch_cpu_logout_t *clop)
640 -{ }
641 -
642 -#else
643 539 ENTRY(get_ecache_dtags_tl1)
644 540
645 541
646 542 PARK_SIBLING_CORE(%g3, %g4, %g5)
647 543 add %g2, CH_CLO_DATA + CH_CHD_EC_DATA, %g2
648 544 rd %asi, %g4
649 545 wr %g0, ASI_N, %asi
650 546 GET_ECACHE_DTAGS(%g1, %g2, %g5, %g6, %g7)
651 547 wr %g4, %asi
652 548 UNPARK_SIBLING_CORE(%g3, %g4, %g5) ! can use %g3 again
653 549
654 550 retry
655 551 SET_SIZE(get_ecache_dtags_tl1)
656 552
657 -#endif /* lint */
658 -
659 -#if defined(lint)
660 -/*ARGSUSED*/
661 -void
662 -get_l2_tag_tl1(uint64_t tag_addr, uint64_t tag_data_ptr)
663 -{ }
664 -
665 -#else
666 553 ENTRY(get_l2_tag_tl1)
667 554
668 555 /*
669 556 * Now read the tag data
670 557 */
671 558 ldxa [%g1]ASI_L2_TAG, %g4 ! save tag_data
672 559 stx %g4, [%g2]
673 560
674 561 retry
675 562 SET_SIZE(get_l2_tag_tl1)
676 563
677 -#endif /* lint */
678 -
679 -#if defined(lint)
680 -/*ARGSUSED*/
681 -void
682 -get_l3_tag_tl1(uint64_t tag_addr, uint64_t tag_data_ptr)
683 -{ }
684 -
685 -#else
686 564 ENTRY(get_l3_tag_tl1)
687 565
688 566 /*
689 567 * Now read the tag data
690 568 */
691 569 ldxa [%g1]ASI_EC_DIAG, %g4 ! save tag_data
692 570 stx %g4, [%g2]
693 571
694 572 retry
695 573 SET_SIZE(get_l3_tag_tl1)
696 -
697 -#endif /* lint */
698 574
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