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de-linting of .s files

@@ -23,13 +23,11 @@
  * Use is subject to license terms.
  *
  * Assembly code support for the Olympus-C module
  */
 
-#if !defined(lint)
 #include "assym.h"
-#endif  /* lint */
 
 #include <sys/asm_linkage.h>
 #include <sys/mmu.h>
 #include <vm/hat_sfmmu.h>
 #include <sys/machparam.h>

@@ -65,19 +63,10 @@
 
 /*
  * SPARC64-VI MMU and Cache operations.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flushpage(caddr_t vaddr, uint64_t sfmmup)
-{}
-
-#else   /* lint */
-
         ENTRY_NP(vtag_flushpage)
         /*
          * flush page from the tlb
          *
          * %o0 = vaddr

@@ -142,21 +131,11 @@
 
         retl
         wrpr    %g0, %o5, %pstate               /* enable interrupts */
         SET_SIZE(vtag_flushpage)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-void
-vtag_flushall(void)
-{}
-
-#else   /* lint */
-
         ENTRY_NP2(vtag_flushall, demap_all)
         /*
          * flush the tlb
          */
         sethi   %hi(FLUSH_ADDR), %o3

@@ -167,22 +146,11 @@
         retl
         nop
         SET_SIZE(demap_all)
         SET_SIZE(vtag_flushall)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flushpage_tl1(uint64_t vaddr, uint64_t sfmmup)
-{}
-
-#else   /* lint */
-
         ENTRY_NP(vtag_flushpage_tl1)
         /*
          * x-trap to flush page from tlb and tsb
          *
          * %g1 = vaddr, zero-extended on 32-bit kernel

@@ -223,22 +191,11 @@
         stxa    %g0, [%g1]ASI_ITLB_DEMAP
         stxa    %g5, [%g4]ASI_DMMU              ! restore old ctxnum
         retry
         SET_SIZE(vtag_flushpage_tl1)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vtag_flush_pgcnt_tl1(uint64_t vaddr, uint64_t sfmmup_pgcnt)
-{}
-
-#else   /* lint */
-
         ENTRY_NP(vtag_flush_pgcnt_tl1)
         /*
          * x-trap to flush pgcnt MMU_PAGESIZE pages from tlb
          *
          * %g1 = vaddr, zero-extended on 32-bit kernel

@@ -313,22 +270,11 @@
 
         stxa    %g6, [%g4]ASI_DMMU              /* restore old ctxnum */
         retry
         SET_SIZE(vtag_flush_pgcnt_tl1)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2)
-{}
-
-#else   /* lint */
-
         ENTRY_NP(vtag_flushall_tl1)
         /*
          * x-trap to flush tlb
          */
         set     DEMAP_ALL_TYPE, %g4

@@ -335,94 +281,38 @@
         stxa    %g0, [%g4]ASI_DTLB_DEMAP
         stxa    %g0, [%g4]ASI_ITLB_DEMAP
         retry
         SET_SIZE(vtag_flushall_tl1)
 
-#endif  /* lint */
 
-
 /*
  * VAC (virtual address conflict) does not apply to OPL.
  * VAC resolution is managed by the Olympus processor hardware.
  * As a result, all OPL VAC flushing routines are no-ops.
  */
 
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushpage(pfn_t pfnum, int vcolor)
-{}
-
-#else   /* lint */
-
         ENTRY(vac_flushpage)
         retl
           nop
         SET_SIZE(vac_flushpage)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushpage_tl1(uint64_t pfnum, uint64_t vcolor)
-{}
-
-#else   /* lint */
-
         ENTRY_NP(vac_flushpage_tl1)
         retry
         SET_SIZE(vac_flushpage_tl1)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushcolor(int vcolor, pfn_t pfnum)
-{}
-
-#else   /* lint */
-
         ENTRY(vac_flushcolor)
         retl
          nop
         SET_SIZE(vac_flushcolor)
 
-#endif  /* lint */
 
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-vac_flushcolor_tl1(uint64_t vcolor, uint64_t pfnum)
-{}
-
-#else   /* lint */
-
         ENTRY(vac_flushcolor_tl1)
         retry
         SET_SIZE(vac_flushcolor_tl1)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-int
-idsr_busy(void)
-{
-        return (0);
-}
-
-#else   /* lint */
-
 /*
  * Determine whether or not the IDSR is busy.
  * Entry: no arguments
  * Returns: 1 if busy, 0 otherwise
  */

@@ -435,26 +325,10 @@
 1:
         retl
         nop
         SET_SIZE(idsr_busy)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-/* ARGSUSED */
-void
-init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
-{}
-
-#else   /* lint */
-
         .global _dispatch_status_busy
 _dispatch_status_busy:
         .asciz  "ASI_INTR_DISPATCH_STATUS error: busy"
         .align  4
 

@@ -504,22 +378,11 @@
         retl
         nop
         SET_SIZE(init_mondo_nocheck)
         SET_SIZE(init_mondo)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-shipit(int upaid, int bn)
-{ return; }
-
-#else   /* lint */
-
 /*
  * Ship mondo to aid using busy/nack pair bn
  */
         ENTRY_NP(shipit)
         sll     %o0, IDCR_PID_SHIFT, %g1        ! IDCR<23:14> = agent id

@@ -530,22 +393,11 @@
         membar  #Sync
         retl
         nop
         SET_SIZE(shipit)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-flush_instr_mem(caddr_t vaddr, size_t len)
-{}
-
-#else   /* lint */
-
 /*
  * flush_instr_mem:
  *      Flush 1 page of the I-$ starting at vaddr
  *      %o0 vaddr
  *      %o1 bytes to be flushed

@@ -561,28 +413,18 @@
         flush   %o0                     ! address irrelevant
         retl
         nop
         SET_SIZE(flush_instr_mem)
 
-#endif  /* lint */
 
-
 /*
  * flush_ecache:
  *      %o0 - 64 bit physical address
  *      %o1 - ecache size
  *      %o2 - ecache linesize
  */
-#if defined(lint)
 
-/*ARGSUSED*/
-void
-flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize)
-{}
-
-#else /* !lint */
-
         ENTRY(flush_ecache)
 
         /*
          * Flush the entire Ecache.
          */

@@ -589,33 +431,18 @@
         ECACHE_FLUSHALL(%o1, %o2, %o0, %o4)
         retl
         nop
         SET_SIZE(flush_ecache)
 
-#endif /* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-kdi_flush_idcache(int dcache_size, int dcache_lsize, int icache_size,
-    int icache_lsize)
-{
-}
-
-#else   /* lint */
-
         /*
          * I/D cache flushing is not needed for OPL processors
          */
         ENTRY(kdi_flush_idcache)
         retl
         nop
         SET_SIZE(kdi_flush_idcache)
 
-#endif  /* lint */
-
 #ifdef  TRAPTRACE
 /*
  * Simplified trap trace macro for OPL. Adapted from us3.
  */
 #define OPL_TRAPTRACE(ptr, scr1, scr2, label)                   \

@@ -999,11 +826,10 @@
  * spill/fill that depends on context info for correct behaviour.
  * Note that the TLBs must be flushed before programming the context
  * registers.
  */
 
-#if !defined(lint)
 #define RESET_MMU_REGS(tmp1, tmp2, tmp3)                        \
         FLUSH_ALL_TLB(tmp1)                                     ;\
         set     MMU_PCONTEXT, tmp1                              ;\
         sethi   %hi(kcontextreg), tmp2                          ;\
         ldx     [tmp2 + %lo(kcontextreg)], tmp2                 ;\

@@ -1021,19 +847,17 @@
 #define RESET_TSB_TAGPTR(tmp)                                   \
         set     MMU_TAG_ACCESS, tmp                             ;\
         stxa    %g0, [tmp]ASI_IMMU                              ;\
         stxa    %g0, [tmp]ASI_DMMU                              ;\
         membar  #Sync
-#endif /* lint */
 
 /*
  * In case of errors in the MMU_TSB_PREFETCH registers we have to
  * reset them. We can use "0" as the reset value, this way we set
  * the "V" bit of the registers to 0, which will disable the prefetch
  * so the values of the other fields are irrelevant.
  */
-#if !defined(lint)
 #define RESET_TSB_PREFETCH(tmp)                 \
         set     VA_UTSBPREF_8K, tmp             ;\
         stxa    %g0, [tmp]ASI_ITSB_PREFETCH     ;\
         set     VA_UTSBPREF_4M, tmp             ;\
         stxa    %g0, [tmp]ASI_ITSB_PREFETCH     ;\

@@ -1047,23 +871,20 @@
         stxa    %g0, [tmp]ASI_DTSB_PREFETCH     ;\
         set     VA_KTSBPREF_8K, tmp             ;\
         stxa    %g0, [tmp]ASI_DTSB_PREFETCH     ;\
         set     VA_KTSBPREF_4M, tmp             ;\
         stxa    %g0, [tmp]ASI_DTSB_PREFETCH
-#endif /* lint */
 
 /*
  * In case of errors in the MMU_SHARED_CONTEXT register we have to
  * reset its value. We can use "0" as the reset value, it will put
  * 0 in the IV field disabling the shared context support, and
  * making values of all the other fields of the register irrelevant.
  */
-#if !defined(lint)
 #define RESET_SHARED_CTXT(tmp)                  \
         set     MMU_SHARED_CONTEXT, tmp         ;\
         stxa    %g0, [tmp]ASI_DMMU
-#endif /* lint */
 
 /*
  * RESET_TO_PRIV()
  *
  * In many cases, we need to force the thread into privilege mode because

@@ -1123,18 +944,10 @@
         or      tmp, tmp1, tmp                                  ;\
         wrpr    tmp, %g0, %tstate                               ;\
         wrpr    %g0, %tpc
 
 
-#if defined(lint)
-
-void
-ce_err(void)
-{}
-
-#else   /* lint */
-
 /*
  * We normally don't expect CE traps since we disable the
  * 0x63 trap reporting at the start of day. There is a
  * small window before we disable them, so let check for
  * it. Otherwise, panic.

@@ -1158,21 +971,11 @@
         sethi   %hi(sys_trap), %g5
         jmp     %g5 + %lo(sys_trap)
         sub     %g0, 1, %g4
         SET_SIZE(ce_err)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-void
-ce_err_tl1(void)
-{}
-
-#else   /* lint */
-
 /*
  * We don't use trap for CE detection.
  */
         ENTRY_NP(ce_err_tl1)
         set     trap, %g1

@@ -1180,21 +983,11 @@
         sethi   %hi(sys_trap), %g5
         jmp     %g5 + %lo(sys_trap)
         sub     %g0, 1, %g4
         SET_SIZE(ce_err_tl1)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-
-void
-async_err(void)
-{}
-
-#else   /* lint */
-
 /*
  * async_err is the default handler for IAE/DAE traps.
  * For OPL, we patch in the right handler at start of day.
  * But if a IAE/DAE trap get generated before the handler
  * is patched, panic.

@@ -1205,18 +998,10 @@
         sethi   %hi(sys_trap), %g5
         jmp     %g5 + %lo(sys_trap)
         sub     %g0, 1, %g4
         SET_SIZE(async_err)
 
-#endif  /* lint */
-
-#if defined(lint)
-void
-opl_sync_trap(void)
-{}
-#else   /* lint */
-
         .seg    ".data"
         .global opl_clr_freg
         .global opl_cpu0_err_log
 
         .align  16

@@ -1399,17 +1184,11 @@
 6:
         sethi   %hi(sys_trap), %g5
         jmp     %g5 + %lo(sys_trap)
          mov    PIL_15, %g4
         SET_SIZE(opl_sync_trap)
-#endif  /* lint */
 
-#if defined(lint)
-void
-opl_uger_trap(void)
-{}
-#else   /* lint */
 /*
  * Common Urgent error trap handler (tt=0x40)
  * All TL=0 and TL>0 0x40 traps vector to this handler.
  * The error handling can be best summarized as follows:
  * 1. Read the Urgent error status register (UGERSR)

@@ -1620,20 +1399,11 @@
         set     opl_cpu_urgent_error, %g1       ! pc
         sethi   %hi(sys_trap), %g5
         jmp     %g5 + %lo(sys_trap)
          mov    PIL_15, %g4
         SET_SIZE(opl_uger_trap)
-#endif  /* lint */
 
-#if defined(lint)
-void
-opl_ta3_trap(void)
-{}
-void
-opl_cleanw_subr(void)
-{}
-#else   /* lint */
 /*
  * OPL ta3 support (note please, that win_reg
  * area size for each cpu is 2^7 bytes)
  */
 

@@ -1725,19 +1495,11 @@
         restored
         restore
         jmp     %g7
           nop
         SET_SIZE(opl_cleanw_subr)
-#endif  /* lint */
 
-#if defined(lint)
-
-void
-opl_serr_instr(void)
-{}
-
-#else   /* lint */
 /*
  * The actual trap handler for tt=0x0a, and tt=0x32
  */
         ENTRY_NP(opl_serr_instr)
         OPL_SAVE_GLOBAL(%g1,%g2,%g3)

@@ -1745,19 +1507,10 @@
         jmp     %g3 + %lo(opl_sync_trap)
          rdpr    %tt, %g1
         .align  32
         SET_SIZE(opl_serr_instr)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-void
-opl_ugerr_instr(void)
-{}
-
-#else   /* lint */
 /*
  * The actual trap handler for tt=0x40
  */
         ENTRY_NP(opl_ugerr_instr)
         sethi   %hi(opl_uger_trap), %g3

@@ -1764,19 +1517,10 @@
         jmp     %g3 + %lo(opl_uger_trap)
          nop
         .align  32
         SET_SIZE(opl_ugerr_instr)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-void
-opl_ta3_instr(void)
-{}
-
-#else   /* lint */
 /*
  * The actual trap handler for tt=0x103 (flushw)
  */
         ENTRY_NP(opl_ta3_instr)
         sethi   %hi(opl_ta3_trap), %g3

@@ -1783,19 +1527,10 @@
         jmp     %g3 + %lo(opl_ta3_trap)
          nop
         .align  32
         SET_SIZE(opl_ta3_instr)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-void
-opl_ta4_instr(void)
-{}
-
-#else   /* lint */
 /*
  * The patch for the .clean_windows code
  */
         ENTRY_NP(opl_ta4_instr)
         sethi   %hi(opl_cleanw_subr), %g3

@@ -1805,48 +1540,20 @@
         nop
         nop
         nop
         SET_SIZE(opl_ta4_instr)
 
-#endif  /* lint */
-
-#if defined(lint)
-/*
- *  Get timestamp (stick).
- */
-/* ARGSUSED */
-void
-stick_timestamp(int64_t *ts)
-{
-}
-
-#else   /* lint */
-
         ENTRY_NP(stick_timestamp)
         rd      STICK, %g1      ! read stick reg
         sllx    %g1, 1, %g1
         srlx    %g1, 1, %g1     ! clear npt bit
 
         retl
         stx     %g1, [%o0]      ! store the timestamp
         SET_SIZE(stick_timestamp)
 
-#endif  /* lint */
 
-
-#if defined(lint)
-/*
- * Set STICK adjusted by skew.
- */
-/* ARGSUSED */
-void
-stick_adj(int64_t skew)
-{
-}
-
-#else   /* lint */
-
         ENTRY_NP(stick_adj)
         rdpr    %pstate, %g1            ! save processor state
         andn    %g1, PSTATE_IE, %g3
         ba      1f                      ! cache align stick adj
         wrpr    %g0, %g3, %pstate       ! turn off interrupts

@@ -1860,43 +1567,17 @@
 
         retl
         wrpr    %g1, %pstate            ! restore processor state
         SET_SIZE(stick_adj)
 
-#endif  /* lint */
-
-#if defined(lint)
-/*
- * Debugger-specific stick retrieval
- */
-/*ARGSUSED*/
-int
-kdi_get_stick(uint64_t *stickp)
-{
-        return (0);
-}
-
-#else   /* lint */
-
         ENTRY_NP(kdi_get_stick)
         rd      STICK, %g1
         stx     %g1, [%o0]
         retl
         mov     %g0, %o0
         SET_SIZE(kdi_get_stick)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-/*ARGSUSED*/
-int
-dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain)
-{ return (0); }
-
-#else
-
         ENTRY(dtrace_blksuword32)
         save    %sp, -SA(MINFRAME + 4), %sp
 
         rdpr    %pstate, %l1
         andn    %l1, PSTATE_IE, %l2             ! disable interrupts to

@@ -1957,36 +1638,19 @@
 1:
         call    dtrace_blksuword32_err
         restore
 
         SET_SIZE(dtrace_blksuword32)
-#endif /* lint */
 
-#if defined(lint)
-/*ARGSUSED*/
-void
-ras_cntr_reset(void *arg)
-{
-}
-#else
         ENTRY_NP(ras_cntr_reset)
         set     OPL_SCRATCHPAD_ERRLOG, %o1
         ldxa    [%o1]ASI_SCRATCHPAD, %o0
         or      %o0, ERRLOG_REG_NUMERR_MASK, %o0
         retl
          stxa   %o0, [%o1]ASI_SCRATCHPAD
         SET_SIZE(ras_cntr_reset)
-#endif /* lint */
 
-#if defined(lint)
-/* ARGSUSED */
-void
-opl_error_setup(uint64_t cpu_err_log_pa)
-{
-}
-
-#else   /* lint */
         ENTRY_NP(opl_error_setup)
         /*
          * Initialize the error log scratchpad register
          */
         ldxa    [%g0]ASI_EIDR, %o2

@@ -2005,19 +1669,11 @@
         ldxa    [%o1]ASI_AFSR, %o0
         andn    %o0, ASI_ECR_RTE_UE|ASI_ECR_RTE_CEDG, %o0
         retl
           stxa  %o0, [%o1]ASI_AFSR
         SET_SIZE(opl_error_setup)
-#endif /* lint */
 
-#if defined(lint)
-/* ARGSUSED */
-void
-cpu_early_feature_init(void)
-{
-}
-#else   /* lint */
         ENTRY_NP(cpu_early_feature_init)
         /*
          * Enable MMU translating multiple page sizes for
          * sITLB and sDTLB.
          */

@@ -2033,22 +1689,11 @@
         stxa    %g0, [%o0]ASI_DTLB_DEMAP
         stxa    %g0, [%o0]ASI_ITLB_DEMAP
         retl
           flush %o1
         SET_SIZE(cpu_early_feature_init)
-#endif /* lint */
 
-#if     defined(lint)
-/*
- * This function is called for each (enabled) CPU. We use it to
- * initialize error handling related registers.
- */
-/*ARGSUSED*/
-void
-cpu_feature_init(void)
-{}
-#else   /* lint */
         ENTRY(cpu_feature_init)
         !
         ! get the device_id and store the device_id
         ! in the appropriate cpunodes structure
         ! given the cpus index

@@ -2062,19 +1707,11 @@
         ! initialize CPU registers
         !
         ba      opl_cpu_reg_init
         nop
         SET_SIZE(cpu_feature_init)
-#endif  /* lint */
 
-#if defined(lint)
-
-void
-cpu_cleartickpnt(void)
-{}
-
-#else   /* lint */
         /*
          * Clear the NPT (non-privileged trap) bit in the %tick/%stick
          * registers. In an effort to make the change in the
          * tick/stick counter as consistent as possible, we disable
          * all interrupts while we're changing the registers. We also

@@ -2110,24 +1747,10 @@
         jmp     %g4 + 4
         wrpr    %g0, %g1, %pstate       /* restore processor state */
 
         SET_SIZE(cpu_clearticknpt)
 
-#endif  /* lint */
-
-#if defined(lint)
-
-void
-cpu_halt_cpu(void)
-{}
-
-void
-cpu_smt_pause(void)
-{}
-
-#else   /* lint */
-
         /*
          * Halt the current strand with the suspend instruction.
          * The compiler/asm currently does not support this suspend
          * instruction mnemonic, use byte code for now.
          */

@@ -2146,6 +1769,5 @@
         .word   0x81b01060
         retl
         nop
         SET_SIZE(cpu_smt_pause)
 
-#endif  /* lint */