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--- old/usr/src/uts/sun4u/cpu/common_asm.s
+++ new/usr/src/uts/sun4u/cpu/common_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
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15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 -#if !defined(lint)
26 25 #include "assym.h"
27 -#endif /* !lint */
28 26
29 27 /*
30 28 * General assembly language routines.
31 29 * It is the intent of this file to contain routines that are
32 30 * specific to cpu architecture.
33 31 */
34 32
35 33 /*
36 34 * WARNING: If you add a fast trap handler which can be invoked by a
37 35 * non-privileged user, you may have to use the FAST_TRAP_DONE macro
38 36 * instead of "done" instruction to return back to the user mode. See
39 37 * comments for the "fast_trap_done" entry point for more information.
40 38 */
41 39 #define FAST_TRAP_DONE \
42 40 ba,a fast_trap_done
43 41
44 42 /*
45 43 * Override GET_NATIVE_TIME for the cpu module code. This is not
46 44 * guaranteed to be exactly one instruction, be careful of using
47 45 * the macro in delay slots.
48 46 *
49 47 * Do not use any instruction that modifies condition codes as the
50 48 * caller may depend on these to remain unchanged across the macro.
51 49 */
52 50 #if defined(CHEETAH) || defined(OLYMPUS_C)
53 51
54 52 #define GET_NATIVE_TIME(out, scr1, scr2) \
55 53 rd STICK, out
56 54 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \
57 55 rd STICK, reg; \
58 56 add reg, delta, reg; \
59 57 wr reg, STICK
60 58 #define RD_TICKCMPR(out, scr) \
61 59 rd STICK_COMPARE, out
62 60 #define WR_TICKCMPR(in, scr1, scr2, label) \
63 61 wr in, STICK_COMPARE
64 62
65 63 #elif defined(HUMMINGBIRD)
66 64 #include <sys/spitregs.h>
67 65
68 66 /*
69 67 * the current hummingbird version of %stick and %stick_cmp
70 68 * were both implemented as (2) 32-bit locations in ASI_IO space;
71 69 * the hdwr should support atomic r/w; meanwhile: ugly alert! ...
72 70 *
73 71 * 64-bit opcodes are required, but move only 32-bits:
74 72 *
75 73 * ldxa [phys]ASI_IO, %dst reads the low 32-bits from phys into %dst
76 74 * stxa %src, [phys]ASI_IO writes the low 32-bits from %src into phys
77 75 *
78 76 * reg equivalent [phys]ASI_IO
79 77 * ------------------ ---------------
80 78 * %stick_cmp low-32 0x1FE.0000.F060
81 79 * %stick_cmp high-32 0x1FE.0000.F068
82 80 * %stick low-32 0x1FE.0000.F070
83 81 * %stick high-32 0x1FE.0000.F078
84 82 */
85 83 #define HSTC_LOW 0x60 /* stick_cmp low 32-bits */
86 84 #define HSTC_HIGH 0x68 /* stick_cmp high 32-bits */
87 85 #define HST_LOW 0x70 /* stick low 32-bits */
88 86 #define HST_HIGH 0x78 /* stick high 32-bits */
89 87 #define HST_DIFF 0x08 /* low<-->high diff */
90 88
91 89 /*
92 90 * Any change in the number of instructions in SETL41()
93 91 * will affect SETL41_OFF
94 92 */
95 93 #define SETL41(reg, byte) \
96 94 sethi %hi(0x1FE00000), reg; /* 0000.0000.1FE0.0000 */ \
97 95 or reg, 0xF, reg; /* 0000.0000.1FE0.000F */ \
98 96 sllx reg, 12, reg; /* 0000.01FE.0000.F000 */ \
99 97 or reg, byte, reg; /* 0000.01FE.0000.F0xx */
100 98
101 99 /*
102 100 * SETL41_OFF is used to calulate the relative PC value when a
103 101 * branch instruction needs to go over SETL41() macro
104 102 */
105 103 #define SETL41_OFF 16
106 104
107 105 /*
108 106 * reading stick requires 2 loads, and there could be an intervening
109 107 * low-to-high 32-bit rollover resulting in a return value that is
110 108 * off by about (2 ^ 32); this rare case is prevented by re-reading
111 109 * the low-32 bits after the high-32 and verifying the "after" value
112 110 * is >= the "before" value; if not, increment the high-32 value.
113 111 *
114 112 * this method is limited to 1 rollover, and based on the fixed
115 113 * stick-frequency (5555555), requires the loads to complete within
116 114 * 773 seconds; incrementing the high-32 value will not overflow for
117 115 * about 52644 years.
118 116 *
119 117 * writing stick requires 2 stores; if the old/new low-32 value is
120 118 * near 0xffffffff, there could be another rollover (also rare).
121 119 * to prevent this, we first write a 0 to the low-32, then write
122 120 * new values to the high-32 then the low-32.
123 121 *
124 122 * When we detect a carry in the lower %stick register, we need to
125 123 * read HST_HIGH again. However at the point where we detect this,
126 124 * we need to rebuild the register address HST_HIGH.This involves more
127 125 * than one instructions and a branch is unavoidable. However, most of
128 126 * the time, there is no carry. So we take the penalty of a branch
129 127 * instruction only when there is carry (less frequent).
130 128 *
131 129 * For GET_NATIVE_TIME(), we start afresh and branch to SETL41().
132 130 * For DELTA_NATIVE_TIME(), we branch to just after SETL41() since
133 131 * addr already points to HST_LOW.
134 132 *
135 133 * NOTE: this method requires disabling interrupts before using
136 134 * DELTA_NATIVE_TIME.
137 135 */
138 136 #define GET_NATIVE_TIME(out, scr, tmp) \
139 137 SETL41(scr, HST_LOW); \
140 138 ldxa [scr]ASI_IO, tmp; \
141 139 inc HST_DIFF, scr; \
142 140 ldxa [scr]ASI_IO, out; \
143 141 dec HST_DIFF, scr; \
144 142 ldxa [scr]ASI_IO, scr; \
145 143 sub scr, tmp, tmp; \
146 144 brlz,pn tmp, .-(SETL41_OFF+24); \
147 145 sllx out, 32, out; \
148 146 or out, scr, out
149 147 #define DELTA_NATIVE_TIME(delta, addr, high, low, tmp) \
150 148 SETL41(addr, HST_LOW); \
151 149 ldxa [addr]ASI_IO, tmp; \
152 150 inc HST_DIFF, addr; \
153 151 ldxa [addr]ASI_IO, high; \
154 152 dec HST_DIFF, addr; \
155 153 ldxa [addr]ASI_IO, low; \
156 154 sub low, tmp, tmp; \
157 155 brlz,pn tmp, .-24; \
158 156 sllx high, 32, high; \
159 157 or high, low, high; \
160 158 add high, delta, high; \
161 159 srl high, 0, low; \
162 160 srlx high, 32, high; \
163 161 stxa %g0, [addr]ASI_IO; \
164 162 inc HST_DIFF, addr; \
165 163 stxa high, [addr]ASI_IO; \
166 164 dec HST_DIFF, addr; \
167 165 stxa low, [addr]ASI_IO
168 166 #define RD_TICKCMPR(out, scr) \
169 167 SETL41(scr, HSTC_LOW); \
170 168 ldxa [scr]ASI_IO, out; \
171 169 inc HST_DIFF, scr; \
172 170 ldxa [scr]ASI_IO, scr; \
173 171 sllx scr, 32, scr; \
174 172 or scr, out, out
175 173 #define WR_TICKCMPR(in, scra, scrd, label) \
176 174 SETL41(scra, HSTC_HIGH); \
177 175 srlx in, 32, scrd; \
178 176 stxa scrd, [scra]ASI_IO; \
179 177 dec HST_DIFF, scra; \
180 178 stxa in, [scra]ASI_IO
181 179
182 180 #else /* !CHEETAH && !HUMMINGBIRD */
183 181
184 182 #define GET_NATIVE_TIME(out, scr1, scr2) \
185 183 rdpr %tick, out
186 184 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \
187 185 rdpr %tick, reg; \
188 186 add reg, delta, reg; \
189 187 wrpr reg, %tick
190 188 #define RD_TICKCMPR(out, scr) \
191 189 rd TICK_COMPARE, out
192 190 #ifdef BB_ERRATA_1 /* writes to TICK_COMPARE may fail */
193 191 /*
194 192 * Writes to the TICK_COMPARE register sometimes fail on blackbird modules.
195 193 * The failure occurs only when the following instruction decodes to wr or
196 194 * wrpr. The workaround is to immediately follow writes to TICK_COMPARE
197 195 * with a read, thus stalling the pipe and keeping following instructions
198 196 * from causing data corruption. Aligning to a quadword will ensure these
199 197 * two instructions are not split due to i$ misses.
200 198 */
201 199 #define WR_TICKCMPR(cmpr,scr1,scr2,label) \
202 200 ba,a .bb_errata_1.label ;\
203 201 .align 64 ;\
204 202 .bb_errata_1.label: ;\
205 203 wr cmpr, TICK_COMPARE ;\
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206 204 rd TICK_COMPARE, %g0
207 205 #else /* BB_ERRATA_1 */
208 206 #define WR_TICKCMPR(in,scr1,scr2,label) \
209 207 wr in, TICK_COMPARE
210 208 #endif /* BB_ERRATA_1 */
211 209
212 210 #endif /* !CHEETAH && !HUMMINGBIRD */
213 211
214 212 #include <sys/clock.h>
215 213
216 -#if defined(lint)
217 -#include <sys/types.h>
218 -#include <sys/scb.h>
219 -#include <sys/systm.h>
220 -#include <sys/regset.h>
221 -#include <sys/sunddi.h>
222 -#include <sys/lockstat.h>
223 -#endif /* lint */
224 214
225 -
226 215 #include <sys/asm_linkage.h>
227 216 #include <sys/privregs.h>
228 217 #include <sys/machparam.h> /* To get SYSBASE and PAGESIZE */
229 218 #include <sys/machthread.h>
230 219 #include <sys/clock.h>
231 220 #include <sys/intreg.h>
232 221 #include <sys/psr_compat.h>
233 222 #include <sys/isa_defs.h>
234 223 #include <sys/dditypes.h>
235 224 #include <sys/intr.h>
236 225
237 -#if !defined(lint)
238 226 #include "assym.h"
239 -#endif /* !lint */
240 227
241 -#if defined(lint)
242 -
243 -uint_t
244 -get_impl(void)
245 -{ return (0); }
246 -
247 -#else /* lint */
248 -
249 228 ENTRY(get_impl)
250 229 GET_CPU_IMPL(%o0)
251 230 retl
252 231 nop
253 232 SET_SIZE(get_impl)
254 233
255 -#endif /* lint */
256 -
257 -#if defined(lint)
258 -/*
259 - * Softint generated when counter field of tick reg matches value field
260 - * of tick_cmpr reg
261 - */
262 -/*ARGSUSED*/
263 -void
264 -tickcmpr_set(uint64_t clock_cycles)
265 -{}
266 -
267 -#else /* lint */
268 -
269 234 ENTRY_NP(tickcmpr_set)
270 235 ! get 64-bit clock_cycles interval
271 236 mov %o0, %o2
272 237 mov 8, %o3 ! A reasonable initial step size
273 238 1:
274 239 WR_TICKCMPR(%o2,%o4,%o5,__LINE__) ! Write to TICK_CMPR
275 240
276 241 GET_NATIVE_TIME(%o0, %o4, %o5) ! Read %tick to confirm the
277 242 sllx %o0, 1, %o0 ! value we wrote was in the future.
278 243 srlx %o0, 1, %o0
279 244
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280 245 cmp %o2, %o0 ! If the value we wrote was in the
281 246 bg,pt %xcc, 2f ! future, then blow out of here.
282 247 sllx %o3, 1, %o3 ! If not, then double our step size,
283 248 ba,pt %xcc, 1b ! and take another lap.
284 249 add %o0, %o3, %o2 !
285 250 2:
286 251 retl
287 252 nop
288 253 SET_SIZE(tickcmpr_set)
289 254
290 -#endif /* lint */
291 -
292 -#if defined(lint)
293 -
294 -void
295 -tickcmpr_disable(void)
296 -{}
297 -
298 -#else /* lint */
299 -
300 255 ENTRY_NP(tickcmpr_disable)
301 256 mov 1, %g1
302 257 sllx %g1, TICKINT_DIS_SHFT, %o0
303 258 WR_TICKCMPR(%o0,%o4,%o5,__LINE__) ! Write to TICK_CMPR
304 259 retl
305 260 nop
306 261 SET_SIZE(tickcmpr_disable)
307 262
308 -#endif /* lint */
309 -
310 -#if defined(lint)
311 -
312 -/*
313 - * tick_write_delta() increments %tick by the specified delta. This should
314 - * only be called after a CPR event to assure that gethrtime() continues to
315 - * increase monotonically. Obviously, writing %tick needs to de done very
316 - * carefully to avoid introducing unnecessary %tick skew across CPUs. For
317 - * this reason, we make sure we're i-cache hot before actually writing to
318 - * %tick.
319 - */
320 -/*ARGSUSED*/
321 -void
322 -tick_write_delta(uint64_t delta)
323 -{}
324 -
325 -#else /* lint */
326 -
327 263 #ifdef DEBUG
328 264 .seg ".text"
329 265 tick_write_panic:
330 266 .asciz "tick_write_delta: interrupts already disabled on entry"
331 267 #endif /* DEBUG */
332 268
333 269 ENTRY_NP(tick_write_delta)
334 270 rdpr %pstate, %g1
335 271 #ifdef DEBUG
336 272 andcc %g1, PSTATE_IE, %g0 ! If DEBUG, check that interrupts
337 273 bnz 0f ! aren't already disabled.
338 274 sethi %hi(tick_write_panic), %o1
339 275 save %sp, -SA(MINFRAME), %sp ! get a new window to preserve caller
340 276 call panic
341 277 or %i1, %lo(tick_write_panic), %o0
342 278 #endif /* DEBUG */
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343 279 0: wrpr %g1, PSTATE_IE, %pstate ! Disable interrupts
344 280 mov %o0, %o2
345 281 ba 0f ! Branch to cache line-aligned instr.
346 282 nop
347 283 .align 16
348 284 0: nop ! The next 3 instructions are now hot.
349 285 DELTA_NATIVE_TIME(%o2, %o3, %o4, %o5, %g2) ! read/inc/write %tick
350 286
351 287 retl ! Return
352 288 wrpr %g0, %g1, %pstate ! delay: Re-enable interrupts
353 -#endif /* lint */
354 289
355 -#if defined(lint)
356 -/*
357 - * return 1 if disabled
358 - */
359 -
360 -int
361 -tickcmpr_disabled(void)
362 -{ return (0); }
363 -
364 -#else /* lint */
365 -
366 290 ENTRY_NP(tickcmpr_disabled)
367 291 RD_TICKCMPR(%g1, %o0)
368 292 retl
369 293 srlx %g1, TICKINT_DIS_SHFT, %o0
370 294 SET_SIZE(tickcmpr_disabled)
371 295
372 -#endif /* lint */
373 -
374 296 /*
375 297 * Get current tick
376 298 */
377 -#if defined(lint)
378 299
379 -u_longlong_t
380 -gettick(void)
381 -{ return (0); }
382 -
383 -u_longlong_t
384 -randtick(void)
385 -{ return (0); }
386 -
387 -#else /* lint */
388 -
389 300 ENTRY(gettick)
390 301 ALTENTRY(randtick)
391 302 GET_NATIVE_TIME(%o0, %o2, %o3)
392 303 retl
393 304 nop
394 305 SET_SIZE(randtick)
395 306 SET_SIZE(gettick)
396 307
397 -#endif /* lint */
398 308
399 -
400 309 /*
401 310 * Return the counter portion of the tick register.
402 311 */
403 312
404 -#if defined(lint)
405 -
406 -uint64_t
407 -gettick_counter(void)
408 -{ return(0); }
409 -
410 -#else /* lint */
411 -
412 313 ENTRY_NP(gettick_counter)
413 314 rdpr %tick, %o0
414 315 sllx %o0, 1, %o0
415 316 retl
416 317 srlx %o0, 1, %o0 ! shake off npt bit
417 318 SET_SIZE(gettick_counter)
418 -#endif /* lint */
419 319
420 320 /*
421 321 * Provide a C callable interface to the trap that reads the hi-res timer.
422 322 * Returns 64-bit nanosecond timestamp in %o0 and %o1.
423 323 */
424 324
425 -#if defined(lint)
426 -
427 -hrtime_t
428 -gethrtime(void)
429 -{
430 - return ((hrtime_t)0);
431 -}
432 -
433 -hrtime_t
434 -gethrtime_unscaled(void)
435 -{
436 - return ((hrtime_t)0);
437 -}
438 -
439 -hrtime_t
440 -gethrtime_max(void)
441 -{
442 - return ((hrtime_t)0);
443 -}
444 -
445 -void
446 -scalehrtime(hrtime_t *hrt)
447 -{
448 - *hrt = 0;
449 -}
450 -
451 -void
452 -gethrestime(timespec_t *tp)
453 -{
454 - tp->tv_sec = 0;
455 - tp->tv_nsec = 0;
456 -}
457 -
458 -time_t
459 -gethrestime_sec(void)
460 -{
461 - return (0);
462 -}
463 -
464 -void
465 -gethrestime_lasttick(timespec_t *tp)
466 -{
467 - tp->tv_sec = 0;
468 - tp->tv_nsec = 0;
469 -}
470 -
471 -/*ARGSUSED*/
472 -void
473 -hres_tick(void)
474 -{
475 -}
476 -
477 -void
478 -panic_hres_tick(void)
479 -{
480 -}
481 -
482 -#else /* lint */
483 -
484 325 ENTRY_NP(gethrtime)
485 326 GET_HRTIME(%g1, %o0, %o1, %o2, %o3, %o4, %o5, %g2)
486 327 ! %g1 = hrtime
487 328 retl
488 329 mov %g1, %o0
489 330 SET_SIZE(gethrtime)
490 331
491 332 ENTRY_NP(gethrtime_unscaled)
492 333 GET_NATIVE_TIME(%g1, %o2, %o3) ! %g1 = native time
493 334 retl
494 335 mov %g1, %o0
495 336 SET_SIZE(gethrtime_unscaled)
496 337
497 338 ENTRY_NP(gethrtime_waitfree)
498 339 ALTENTRY(dtrace_gethrtime)
499 340 GET_NATIVE_TIME(%g1, %o2, %o3) ! %g1 = native time
500 341 NATIVE_TIME_TO_NSEC(%g1, %o2, %o3)
501 342 retl
502 343 mov %g1, %o0
503 344 SET_SIZE(dtrace_gethrtime)
504 345 SET_SIZE(gethrtime_waitfree)
505 346
506 347 ENTRY(gethrtime_max)
507 348 NATIVE_TIME_MAX(%g1)
508 349 NATIVE_TIME_TO_NSEC(%g1, %o0, %o1)
509 350
510 351 ! hrtime_t's are signed, max hrtime_t must be positive
511 352 mov -1, %o2
512 353 brlz,a %g1, 1f
513 354 srlx %o2, 1, %g1
514 355 1:
515 356 retl
516 357 mov %g1, %o0
517 358 SET_SIZE(gethrtime_max)
518 359
519 360 ENTRY(scalehrtime)
520 361 ldx [%o0], %o1
521 362 NATIVE_TIME_TO_NSEC(%o1, %o2, %o3)
522 363 retl
523 364 stx %o1, [%o0]
524 365 SET_SIZE(scalehrtime)
525 366
526 367 /*
527 368 * Fast trap to return a timestamp, uses trap window, leaves traps
528 369 * disabled. Returns a 64-bit nanosecond timestamp in %o0 and %o1.
529 370 *
530 371 * This is the handler for the ST_GETHRTIME trap.
531 372 */
532 373
533 374 ENTRY_NP(get_timestamp)
534 375 GET_HRTIME(%g1, %g2, %g3, %g4, %g5, %o0, %o1, %o2) ! %g1 = hrtime
535 376 srlx %g1, 32, %o0 ! %o0 = hi32(%g1)
536 377 srl %g1, 0, %o1 ! %o1 = lo32(%g1)
537 378 FAST_TRAP_DONE
538 379 SET_SIZE(get_timestamp)
539 380
540 381 /*
541 382 * Macro to convert GET_HRESTIME() bits into a timestamp.
542 383 *
543 384 * We use two separate macros so that the platform-dependent GET_HRESTIME()
544 385 * can be as small as possible; CONV_HRESTIME() implements the generic part.
545 386 */
546 387 #define CONV_HRESTIME(hrestsec, hrestnsec, adj, nslt, nano) \
547 388 brz,pt adj, 3f; /* no adjustments, it's easy */ \
548 389 add hrestnsec, nslt, hrestnsec; /* hrest.tv_nsec += nslt */ \
549 390 brlz,pn adj, 2f; /* if hrestime_adj negative */ \
550 391 srlx nslt, ADJ_SHIFT, nslt; /* delay: nslt >>= 4 */ \
551 392 subcc adj, nslt, %g0; /* hrestime_adj - nslt/16 */ \
552 393 movg %xcc, nslt, adj; /* adj by min(adj, nslt/16) */ \
553 394 ba 3f; /* go convert to sec/nsec */ \
554 395 add hrestnsec, adj, hrestnsec; /* delay: apply adjustment */ \
555 396 2: addcc adj, nslt, %g0; /* hrestime_adj + nslt/16 */ \
556 397 bge,a,pt %xcc, 3f; /* is adj less negative? */ \
557 398 add hrestnsec, adj, hrestnsec; /* yes: hrest.nsec += adj */ \
558 399 sub hrestnsec, nslt, hrestnsec; /* no: hrest.nsec -= nslt/16 */ \
559 400 3: cmp hrestnsec, nano; /* more than a billion? */ \
560 401 bl,pt %xcc, 4f; /* if not, we're done */ \
561 402 nop; /* delay: do nothing :( */ \
562 403 add hrestsec, 1, hrestsec; /* hrest.tv_sec++; */ \
563 404 sub hrestnsec, nano, hrestnsec; /* hrest.tv_nsec -= NANOSEC; */ \
564 405 ba,a 3b; /* check >= billion again */ \
565 406 4:
566 407
567 408 ENTRY_NP(gethrestime)
568 409 GET_HRESTIME(%o1, %o2, %o3, %o4, %o5, %g1, %g2, %g3, %g4)
569 410 CONV_HRESTIME(%o1, %o2, %o3, %o4, %o5)
570 411 stn %o1, [%o0]
571 412 retl
572 413 stn %o2, [%o0 + CLONGSIZE]
573 414 SET_SIZE(gethrestime)
574 415
575 416 /*
576 417 * Similar to gethrestime(), but gethrestime_sec() returns current hrestime
577 418 * seconds.
578 419 */
579 420 ENTRY_NP(gethrestime_sec)
580 421 GET_HRESTIME(%o0, %o2, %o3, %o4, %o5, %g1, %g2, %g3, %g4)
581 422 CONV_HRESTIME(%o0, %o2, %o3, %o4, %o5)
582 423 retl ! %o0 current hrestime seconds
583 424 nop
584 425 SET_SIZE(gethrestime_sec)
585 426
586 427 /*
587 428 * Returns the hrestime on the last tick. This is simpler than gethrestime()
588 429 * and gethrestime_sec(): no conversion is required. gethrestime_lasttick()
589 430 * follows the same locking algorithm as GET_HRESTIME and GET_HRTIME,
590 431 * outlined in detail in clock.h. (Unlike GET_HRESTIME/GET_HRTIME, we don't
591 432 * rely on load dependencies to effect the membar #LoadLoad, instead declaring
592 433 * it explicitly.)
593 434 */
594 435 ENTRY_NP(gethrestime_lasttick)
595 436 sethi %hi(hres_lock), %o1
596 437 0:
597 438 lduw [%o1 + %lo(hres_lock)], %o2 ! Load lock value
598 439 membar #LoadLoad ! Load of lock must complete
599 440 andn %o2, 1, %o2 ! Mask off lowest bit
600 441 ldn [%o1 + %lo(hrestime)], %g1 ! Seconds.
601 442 add %o1, %lo(hrestime), %o4
602 443 ldn [%o4 + CLONGSIZE], %g2 ! Nanoseconds.
603 444 membar #LoadLoad ! All loads must complete
604 445 lduw [%o1 + %lo(hres_lock)], %o3 ! Reload lock value
605 446 cmp %o3, %o2 ! If lock is locked or has
606 447 bne 0b ! changed, retry.
607 448 stn %g1, [%o0] ! Delay: store seconds
608 449 retl
609 450 stn %g2, [%o0 + CLONGSIZE] ! Delay: store nanoseconds
610 451 SET_SIZE(gethrestime_lasttick)
611 452
612 453 /*
613 454 * Fast trap for gettimeofday(). Returns a timestruc_t in %o0 and %o1.
614 455 *
615 456 * This is the handler for the ST_GETHRESTIME trap.
616 457 */
617 458
618 459 ENTRY_NP(get_hrestime)
619 460 GET_HRESTIME(%o0, %o1, %g1, %g2, %g3, %g4, %g5, %o2, %o3)
620 461 CONV_HRESTIME(%o0, %o1, %g1, %g2, %g3)
621 462 FAST_TRAP_DONE
622 463 SET_SIZE(get_hrestime)
623 464
624 465 /*
625 466 * Fast trap to return lwp virtual time, uses trap window, leaves traps
626 467 * disabled. Returns a 64-bit number in %o0:%o1, which is the number
627 468 * of nanoseconds consumed.
628 469 *
629 470 * This is the handler for the ST_GETHRVTIME trap.
630 471 *
631 472 * Register usage:
632 473 * %o0, %o1 = return lwp virtual time
633 474 * %o2 = CPU/thread
634 475 * %o3 = lwp
635 476 * %g1 = scratch
636 477 * %g5 = scratch
637 478 */
638 479 ENTRY_NP(get_virtime)
639 480 GET_NATIVE_TIME(%g5, %g1, %g2) ! %g5 = native time in ticks
640 481 CPU_ADDR(%g2, %g3) ! CPU struct ptr to %g2
641 482 ldn [%g2 + CPU_THREAD], %g2 ! thread pointer to %g2
642 483 ldn [%g2 + T_LWP], %g3 ! lwp pointer to %g3
643 484
644 485 /*
645 486 * Subtract start time of current microstate from time
646 487 * of day to get increment for lwp virtual time.
647 488 */
648 489 ldx [%g3 + LWP_STATE_START], %g1 ! ms_state_start
649 490 sub %g5, %g1, %g5
650 491
651 492 /*
652 493 * Add current value of ms_acct[LMS_USER]
653 494 */
654 495 ldx [%g3 + LWP_ACCT_USER], %g1 ! ms_acct[LMS_USER]
655 496 add %g5, %g1, %g5
656 497 NATIVE_TIME_TO_NSEC(%g5, %g1, %o0)
657 498
658 499 srl %g5, 0, %o1 ! %o1 = lo32(%g5)
659 500 srlx %g5, 32, %o0 ! %o0 = hi32(%g5)
660 501
661 502 FAST_TRAP_DONE
662 503 SET_SIZE(get_virtime)
663 504
664 505
665 506
666 507 .seg ".text"
667 508 hrtime_base_panic:
668 509 .asciz "hrtime_base stepping back"
669 510
670 511
671 512 ENTRY_NP(hres_tick)
672 513 save %sp, -SA(MINFRAME), %sp ! get a new window
673 514
674 515 sethi %hi(hrestime), %l4
675 516 ldstub [%l4 + %lo(hres_lock + HRES_LOCK_OFFSET)], %l5 ! try locking
676 517 7: tst %l5
677 518 bz,pt %xcc, 8f ! if we got it, drive on
678 519 ld [%l4 + %lo(nsec_scale)], %l5 ! delay: %l5 = scaling factor
679 520 ldub [%l4 + %lo(hres_lock + HRES_LOCK_OFFSET)], %l5
680 521 9: tst %l5
681 522 bz,a,pn %xcc, 7b
682 523 ldstub [%l4 + %lo(hres_lock + HRES_LOCK_OFFSET)], %l5
683 524 ba,pt %xcc, 9b
684 525 ldub [%l4 + %lo(hres_lock + HRES_LOCK_OFFSET)], %l5
685 526 8:
686 527 membar #StoreLoad|#StoreStore
687 528
688 529 !
689 530 ! update hres_last_tick. %l5 has the scaling factor (nsec_scale).
690 531 !
691 532 ldx [%l4 + %lo(hrtime_base)], %g1 ! load current hrtime_base
692 533 GET_NATIVE_TIME(%l0, %l3, %l6) ! current native time
693 534 stx %l0, [%l4 + %lo(hres_last_tick)]! prev = current
694 535 ! convert native time to nsecs
695 536 NATIVE_TIME_TO_NSEC_SCALE(%l0, %l5, %l2, NSEC_SHIFT)
696 537
697 538 sub %l0, %g1, %i1 ! get accurate nsec delta
698 539
699 540 ldx [%l4 + %lo(hrtime_base)], %l1
700 541 cmp %l1, %l0
701 542 bg,pn %xcc, 9f
702 543 nop
703 544
704 545 stx %l0, [%l4 + %lo(hrtime_base)] ! update hrtime_base
705 546
706 547 !
707 548 ! apply adjustment, if any
708 549 !
709 550 ldx [%l4 + %lo(hrestime_adj)], %l0 ! %l0 = hrestime_adj
710 551 brz %l0, 2f
711 552 ! hrestime_adj == 0 ?
712 553 ! yes, skip adjustments
713 554 clr %l5 ! delay: set adj to zero
714 555 tst %l0 ! is hrestime_adj >= 0 ?
715 556 bge,pt %xcc, 1f ! yes, go handle positive case
716 557 srl %i1, ADJ_SHIFT, %l5 ! delay: %l5 = adj
717 558
718 559 addcc %l0, %l5, %g0 ! hrestime_adj < -adj ?
719 560 bl,pt %xcc, 2f ! yes, use current adj
720 561 neg %l5 ! delay: %l5 = -adj
721 562 ba,pt %xcc, 2f
722 563 mov %l0, %l5 ! no, so set adj = hrestime_adj
723 564 1:
724 565 subcc %l0, %l5, %g0 ! hrestime_adj < adj ?
725 566 bl,a,pt %xcc, 2f ! yes, set adj = hrestime_adj
726 567 mov %l0, %l5 ! delay: adj = hrestime_adj
727 568 2:
728 569 ldx [%l4 + %lo(timedelta)], %l0 ! %l0 = timedelta
729 570 sub %l0, %l5, %l0 ! timedelta -= adj
730 571
731 572 stx %l0, [%l4 + %lo(timedelta)] ! store new timedelta
732 573 stx %l0, [%l4 + %lo(hrestime_adj)] ! hrestime_adj = timedelta
733 574
734 575 or %l4, %lo(hrestime), %l2
735 576 ldn [%l2], %i2 ! %i2:%i3 = hrestime sec:nsec
736 577 ldn [%l2 + CLONGSIZE], %i3
737 578 add %i3, %l5, %i3 ! hrestime.nsec += adj
738 579 add %i3, %i1, %i3 ! hrestime.nsec += nslt
739 580
740 581 set NANOSEC, %l5 ! %l5 = NANOSEC
741 582 cmp %i3, %l5
742 583 bl,pt %xcc, 5f ! if hrestime.tv_nsec < NANOSEC
743 584 sethi %hi(one_sec), %i1 ! delay
744 585 add %i2, 0x1, %i2 ! hrestime.tv_sec++
745 586 sub %i3, %l5, %i3 ! hrestime.tv_nsec - NANOSEC
746 587 mov 0x1, %l5
747 588 st %l5, [%i1 + %lo(one_sec)]
748 589 5:
749 590 stn %i2, [%l2]
750 591 stn %i3, [%l2 + CLONGSIZE] ! store the new hrestime
751 592
752 593 membar #StoreStore
753 594
754 595 ld [%l4 + %lo(hres_lock)], %i1
755 596 inc %i1 ! release lock
756 597 st %i1, [%l4 + %lo(hres_lock)] ! clear hres_lock
757 598
758 599 ret
759 600 restore
760 601
761 602 9:
762 603 !
763 604 ! release hres_lock
764 605 !
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765 606 ld [%l4 + %lo(hres_lock)], %i1
766 607 inc %i1
767 608 st %i1, [%l4 + %lo(hres_lock)]
768 609
769 610 sethi %hi(hrtime_base_panic), %o0
770 611 call panic
771 612 or %o0, %lo(hrtime_base_panic), %o0
772 613
773 614 SET_SIZE(hres_tick)
774 615
775 -#endif /* lint */
776 -
777 -#if !defined(lint) && !defined(__lint)
778 -
779 616 .seg ".text"
780 617 kstat_q_panic_msg:
781 618 .asciz "kstat_q_exit: qlen == 0"
782 619
783 620 ENTRY(kstat_q_panic)
784 621 save %sp, -SA(MINFRAME), %sp
785 622 sethi %hi(kstat_q_panic_msg), %o0
786 623 call panic
787 624 or %o0, %lo(kstat_q_panic_msg), %o0
788 625 /*NOTREACHED*/
789 626 SET_SIZE(kstat_q_panic)
790 627
791 628 #define BRZPN brz,pn
792 629 #define BRZPT brz,pt
793 630
794 631 #define KSTAT_Q_UPDATE(QOP, QBR, QZERO, QRETURN, QTYPE) \
795 632 ld [%o0 + QTYPE/**/CNT], %o1; /* %o1 = old qlen */ \
796 633 QOP %o1, 1, %o2; /* %o2 = new qlen */ \
797 634 QBR %o1, QZERO; /* done if qlen == 0 */ \
798 635 st %o2, [%o0 + QTYPE/**/CNT]; /* delay: save qlen */ \
799 636 ldx [%o0 + QTYPE/**/LASTUPDATE], %o3; \
800 637 ldx [%o0 + QTYPE/**/TIME], %o4; /* %o4 = old time */ \
801 638 ldx [%o0 + QTYPE/**/LENTIME], %o5; /* %o5 = old lentime */ \
802 639 sub %g1, %o3, %o2; /* %o2 = time delta */ \
803 640 mulx %o1, %o2, %o3; /* %o3 = cur lentime */ \
804 641 add %o4, %o2, %o4; /* %o4 = new time */ \
805 642 add %o5, %o3, %o5; /* %o5 = new lentime */ \
806 643 stx %o4, [%o0 + QTYPE/**/TIME]; /* save time */ \
807 644 stx %o5, [%o0 + QTYPE/**/LENTIME]; /* save lentime */ \
808 645 QRETURN; \
809 646 stx %g1, [%o0 + QTYPE/**/LASTUPDATE]; /* lastupdate = now */
810 647
811 648 #if !defined(DEBUG)
812 649 /*
813 650 * same as KSTAT_Q_UPDATE but without:
814 651 * QBR %o1, QZERO;
815 652 * to be used only with non-debug build. mimics ASSERT() behaviour.
816 653 */
817 654 #define KSTAT_Q_UPDATE_ND(QOP, QRETURN, QTYPE) \
818 655 ld [%o0 + QTYPE/**/CNT], %o1; /* %o1 = old qlen */ \
819 656 QOP %o1, 1, %o2; /* %o2 = new qlen */ \
820 657 st %o2, [%o0 + QTYPE/**/CNT]; /* delay: save qlen */ \
821 658 ldx [%o0 + QTYPE/**/LASTUPDATE], %o3; \
822 659 ldx [%o0 + QTYPE/**/TIME], %o4; /* %o4 = old time */ \
823 660 ldx [%o0 + QTYPE/**/LENTIME], %o5; /* %o5 = old lentime */ \
824 661 sub %g1, %o3, %o2; /* %o2 = time delta */ \
825 662 mulx %o1, %o2, %o3; /* %o3 = cur lentime */ \
826 663 add %o4, %o2, %o4; /* %o4 = new time */ \
827 664 add %o5, %o3, %o5; /* %o5 = new lentime */ \
828 665 stx %o4, [%o0 + QTYPE/**/TIME]; /* save time */ \
829 666 stx %o5, [%o0 + QTYPE/**/LENTIME]; /* save lentime */ \
830 667 QRETURN; \
831 668 stx %g1, [%o0 + QTYPE/**/LASTUPDATE]; /* lastupdate = now */
832 669 #endif
833 670
834 671 .align 16
835 672 ENTRY(kstat_waitq_enter)
836 673 GET_NATIVE_TIME(%g1, %g2, %g3)
837 674 KSTAT_Q_UPDATE(add, BRZPT, 1f, 1:retl, KSTAT_IO_W)
838 675 SET_SIZE(kstat_waitq_enter)
839 676
840 677 .align 16
841 678 ENTRY(kstat_waitq_exit)
842 679 GET_NATIVE_TIME(%g1, %g2, %g3)
843 680 #if defined(DEBUG)
844 681 KSTAT_Q_UPDATE(sub, BRZPN, kstat_q_panic, retl, KSTAT_IO_W)
845 682 #else
846 683 KSTAT_Q_UPDATE_ND(sub, retl, KSTAT_IO_W)
847 684 #endif
848 685 SET_SIZE(kstat_waitq_exit)
849 686
850 687 .align 16
851 688 ENTRY(kstat_runq_enter)
852 689 GET_NATIVE_TIME(%g1, %g2, %g3)
853 690 KSTAT_Q_UPDATE(add, BRZPT, 1f, 1:retl, KSTAT_IO_R)
854 691 SET_SIZE(kstat_runq_enter)
855 692
856 693 .align 16
857 694 ENTRY(kstat_runq_exit)
858 695 GET_NATIVE_TIME(%g1, %g2, %g3)
859 696 #if defined(DEBUG)
860 697 KSTAT_Q_UPDATE(sub, BRZPN, kstat_q_panic, retl, KSTAT_IO_R)
861 698 #else
862 699 KSTAT_Q_UPDATE_ND(sub, retl, KSTAT_IO_R)
863 700 #endif
864 701 SET_SIZE(kstat_runq_exit)
865 702
866 703 .align 16
867 704 ENTRY(kstat_waitq_to_runq)
868 705 GET_NATIVE_TIME(%g1, %g2, %g3)
869 706 #if defined(DEBUG)
870 707 KSTAT_Q_UPDATE(sub, BRZPN, kstat_q_panic, 1:, KSTAT_IO_W)
871 708 #else
872 709 KSTAT_Q_UPDATE_ND(sub, 1:, KSTAT_IO_W)
873 710 #endif
874 711 KSTAT_Q_UPDATE(add, BRZPT, 1f, 1:retl, KSTAT_IO_R)
875 712 SET_SIZE(kstat_waitq_to_runq)
876 713
877 714 .align 16
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878 715 ENTRY(kstat_runq_back_to_waitq)
879 716 GET_NATIVE_TIME(%g1, %g2, %g3)
880 717 #if defined(DEBUG)
881 718 KSTAT_Q_UPDATE(sub, BRZPN, kstat_q_panic, 1:, KSTAT_IO_R)
882 719 #else
883 720 KSTAT_Q_UPDATE_ND(sub, 1:, KSTAT_IO_R)
884 721 #endif
885 722 KSTAT_Q_UPDATE(add, BRZPT, 1f, 1:retl, KSTAT_IO_W)
886 723 SET_SIZE(kstat_runq_back_to_waitq)
887 724
888 -#endif /* !(lint || __lint) */
889 -
890 -#ifdef lint
891 -
892 -int64_t timedelta;
893 -hrtime_t hres_last_tick;
894 -volatile timestruc_t hrestime;
895 -int64_t hrestime_adj;
896 -volatile int hres_lock;
897 -uint_t nsec_scale;
898 -hrtime_t hrtime_base;
899 -int traptrace_use_stick;
900 -
901 -#else /* lint */
902 725 /*
903 726 * -- WARNING --
904 727 *
905 728 * The following variables MUST be together on a 128-byte boundary.
906 729 * In addition to the primary performance motivation (having them all
907 730 * on the same cache line(s)), code here and in the GET*TIME() macros
908 731 * assumes that they all have the same high 22 address bits (so
909 732 * there's only one sethi).
910 733 */
911 734 .seg ".data"
912 735 .global timedelta, hres_last_tick, hrestime, hrestime_adj
913 736 .global hres_lock, nsec_scale, hrtime_base, traptrace_use_stick
914 737 .global nsec_shift, adj_shift
915 738
916 739 /* XXX - above comment claims 128-bytes is necessary */
917 740 .align 64
918 741 timedelta:
919 742 .word 0, 0 /* int64_t */
920 743 hres_last_tick:
921 744 .word 0, 0 /* hrtime_t */
922 745 hrestime:
923 746 .nword 0, 0 /* 2 longs */
924 747 hrestime_adj:
925 748 .word 0, 0 /* int64_t */
926 749 hres_lock:
927 750 .word 0
928 751 nsec_scale:
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929 752 .word 0
930 753 hrtime_base:
931 754 .word 0, 0
932 755 traptrace_use_stick:
933 756 .word 0
934 757 nsec_shift:
935 758 .word NSEC_SHIFT
936 759 adj_shift:
937 760 .word ADJ_SHIFT
938 761
939 -#endif /* lint */
940 762
941 -
942 763 /*
943 764 * drv_usecwait(clock_t n) [DDI/DKI - section 9F]
944 765 * usec_delay(int n) [compatibility - should go one day]
945 766 * Delay by spinning.
946 767 *
947 768 * delay for n microseconds. numbers <= 0 delay 1 usec
948 769 *
949 770 * With UltraSPARC-III the combination of supporting mixed-speed CPUs
950 771 * and variable clock rate for power management requires that we
951 772 * use %stick to implement this routine.
952 773 *
953 774 * For OPL platforms that support the "sleep" instruction, we
954 775 * conditionally (ifdef'ed) insert a "sleep" instruction in
955 776 * the loop. Note that theoritically we should have move (duplicated)
956 777 * the code down to spitfire/us3/opl specific asm files - but this
957 778 * is alot of code duplication just to add one "sleep" instruction.
958 779 * We chose less code duplication for this.
959 780 */
960 781
961 -#if defined(lint)
962 -
963 -/*ARGSUSED*/
964 -void
965 -drv_usecwait(clock_t n)
966 -{}
967 -
968 -/*ARGSUSED*/
969 -void
970 -usec_delay(int n)
971 -{}
972 -
973 -#else /* lint */
974 -
975 782 ENTRY(drv_usecwait)
976 783 ALTENTRY(usec_delay)
977 784 brlez,a,pn %o0, 0f
978 785 mov 1, %o0
979 786 0:
980 787 sethi %hi(sticks_per_usec), %o1
981 788 lduw [%o1 + %lo(sticks_per_usec)], %o1
982 789 mulx %o1, %o0, %o1 ! Scale usec to ticks
983 790 inc %o1 ! We don't start on a tick edge
984 791 GET_NATIVE_TIME(%o2, %o3, %o4)
985 792 add %o1, %o2, %o1
986 793
987 794 1:
988 795 #ifdef _OPL
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989 796 .word 0x81b01060 ! insert "sleep" instruction
990 797 #endif /* _OPL */ ! use byte code for now
991 798 cmp %o1, %o2
992 799 GET_NATIVE_TIME(%o2, %o3, %o4)
993 800 bgeu,pt %xcc, 1b
994 801 nop
995 802 retl
996 803 nop
997 804 SET_SIZE(usec_delay)
998 805 SET_SIZE(drv_usecwait)
999 -#endif /* lint */
1000 806
1001 -#if defined(lint)
1002 -
1003 -/* ARGSUSED */
1004 -void
1005 -pil14_interrupt(int level)
1006 -{}
1007 -
1008 -#else /* lint */
1009 -
1010 807 /*
1011 808 * Level-14 interrupt prologue.
1012 809 */
1013 810 ENTRY_NP(pil14_interrupt)
1014 811 CPU_ADDR(%g1, %g2)
1015 812 rdpr %pil, %g6 ! %g6 = interrupted PIL
1016 813 stn %g6, [%g1 + CPU_PROFILE_PIL] ! record interrupted PIL
1017 814 rdpr %tstate, %g6
1018 815 rdpr %tpc, %g5
1019 816 btst TSTATE_PRIV, %g6 ! trap from supervisor mode?
1020 817 bnz,a,pt %xcc, 1f
1021 818 stn %g5, [%g1 + CPU_PROFILE_PC] ! if so, record kernel PC
1022 819 stn %g5, [%g1 + CPU_PROFILE_UPC] ! if not, record user PC
1023 820 ba pil_interrupt_common ! must be large-disp branch
1024 821 stn %g0, [%g1 + CPU_PROFILE_PC] ! zero kernel PC
1025 822 1: ba pil_interrupt_common ! must be large-disp branch
1026 823 stn %g0, [%g1 + CPU_PROFILE_UPC] ! zero user PC
1027 824 SET_SIZE(pil14_interrupt)
1028 825
1029 826 ENTRY_NP(tick_rtt)
1030 827 !
1031 828 ! Load TICK_COMPARE into %o5; if bit 63 is set, then TICK_COMPARE is
1032 829 ! disabled. If TICK_COMPARE is enabled, we know that we need to
1033 830 ! reenqueue the interrupt request structure. We'll then check TICKINT
1034 831 ! in SOFTINT; if it's set, then we know that we were in a TICK_COMPARE
1035 832 ! interrupt. In this case, TICK_COMPARE may have been rewritten
1036 833 ! recently; we'll compare %o5 to the current time to verify that it's
1037 834 ! in the future.
1038 835 !
1039 836 ! Note that %o5 is live until after 1f.
1040 837 ! XXX - there is a subroutine call while %o5 is live!
1041 838 !
1042 839 RD_TICKCMPR(%o5, %g1)
1043 840 srlx %o5, TICKINT_DIS_SHFT, %g1
1044 841 brnz,pt %g1, 2f
1045 842 nop
1046 843
1047 844 rdpr %pstate, %g5
1048 845 andn %g5, PSTATE_IE, %g1
1049 846 wrpr %g0, %g1, %pstate ! Disable vec interrupts
1050 847
1051 848 sethi %hi(cbe_level14_inum), %o1
1052 849 ldx [%o1 + %lo(cbe_level14_inum)], %o1
1053 850 call intr_enqueue_req ! preserves %o5 and %g5
1054 851 mov PIL_14, %o0
1055 852
1056 853 ! Check SOFTINT for TICKINT/STICKINT
1057 854 rd SOFTINT, %o4
1058 855 set (TICK_INT_MASK | STICK_INT_MASK), %o0
1059 856 andcc %o4, %o0, %g0
1060 857 bz,a,pn %icc, 2f
1061 858 wrpr %g0, %g5, %pstate ! Enable vec interrupts
1062 859
1063 860 ! clear TICKINT/STICKINT
1064 861 wr %o0, CLEAR_SOFTINT
1065 862
1066 863 !
1067 864 ! Now that we've cleared TICKINT, we can reread %tick and confirm
1068 865 ! that the value we programmed is still in the future. If it isn't,
1069 866 ! we need to reprogram TICK_COMPARE to fire as soon as possible.
1070 867 !
1071 868 GET_NATIVE_TIME(%o0, %g1, %g2) ! %o0 = tick
1072 869 sllx %o0, 1, %o0 ! Clear the DIS bit
1073 870 srlx %o0, 1, %o0
1074 871 cmp %o5, %o0 ! In the future?
1075 872 bg,a,pt %xcc, 2f ! Yes, drive on.
1076 873 wrpr %g0, %g5, %pstate ! delay: enable vec intr
1077 874
1078 875 !
1079 876 ! If we're here, then we have programmed TICK_COMPARE with a %tick
1080 877 ! which is in the past; we'll now load an initial step size, and loop
1081 878 ! until we've managed to program TICK_COMPARE to fire in the future.
1082 879 !
1083 880 mov 8, %o4 ! 8 = arbitrary inital step
1084 881 1: add %o0, %o4, %o5 ! Add the step
1085 882 WR_TICKCMPR(%o5,%g1,%g2,__LINE__) ! Write to TICK_CMPR
1086 883 GET_NATIVE_TIME(%o0, %g1, %g2) ! %o0 = tick
1087 884 sllx %o0, 1, %o0 ! Clear the DIS bit
1088 885 srlx %o0, 1, %o0
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1089 886 cmp %o5, %o0 ! In the future?
1090 887 bg,a,pt %xcc, 2f ! Yes, drive on.
1091 888 wrpr %g0, %g5, %pstate ! delay: enable vec intr
1092 889 ba 1b ! No, try again.
1093 890 sllx %o4, 1, %o4 ! delay: double step size
1094 891
1095 892 2: ba current_thread_complete
1096 893 nop
1097 894 SET_SIZE(tick_rtt)
1098 895
1099 -#endif /* lint */
1100 -
1101 -#if defined(lint)
1102 -
1103 -/* ARGSUSED */
1104 -void
1105 -pil15_interrupt(int level)
1106 -{}
1107 -
1108 -#else /* lint */
1109 -
1110 896 /*
1111 897 * Level-15 interrupt prologue.
1112 898 */
1113 899 ENTRY_NP(pil15_interrupt)
1114 900 CPU_ADDR(%g1, %g2)
1115 901 rdpr %tstate, %g6
1116 902 rdpr %tpc, %g5
1117 903 btst TSTATE_PRIV, %g6 ! trap from supervisor mode?
1118 904 bnz,a,pt %xcc, 1f
1119 905 stn %g5, [%g1 + CPU_CPCPROFILE_PC] ! if so, record kernel PC
1120 906 stn %g5, [%g1 + CPU_CPCPROFILE_UPC] ! if not, record user PC
1121 907 ba pil15_epilogue ! must be large-disp branch
1122 908 stn %g0, [%g1 + CPU_CPCPROFILE_PC] ! zero kernel PC
1123 909 1: ba pil15_epilogue ! must be large-disp branch
1124 910 stn %g0, [%g1 + CPU_CPCPROFILE_UPC] ! zero user PC
1125 911 SET_SIZE(pil15_interrupt)
1126 912
1127 -#endif /* lint */
1128 -
1129 -#if defined(lint) || defined(__lint)
1130 -
1131 -/* ARGSUSED */
1132 -uint64_t
1133 -find_cpufrequency(volatile uchar_t *clock_ptr)
1134 -{
1135 - return (0);
1136 -}
1137 -
1138 -#else /* lint */
1139 -
1140 913 #ifdef DEBUG
1141 914 .seg ".text"
1142 915 find_cpufreq_panic:
1143 916 .asciz "find_cpufrequency: interrupts already disabled on entry"
1144 917 #endif /* DEBUG */
1145 918
1146 919 ENTRY_NP(find_cpufrequency)
1147 920 rdpr %pstate, %g1
1148 921
1149 922 #ifdef DEBUG
1150 923 andcc %g1, PSTATE_IE, %g0 ! If DEBUG, check that interrupts
1151 924 bnz 0f ! are currently enabled
1152 925 sethi %hi(find_cpufreq_panic), %o1
1153 926 call panic
1154 927 or %o1, %lo(find_cpufreq_panic), %o0
1155 928 #endif /* DEBUG */
1156 929
1157 930 0:
1158 931 wrpr %g1, PSTATE_IE, %pstate ! Disable interrupts
1159 932 3:
1160 933 ldub [%o0], %o1 ! Read the number of seconds
1161 934 mov %o1, %o2 ! remember initial value in %o2
1162 935 1:
1163 936 GET_NATIVE_TIME(%o3, %g4, %g5)
1164 937 cmp %o1, %o2 ! did the seconds register roll over?
1165 938 be,pt %icc, 1b ! branch back if unchanged
1166 939 ldub [%o0], %o2 ! delay: load the new seconds val
1167 940
1168 941 brz,pn %o2, 3b ! if the minutes just rolled over,
1169 942 ! the last second could have been
1170 943 ! inaccurate; try again.
1171 944 mov %o2, %o4 ! delay: store init. val. in %o2
1172 945 2:
1173 946 GET_NATIVE_TIME(%o5, %g4, %g5)
1174 947 cmp %o2, %o4 ! did the seconds register roll over?
1175 948 be,pt %icc, 2b ! branch back if unchanged
1176 949 ldub [%o0], %o4 ! delay: load the new seconds val
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1177 950
1178 951 brz,pn %o4, 0b ! if the minutes just rolled over,
1179 952 ! the last second could have been
1180 953 ! inaccurate; try again.
1181 954 wrpr %g0, %g1, %pstate ! delay: re-enable interrupts
1182 955
1183 956 retl
1184 957 sub %o5, %o3, %o0 ! return the difference in ticks
1185 958 SET_SIZE(find_cpufrequency)
1186 959
1187 -#endif /* lint */
1188 -
1189 -#if defined(lint)
1190 -/*
1191 - * Prefetch a page_t for write or read, this assumes a linear
1192 - * scan of sequential page_t's.
1193 - */
1194 -/*ARGSUSED*/
1195 -void
1196 -prefetch_page_w(void *pp)
1197 -{}
1198 -
1199 -/*ARGSUSED*/
1200 -void
1201 -prefetch_page_r(void *pp)
1202 -{}
1203 -#else /* lint */
1204 -
1205 960 #if defined(CHEETAH) || defined(CHEETAH_PLUS) || defined(JALAPENO) || \
1206 961 defined(SERRANO)
1207 962 !
1208 963 ! On US-III, the prefetch instruction queue is 8 entries deep.
1209 964 ! Also, prefetches for write put data in the E$, which has
1210 965 ! lines of 512 bytes for an 8MB cache. Each E$ line is further
1211 966 ! subblocked into 64 byte chunks.
1212 967 !
1213 968 ! Since prefetch can only bring in 64 bytes at a time (See Sparc
1214 969 ! v9 Architecture Manual pp.204) and a page_t is 128 bytes,
1215 970 ! then 2 prefetches are required in order to bring an entire
1216 971 ! page into the E$.
1217 972 !
1218 973 ! Since the prefetch queue is 8 entries deep, we currently can
1219 974 ! only have 4 prefetches for page_t's outstanding. Thus, we
1220 975 ! prefetch n+4 ahead of where we are now:
1221 976 !
1222 977 ! 4 * sizeof(page_t) -> 512
1223 978 ! 4 * sizeof(page_t) +64 -> 576
1224 979 !
1225 980 ! Example
1226 981 ! =======
1227 982 ! contiguous page array in memory...
1228 983 !
1229 984 ! |AAA1|AAA2|BBB1|BBB2|CCC1|CCC2|DDD1|DDD2|XXX1|XXX2|YYY1|YYY2|...
1230 985 ! ^ ^ ^ ^ ^ ^
1231 986 ! pp | pp+4*sizeof(page)+64
1232 987 ! |
1233 988 ! pp+4*sizeof(page)
1234 989 !
1235 990 ! Prefetch
1236 991 ! Queue
1237 992 ! +-------+<--- In this iteration, we're working with pp (AAA1),
1238 993 ! |Preftch| but we enqueue prefetch for addr = XXX1
1239 994 ! | XXX1 |
1240 995 ! +-------+<--- this queue slot will be a prefetch instruction for
1241 996 ! |Preftch| for addr = pp + 4*sizeof(page_t) + 64 (or second
1242 997 ! | XXX2 | half of page XXX)
1243 998 ! +-------+
1244 999 ! |Preftch|<-+- The next time around this function, we'll be
1245 1000 ! | YYY1 | | working with pp = BBB1, but will be enqueueing
1246 1001 ! +-------+ | prefetches to for both halves of page YYY,
1247 1002 ! |Preftch| | while both halves of page XXX are in transit
1248 1003 ! | YYY2 |<-+ make their way into the E$.
1249 1004 ! +-------+
1250 1005 ! |Preftch|
1251 1006 ! | ZZZ1 |
1252 1007 ! +-------+
1253 1008 ! . .
1254 1009 ! : :
1255 1010 !
1256 1011 ! E$
1257 1012 ! +============================================...
1258 1013 ! | XXX1 | XXX2 | YYY1 | YYY2 | ZZZ1 | ZZZ2 |
1259 1014 ! +============================================...
1260 1015 ! | | | | | | |
1261 1016 ! +============================================...
1262 1017 ! .
1263 1018 ! :
1264 1019 !
1265 1020 ! So we should expect the first four page accesses to stall
1266 1021 ! while we warm up the cache, afterwhich, most of the pages
1267 1022 ! will have their pp ready in the E$.
1268 1023 !
1269 1024 ! Also note that if sizeof(page_t) grows beyond 128, then
1270 1025 ! we'll need an additional prefetch to get an entire page
1271 1026 ! into the E$, thus reducing the number of outstanding page
1272 1027 ! prefetches to 2 (ie. 3 prefetches/page = 6 queue slots)
1273 1028 ! etc.
1274 1029 !
1275 1030 ! Cheetah+
1276 1031 ! ========
1277 1032 ! On Cheetah+ we use "#n_write" prefetches as these avoid
1278 1033 ! unnecessary RTS->RTO bus transaction state change, and
1279 1034 ! just issues RTO transaction. (See pp.77 of Cheetah+ Delta
1280 1035 ! PRM). On Cheetah, #n_write prefetches are reflected with
1281 1036 ! RTS->RTO state transition regardless.
1282 1037 !
1283 1038 #define STRIDE1 512
1284 1039 #define STRIDE2 576
1285 1040
1286 1041 #if STRIDE1 != (PAGE_SIZE * 4)
1287 1042 #error "STRIDE1 != (PAGE_SIZE * 4)"
1288 1043 #endif /* STRIDE1 != (PAGE_SIZE * 4) */
1289 1044
1290 1045 ENTRY(prefetch_page_w)
1291 1046 prefetch [%o0+STRIDE1], #n_writes
1292 1047 retl
1293 1048 prefetch [%o0+STRIDE2], #n_writes
1294 1049 SET_SIZE(prefetch_page_w)
1295 1050
1296 1051 !
1297 1052 ! Note on CHEETAH to prefetch for read, we really use #one_write.
1298 1053 ! This fetches to E$ (general use) rather than P$ (floating point use).
1299 1054 !
1300 1055 ENTRY(prefetch_page_r)
1301 1056 prefetch [%o0+STRIDE1], #one_write
1302 1057 retl
1303 1058 prefetch [%o0+STRIDE2], #one_write
1304 1059 SET_SIZE(prefetch_page_r)
1305 1060
1306 1061 #elif defined(SPITFIRE) || defined(HUMMINGBIRD)
1307 1062
1308 1063 !
1309 1064 ! UltraSparcII can have up to 3 prefetches outstanding.
1310 1065 ! A page_t is 128 bytes (2 prefetches of 64 bytes each)
1311 1066 ! So prefetch for pp + 1, which is
1312 1067 !
1313 1068 ! pp + sizeof(page_t)
1314 1069 ! and
1315 1070 ! pp + sizeof(page_t) + 64
1316 1071 !
1317 1072 #define STRIDE1 128
1318 1073 #define STRIDE2 192
1319 1074
1320 1075 #if STRIDE1 != PAGE_SIZE
1321 1076 #error "STRIDE1 != PAGE_SIZE"
1322 1077 #endif /* STRIDE1 != PAGE_SIZE */
1323 1078
1324 1079 ENTRY(prefetch_page_w)
1325 1080 prefetch [%o0+STRIDE1], #n_writes
1326 1081 retl
1327 1082 prefetch [%o0+STRIDE2], #n_writes
1328 1083 SET_SIZE(prefetch_page_w)
1329 1084
1330 1085 ENTRY(prefetch_page_r)
1331 1086 prefetch [%o0+STRIDE1], #n_reads
1332 1087 retl
1333 1088 prefetch [%o0+STRIDE2], #n_reads
1334 1089 SET_SIZE(prefetch_page_r)
1335 1090
1336 1091 #elif defined(OLYMPUS_C)
1337 1092 !
1338 1093 ! Prefetch strides for Olympus-C
1339 1094 !
1340 1095
1341 1096 #define STRIDE1 0x440
1342 1097 #define STRIDE2 0x640
1343 1098
1344 1099 ENTRY(prefetch_page_w)
1345 1100 prefetch [%o0+STRIDE1], #n_writes
1346 1101 retl
1347 1102 prefetch [%o0+STRIDE2], #n_writes
1348 1103 SET_SIZE(prefetch_page_w)
1349 1104
1350 1105 ENTRY(prefetch_page_r)
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1351 1106 prefetch [%o0+STRIDE1], #n_writes
1352 1107 retl
1353 1108 prefetch [%o0+STRIDE2], #n_writes
1354 1109 SET_SIZE(prefetch_page_r)
1355 1110 #else /* OLYMPUS_C */
1356 1111
1357 1112 #error "You need to fix this for your new cpu type."
1358 1113
1359 1114 #endif /* OLYMPUS_C */
1360 1115
1361 -#endif /* lint */
1362 -
1363 -#if defined(lint)
1364 -/*
1365 - * Prefetch struct smap for write.
1366 - */
1367 -/*ARGSUSED*/
1368 -void
1369 -prefetch_smap_w(void *smp)
1370 -{}
1371 -#else /* lint */
1372 -
1373 1116 #if defined(CHEETAH) || defined(CHEETAH_PLUS) || defined(JALAPENO) || \
1374 1117 defined(SERRANO)
1375 1118
1376 1119 #define PREFETCH_Q_LEN 8
1377 1120
1378 1121 #elif defined(SPITFIRE) || defined(HUMMINGBIRD)
1379 1122
1380 1123 #define PREFETCH_Q_LEN 3
1381 1124
1382 1125 #elif defined(OLYMPUS_C)
1383 1126 !
1384 1127 ! Use length of one for now.
1385 1128 !
1386 1129 #define PREFETCH_Q_LEN 1
1387 1130
1388 1131 #else /* OLYMPUS_C */
1389 1132
1390 1133 #error You need to fix this for your new cpu type.
1391 1134
1392 1135 #endif /* OLYMPUS_C */
1393 1136
1394 1137 #include <vm/kpm.h>
1395 1138
1396 1139 #ifdef SEGKPM_SUPPORT
1397 1140
1398 1141 #define SMAP_SIZE 72
1399 1142 #define SMAP_STRIDE (((PREFETCH_Q_LEN * 64) / SMAP_SIZE) * 64)
1400 1143
1401 1144 #else /* SEGKPM_SUPPORT */
1402 1145
1403 1146 !
1404 1147 ! The hardware will prefetch the 64 byte cache aligned block
1405 1148 ! that contains the address specified in the prefetch instruction.
1406 1149 ! Since the size of the smap struct is 48 bytes, issuing 1 prefetch
1407 1150 ! per pass will suffice as long as we prefetch far enough ahead to
1408 1151 ! make sure we don't stall for the cases where the smap object
1409 1152 ! spans multiple hardware prefetch blocks. Let's prefetch as far
1410 1153 ! ahead as the hardware will allow.
1411 1154 !
1412 1155 ! The smap array is processed with decreasing address pointers.
1413 1156 !
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1414 1157 #define SMAP_SIZE 48
1415 1158 #define SMAP_STRIDE (PREFETCH_Q_LEN * SMAP_SIZE)
1416 1159
1417 1160 #endif /* SEGKPM_SUPPORT */
1418 1161
1419 1162 ENTRY(prefetch_smap_w)
1420 1163 retl
1421 1164 prefetch [%o0-SMAP_STRIDE], #n_writes
1422 1165 SET_SIZE(prefetch_smap_w)
1423 1166
1424 -#endif /* lint */
1425 -
1426 -#if defined(lint) || defined(__lint)
1427 -
1428 -/* ARGSUSED */
1429 -uint64_t
1430 -getidsr(void)
1431 -{ return 0; }
1432 -
1433 -#else /* lint */
1434 -
1435 1167 ENTRY_NP(getidsr)
1436 1168 retl
1437 1169 ldxa [%g0]ASI_INTR_DISPATCH_STATUS, %o0
1438 1170 SET_SIZE(getidsr)
1439 1171
1440 -#endif /* lint */
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