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de-linting of .s files
@@ -20,13 +20,11 @@
*/
/*
* Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
*/
-#if !defined(lint)
#include "assym.h"
-#endif /* !lint */
/*
* General assembly language routines.
* It is the intent of this file to contain routines that are
* specific to cpu architecture.
@@ -211,20 +209,11 @@
#endif /* !CHEETAH && !HUMMINGBIRD */
#include <sys/clock.h>
-#if defined(lint)
-#include <sys/types.h>
-#include <sys/scb.h>
-#include <sys/systm.h>
-#include <sys/regset.h>
-#include <sys/sunddi.h>
-#include <sys/lockstat.h>
-#endif /* lint */
-
#include <sys/asm_linkage.h>
#include <sys/privregs.h>
#include <sys/machparam.h> /* To get SYSBASE and PAGESIZE */
#include <sys/machthread.h>
#include <sys/clock.h>
@@ -232,42 +221,18 @@
#include <sys/psr_compat.h>
#include <sys/isa_defs.h>
#include <sys/dditypes.h>
#include <sys/intr.h>
-#if !defined(lint)
#include "assym.h"
-#endif /* !lint */
-#if defined(lint)
-
-uint_t
-get_impl(void)
-{ return (0); }
-
-#else /* lint */
-
ENTRY(get_impl)
GET_CPU_IMPL(%o0)
retl
nop
SET_SIZE(get_impl)
-#endif /* lint */
-
-#if defined(lint)
-/*
- * Softint generated when counter field of tick reg matches value field
- * of tick_cmpr reg
- */
-/*ARGSUSED*/
-void
-tickcmpr_set(uint64_t clock_cycles)
-{}
-
-#else /* lint */
-
ENTRY_NP(tickcmpr_set)
! get 64-bit clock_cycles interval
mov %o0, %o2
mov 8, %o3 ! A reasonable initial step size
1:
@@ -285,47 +250,18 @@
2:
retl
nop
SET_SIZE(tickcmpr_set)
-#endif /* lint */
-
-#if defined(lint)
-
-void
-tickcmpr_disable(void)
-{}
-
-#else /* lint */
-
ENTRY_NP(tickcmpr_disable)
mov 1, %g1
sllx %g1, TICKINT_DIS_SHFT, %o0
WR_TICKCMPR(%o0,%o4,%o5,__LINE__) ! Write to TICK_CMPR
retl
nop
SET_SIZE(tickcmpr_disable)
-#endif /* lint */
-
-#if defined(lint)
-
-/*
- * tick_write_delta() increments %tick by the specified delta. This should
- * only be called after a CPR event to assure that gethrtime() continues to
- * increase monotonically. Obviously, writing %tick needs to de done very
- * carefully to avoid introducing unnecessary %tick skew across CPUs. For
- * this reason, we make sure we're i-cache hot before actually writing to
- * %tick.
- */
-/*ARGSUSED*/
-void
-tick_write_delta(uint64_t delta)
-{}
-
-#else /* lint */
-
#ifdef DEBUG
.seg ".text"
tick_write_panic:
.asciz "tick_write_delta: interrupts already disabled on entry"
#endif /* DEBUG */
@@ -348,141 +284,46 @@
0: nop ! The next 3 instructions are now hot.
DELTA_NATIVE_TIME(%o2, %o3, %o4, %o5, %g2) ! read/inc/write %tick
retl ! Return
wrpr %g0, %g1, %pstate ! delay: Re-enable interrupts
-#endif /* lint */
-#if defined(lint)
-/*
- * return 1 if disabled
- */
-
-int
-tickcmpr_disabled(void)
-{ return (0); }
-
-#else /* lint */
-
ENTRY_NP(tickcmpr_disabled)
RD_TICKCMPR(%g1, %o0)
retl
srlx %g1, TICKINT_DIS_SHFT, %o0
SET_SIZE(tickcmpr_disabled)
-#endif /* lint */
-
/*
* Get current tick
*/
-#if defined(lint)
-u_longlong_t
-gettick(void)
-{ return (0); }
-
-u_longlong_t
-randtick(void)
-{ return (0); }
-
-#else /* lint */
-
ENTRY(gettick)
ALTENTRY(randtick)
GET_NATIVE_TIME(%o0, %o2, %o3)
retl
nop
SET_SIZE(randtick)
SET_SIZE(gettick)
-#endif /* lint */
-
/*
* Return the counter portion of the tick register.
*/
-#if defined(lint)
-
-uint64_t
-gettick_counter(void)
-{ return(0); }
-
-#else /* lint */
-
ENTRY_NP(gettick_counter)
rdpr %tick, %o0
sllx %o0, 1, %o0
retl
srlx %o0, 1, %o0 ! shake off npt bit
SET_SIZE(gettick_counter)
-#endif /* lint */
/*
* Provide a C callable interface to the trap that reads the hi-res timer.
* Returns 64-bit nanosecond timestamp in %o0 and %o1.
*/
-#if defined(lint)
-
-hrtime_t
-gethrtime(void)
-{
- return ((hrtime_t)0);
-}
-
-hrtime_t
-gethrtime_unscaled(void)
-{
- return ((hrtime_t)0);
-}
-
-hrtime_t
-gethrtime_max(void)
-{
- return ((hrtime_t)0);
-}
-
-void
-scalehrtime(hrtime_t *hrt)
-{
- *hrt = 0;
-}
-
-void
-gethrestime(timespec_t *tp)
-{
- tp->tv_sec = 0;
- tp->tv_nsec = 0;
-}
-
-time_t
-gethrestime_sec(void)
-{
- return (0);
-}
-
-void
-gethrestime_lasttick(timespec_t *tp)
-{
- tp->tv_sec = 0;
- tp->tv_nsec = 0;
-}
-
-/*ARGSUSED*/
-void
-hres_tick(void)
-{
-}
-
-void
-panic_hres_tick(void)
-{
-}
-
-#else /* lint */
-
ENTRY_NP(gethrtime)
GET_HRTIME(%g1, %o0, %o1, %o2, %o3, %o4, %o5, %g2)
! %g1 = hrtime
retl
mov %g1, %o0
@@ -770,14 +611,10 @@
call panic
or %o0, %lo(hrtime_base_panic), %o0
SET_SIZE(hres_tick)
-#endif /* lint */
-
-#if !defined(lint) && !defined(__lint)
-
.seg ".text"
kstat_q_panic_msg:
.asciz "kstat_q_exit: qlen == 0"
ENTRY(kstat_q_panic)
@@ -883,24 +720,10 @@
KSTAT_Q_UPDATE_ND(sub, 1:, KSTAT_IO_R)
#endif
KSTAT_Q_UPDATE(add, BRZPT, 1f, 1:retl, KSTAT_IO_W)
SET_SIZE(kstat_runq_back_to_waitq)
-#endif /* !(lint || __lint) */
-
-#ifdef lint
-
-int64_t timedelta;
-hrtime_t hres_last_tick;
-volatile timestruc_t hrestime;
-int64_t hrestime_adj;
-volatile int hres_lock;
-uint_t nsec_scale;
-hrtime_t hrtime_base;
-int traptrace_use_stick;
-
-#else /* lint */
/*
* -- WARNING --
*
* The following variables MUST be together on a 128-byte boundary.
* In addition to the primary performance motivation (having them all
@@ -934,13 +757,11 @@
nsec_shift:
.word NSEC_SHIFT
adj_shift:
.word ADJ_SHIFT
-#endif /* lint */
-
/*
* drv_usecwait(clock_t n) [DDI/DKI - section 9F]
* usec_delay(int n) [compatibility - should go one day]
* Delay by spinning.
*
@@ -956,24 +777,10 @@
* the code down to spitfire/us3/opl specific asm files - but this
* is alot of code duplication just to add one "sleep" instruction.
* We chose less code duplication for this.
*/
-#if defined(lint)
-
-/*ARGSUSED*/
-void
-drv_usecwait(clock_t n)
-{}
-
-/*ARGSUSED*/
-void
-usec_delay(int n)
-{}
-
-#else /* lint */
-
ENTRY(drv_usecwait)
ALTENTRY(usec_delay)
brlez,a,pn %o0, 0f
mov 1, %o0
0:
@@ -994,21 +801,11 @@
nop
retl
nop
SET_SIZE(usec_delay)
SET_SIZE(drv_usecwait)
-#endif /* lint */
-#if defined(lint)
-
-/* ARGSUSED */
-void
-pil14_interrupt(int level)
-{}
-
-#else /* lint */
-
/*
* Level-14 interrupt prologue.
*/
ENTRY_NP(pil14_interrupt)
CPU_ADDR(%g1, %g2)
@@ -1094,21 +891,10 @@
2: ba current_thread_complete
nop
SET_SIZE(tick_rtt)
-#endif /* lint */
-
-#if defined(lint)
-
-/* ARGSUSED */
-void
-pil15_interrupt(int level)
-{}
-
-#else /* lint */
-
/*
* Level-15 interrupt prologue.
*/
ENTRY_NP(pil15_interrupt)
CPU_ADDR(%g1, %g2)
@@ -1122,23 +908,10 @@
stn %g0, [%g1 + CPU_CPCPROFILE_PC] ! zero kernel PC
1: ba pil15_epilogue ! must be large-disp branch
stn %g0, [%g1 + CPU_CPCPROFILE_UPC] ! zero user PC
SET_SIZE(pil15_interrupt)
-#endif /* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-uint64_t
-find_cpufrequency(volatile uchar_t *clock_ptr)
-{
- return (0);
-}
-
-#else /* lint */
-
#ifdef DEBUG
.seg ".text"
find_cpufreq_panic:
.asciz "find_cpufrequency: interrupts already disabled on entry"
#endif /* DEBUG */
@@ -1182,28 +955,10 @@
retl
sub %o5, %o3, %o0 ! return the difference in ticks
SET_SIZE(find_cpufrequency)
-#endif /* lint */
-
-#if defined(lint)
-/*
- * Prefetch a page_t for write or read, this assumes a linear
- * scan of sequential page_t's.
- */
-/*ARGSUSED*/
-void
-prefetch_page_w(void *pp)
-{}
-
-/*ARGSUSED*/
-void
-prefetch_page_r(void *pp)
-{}
-#else /* lint */
-
#if defined(CHEETAH) || defined(CHEETAH_PLUS) || defined(JALAPENO) || \
defined(SERRANO)
!
! On US-III, the prefetch instruction queue is 8 entries deep.
! Also, prefetches for write put data in the E$, which has
@@ -1356,22 +1111,10 @@
#error "You need to fix this for your new cpu type."
#endif /* OLYMPUS_C */
-#endif /* lint */
-
-#if defined(lint)
-/*
- * Prefetch struct smap for write.
- */
-/*ARGSUSED*/
-void
-prefetch_smap_w(void *smp)
-{}
-#else /* lint */
-
#if defined(CHEETAH) || defined(CHEETAH_PLUS) || defined(JALAPENO) || \
defined(SERRANO)
#define PREFETCH_Q_LEN 8
@@ -1419,22 +1162,10 @@
ENTRY(prefetch_smap_w)
retl
prefetch [%o0-SMAP_STRIDE], #n_writes
SET_SIZE(prefetch_smap_w)
-#endif /* lint */
-
-#if defined(lint) || defined(__lint)
-
-/* ARGSUSED */
-uint64_t
-getidsr(void)
-{ return 0; }
-
-#else /* lint */
-
ENTRY_NP(getidsr)
retl
ldxa [%g0]ASI_INTR_DISPATCH_STATUS, %o0
SET_SIZE(getidsr)
-#endif /* lint */