Print this page
de-linting of .s files
Split |
Close |
Expand all |
Collapse all |
--- old/usr/src/uts/sparc/ml/fd_asm.s
+++ new/usr/src/uts/sparc/ml/fd_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License, Version 1.0 only
6 6 * (the "License"). You may not use this file except in compliance
7 7 * with the License.
8 8 *
9 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 10 * or http://www.opensolaris.org/os/licensing.
11 11 * See the License for the specific language governing permissions
12 12 * and limitations under the License.
13 13 *
14 14 * When distributing Covered Code, include this CDDL HEADER in each
15 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 16 * If applicable, add the following below this CDDL HEADER, with the
17 17 * fields enclosed by brackets "[]" replaced with your own identifying
18 18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 19 *
20 20 * CDDL HEADER END
21 21 */
22 22 /*
23 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
↓ open down ↓ |
24 lines elided |
↑ open up ↑ |
25 25 */
26 26
27 27 #ident "%Z%%M% %I% %E% SMI"
28 28
29 29 /*
30 30 * This file contains no entry points which can be called directly from
31 31 * C and hence is of no interest to lint. However, we want to avoid the
32 32 * dreaded "Empty translation unit" warning.
33 33 */
34 34
35 -#if defined(lint)
36 -#include <sys/types.h>
37 -
38 -/*ARGSUSED*/
39 -u_int
40 -fd_intr(caddr_t arg)
41 -{
42 - return (0);
43 -}
44 -
45 -#else /* lint */
46 -
47 35 #include <sys/asm_linkage.h>
48 36 #include <sys/fdreg.h>
49 37 #include <sys/fdvar.h>
50 38 #include "fd_assym.h"
51 39
52 40 /*
53 41 * Since this is part of a Sparc "generic" module, it may be loaded during
54 42 * reconfigure time on systems that do not support the fast interrupt
55 43 * handler. On these machines the symbol "impl_setintreg_on" will be
56 44 * undefined but we don't want to cause error messages when we load.
57 45 */
58 46 .weak impl_setintreg_on
59 47 .type impl_setintreg_on, #function
60 48 .weak fd_softintr_cookie
61 49 .type fd_softintr_cookie, #object
62 50
63 51 #define Tmp2 %l4 /* temp register prior to dispatch to right opmode */
64 52 #define Reg %l4 /* pointer to the chip's registers */
65 53 #define Fdc %l3 /* pointer to fdctlr structure */
66 54 #define Adr %l5 /* data address pointer */
67 55 #define Len %l6 /* data length counter */
68 56 #define Tmp %l7 /* general scratch */
69 57 #define TRIGGER 0x33
70 58 ENTRY(fd_intr) ! fd standard interrupt handler
71 59 save %sp, -SA(MINFRAME), %sp
72 60 !
73 61 ! Traverse the list of controllers until we find the first
74 62 ! controller expecting an interrupt. Unfortunately, the
75 63 ! 82072 floppy controller really doesn't have a way to tell
76 64 ! you that it is interrupting.
77 65 !
78 66 set fdctlrs, Fdc ! load list of controllers
79 67 ldn [Fdc], Fdc ! get the first in the list...
80 68 1: tst Fdc ! do we have any more to check
81 69 bz .panic ! Nothing to service. Panic
82 70 nop
83 71
84 72 3: ldub [Fdc + FD_OPMODE], Tmp2 ! load opmode into Tmp2
85 73 and Tmp2, 0x3, Tmp2 ! opmode must be 1, 2, or 3
86 74 tst Tmp2 ! non-zero?
87 75 bnz .mutex_enter ! yes!
88 76 nop
89 77 ldn [Fdc + FD_NEXT], Tmp ! Try next ctlr...
90 78 tst Tmp
91 79 bnz,a 1b
92 80 mov Tmp, Fdc
93 81 ! no more controllers
94 82 mov 0x2, Tmp2 ! must be spurious or "ready" int
95 83 .mutex_enter:
96 84 !
97 85 ! grab high level mutex for this controller
98 86 !
99 87 sethi %hi(asm_mutex_spin_enter), %l7
100 88 jmpl %l7 + %lo(asm_mutex_spin_enter), %l7
101 89 add Fdc, FD_HILOCK, %l6
102 90 !
103 91 ! dispatch to correct handler
104 92 !
105 93 cmp Tmp2, 3 !case 3: results ?
106 94 be,a .opmode3 ! yes...
107 95 ldn [Fdc + FD_REG], Reg ! load pointer to h/w registers
108 96 cmp Tmp2, 2 !case 2: seek/recalibrate ?
109 97 be .opmode2 ! yes..
110 98 ldn [Fdc + FD_REG], Reg ! load pointer to h/w registers
111 99 !
112 100 ! opmode 1:
113 101 ! read/write/format data-xfer case - they have a result phase
114 102 !
115 103 .opmode1:
116 104 ld [Fdc + FD_RLEN], Len
117 105 !
118 106 ! XXX- test for null raddr
119 107 !
120 108 ldn [Fdc + FD_RADDR], Adr
121 109
122 110 !
123 111 ! while the fifo ready bit set, then data/status available
124 112 !
125 113 1: ldub [Reg], Tmp ! get csr
126 114 andcc Tmp, RQM, %g0 !
127 115 be 4f ! branch if bit clear
128 116 andcc Tmp, NDM, %g0 ! NDM set means data
129 117 be 7f ! if not set, it is status time
130 118 andcc Tmp, DIO, %g0 ! check for input vs. output data
131 119 be 2f !
132 120 sub Len, 0x1, Len ! predecrement length...
133 121 ldub [Reg + 0x1], Tmp ! DIO set, *addr = *fifo
134 122 b 3f !
135 123 stb Tmp, [Adr] !
136 124 2: ldsb [Adr], Tmp ! *fifo = *addr
137 125 stb Tmp, [Reg + 0x1] !
138 126 3: tst Len ! if (len == 0) send TC
139 127 bne 1b ! branch if not....
140 128 add Adr, 0x1, Adr !
141 129 b 6f !
142 130 .empty !
143 131 !
144 132 ! save updated len, addr
145 133 !
146 134 4: st Len, [Fdc + FD_RLEN]
147 135 b .out ! not done yet, return
148 136 stn Adr, [Fdc + FD_RADDR]
149 137 !
150 138 ! END OF TRANSFER - if read/write, toggle the TC
151 139 ! bit in AUXIO_REG then save status and set state = 3.
152 140 !
153 141 5:
154 142 !
155 143 ! Stash len and addr before they get lost
156 144 !
157 145 st Len, [Fdc + FD_RLEN]
158 146 6: stn Adr, [Fdc + FD_RADDR]
159 147 !
160 148 ! Begin TC delay...
161 149 ! Old comment:
162 150 ! five nops provide 100ns of delay at 10MIPS to ensure
163 151 ! TC is wide enough at slowest possible floppy clock
164 152 ! (500ns @ 250Kbps).
165 153 !
166 154 ! I gather this mean that we have to give 100ns delay for TC.
167 155 !
168 156 ! At 100 Mips, that would be 1 * 10 (10) nops.
169 157 !
170 158
171 159 ldn [Fdc + FD_AUXIOVA], Adr
172 160 ldub [Fdc + FD_AUXIODATA], Tmp2
173 161 ldub [Adr], Tmp
174 162 or Tmp, Tmp2, Tmp
175 163 stb Tmp, [Adr]
176 164 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop ! 10 nops
177 165 !
178 166 ! End TC delay...now clear the TC bit
179 167 !
180 168 ldub [Fdc + FD_AUXIODATA2], Tmp2
181 169 andn Tmp, Tmp2, Tmp
182 170 stb Tmp, [Adr]
183 171
184 172 !
185 173 ! set opmode to 3 to indicate going into status mode
186 174 !
187 175 mov 3, Tmp
188 176 b .out
189 177 stb Tmp, [Fdc + FD_OPMODE]
190 178 !
191 179 ! error status state: save old pointers, go direct to result snarfing
192 180 !
193 181 7: st Len, [Fdc + FD_RLEN]
194 182 stn Adr, [Fdc + FD_RADDR]
195 183 mov 0x3, Tmp
196 184 b .opmode3
197 185 stb Tmp, [Fdc + FD_OPMODE]
198 186 !
199 187 ! opmode 2:
200 188 ! recalibrate/seek - no result phase, must do sense interrupt status.
201 189 !
202 190 .opmode2:
203 191 ldub [Reg], Tmp ! Tmp = *csr
204 192 1: andcc Tmp, CB, %g0 ! is CB set?
205 193 bne 1b ! yes, keep waiting
206 194 ldub [Reg], Tmp !! Tmp = *csr
207 195 !
208 196 ! wait!!! should we check rqm first??? ABSOLUTELY YES!!!!
209 197 !
210 198 1: andcc Tmp, RQM, %g0 !
211 199 be,a 1b ! branch if bit clear
212 200 ldub [Reg], Tmp ! busy wait until RQM set
213 201 mov SNSISTAT, Tmp ! cmd for SENSE_INTERRUPT_STATUS
214 202 stb Tmp, [Reg + 0x1]
215 203 !
216 204 ! NOTE: we ignore DIO here, assume it is set before RQM!
217 205 !
218 206 ldub [Reg], Tmp ! busy wait until RQM set
219 207 1: andcc Tmp, RQM, Tmp
220 208 be,a 1b ! branch if bit clear
221 209 ldub [Reg], Tmp ! busy wait until RQM set
222 210 !
223 211 ! fdc->c_csb.csb_rslt[0] = *fifo;
224 212 !
225 213 ldub [Reg + 0x1], Tmp
226 214 stb Tmp, [Fdc + FD_RSLT]
227 215 ldub [Reg], Tmp ! busy wait until RQM set
228 216 1: andcc Tmp, RQM, Tmp
229 217 be,a 1b ! branch if bit clear
230 218 ldub [Reg], Tmp ! busy wait until RQM set
231 219 !
232 220 ! fdc->c_csb.csb_rslt[1] = *fifo;
233 221 !
234 222 ldub [Reg + 0x1], Tmp
235 223 b .notify
236 224 stb Tmp, [Fdc + FD_RSLT + 1]
237 225 !
238 226 ! case 3: result mode
239 227 ! We are in result mode make sure all status bytes are read out
240 228 !
241 229 ! We have to have *both* RQM and DIO set.
242 230 !
243 231 .opmode3:
244 232 add Fdc, FD_RSLT, Adr ! load address of csb->csb_rslt
245 233 add Adr, 10, Len ! put an upper bound on it..
246 234 ldub [Reg], Tmp !
247 235 1: andcc Tmp, CB, %g0 ! is CB set?
248 236 be .notify ! no, jump around, must be done
249 237 andcc Tmp, RQM, %g0 ! check for RQM in delay slot
250 238 be,a 1b ! No RQM, go back
251 239 ldub [Reg], Tmp ! and load control reg in delay
252 240 andcc Tmp, DIO, %g0 ! DIO set?
253 241 be,a 1b ! No DIO, go back
254 242 ldub [Reg], Tmp ! and load control reg in delay
255 243 !
256 244 ! CB && DIO && RQM all true.
257 245 ! Time to get a byte.
258 246 !
259 247 ldub [Reg + 0x1], Tmp ! *fifo into Tmp
260 248 cmp Adr, Len ! already at our limit?
261 249 bge,a 1b ! Yes, go back..
262 250 ldub [Reg], Tmp ! and load control reg in delay
263 251 stb Tmp, [Adr] ! store new byte
264 252 add Adr, 1, Adr ! increment address
265 253 b 1b ! and pop back to the top
266 254 ldub [Reg], Tmp ! and load control reg in delay
267 255
268 256 !
269 257 ! schedule 2nd stage interrupt
270 258 !
271 259 .notify:
272 260 !
273 261 ! if fast traps are enabled, use the platform dependent
274 262 ! impl_setintreg_on function.
275 263 !
276 264 ldub [Fdc + FD_FASTTRAP], Tmp
277 265 tst Tmp
278 266 bnz .fast
279 267 nop
280 268
281 269 !
282 270 ! fast traps are not in use. Do not schedule the soft interrupt
283 271 ! at this time. Wait to trigger it at the end of the handler
284 272 ! when the mutexes have been released
285 273 !
286 274 mov TRIGGER, Tmp2
287 275 b .out
288 276 nop
289 277
290 278 !
291 279 ! fast traps are enabled. Schedule the soft interrupt.
292 280 ! impl_setintreg uses %l4-%l7
293 281 !
294 282 .fast: sethi %hi(fd_softintr_cookie), %l6
295 283 sethi %hi(impl_setintreg_on), %l7
296 284 jmpl %l7 + %lo(impl_setintreg_on), %l7
297 285 ld [%l6 + %lo(fd_softintr_cookie)], %l6
298 286 !
299 287 ! set new opmode to 4
300 288 !
301 289 mov 0x4, Tmp
302 290 stb Tmp, [Fdc + FD_OPMODE]
303 291
304 292 !
305 293 ! and fall through to exit
306 294 !
307 295 .out:
308 296 !
309 297 ! update high level interrupt counter...
310 298 !
311 299 ldn [Fdc + FD_HIINTCT], Adr
312 300 tst Adr
313 301 be,a 1f
314 302 nop
315 303 ld [Adr], Tmp
316 304 inc Tmp
317 305 st Tmp, [Adr]
318 306 1:
319 307 !
320 308 ! Release mutex
321 309 !
322 310 sethi %hi(asm_mutex_spin_exit), %l7
323 311 jmpl %l7 + %lo(asm_mutex_spin_exit), %l7
324 312 add Fdc, FD_HILOCK, %l6
325 313
326 314 !
327 315 ! schedule the soft interrupt if needed
328 316 !
329 317 cmp Tmp2, TRIGGER
330 318 bne .end
331 319 nop
332 320
333 321 !
334 322 ! set new opmode to 4
335 323 !
336 324 mov 0x4, Tmp
337 325 stb Tmp, [Fdc + FD_OPMODE]
338 326
339 327 ! invoke ddi_trigger_softintr. load
340 328 ! softid parameter in the delay slot
341 329 !
342 330 call ddi_trigger_softintr
343 331 ldn [Fdc + FD_SOFTID], %o0
344 332
345 333 .end: mov 1, %i0
346 334 ret
347 335 restore
348 336 SET_SIZE(fd_intr)
↓ open down ↓ |
292 lines elided |
↑ open up ↑ |
349 337
350 338 .panic:
351 339 ! invoke a kernel panic
352 340 sethi %hi(panic_msg), %o1
353 341 ldn [%o1 + %lo(panic_msg)], %o1
354 342 mov 3, %o0
355 343 call cmn_err
356 344 nop
357 345
358 346
359 -#endif /* lint */
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX