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--- old/usr/src/uts/intel/ia32/ml/float.s
+++ new/usr/src/uts/intel/ia32/ml/float.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
24 24 * Copyright (c) 2018, Joyent, Inc.
25 25 */
26 26
27 27 /* Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. */
28 28 /* Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T */
29 29 /* All Rights Reserved */
30 30
31 31 /* Copyright (c) 1987, 1988 Microsoft Corporation */
32 32 /* All Rights Reserved */
33 33
34 34 /*
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35 35 * Copyright (c) 2009, Intel Corporation.
36 36 * All rights reserved.
37 37 */
38 38
39 39 #include <sys/asm_linkage.h>
40 40 #include <sys/asm_misc.h>
41 41 #include <sys/regset.h>
42 42 #include <sys/privregs.h>
43 43 #include <sys/x86_archext.h>
44 44
45 -#if defined(__lint)
46 -#include <sys/types.h>
47 -#include <sys/fp.h>
48 -#else
49 45 #include "assym.h"
50 -#endif
51 46
52 -#if defined(__lint)
53 -
54 -uint_t
55 -fpu_initial_probe(void)
56 -{ return (0); }
57 -
58 -#else /* __lint */
59 -
60 47 /*
61 48 * Returns zero if x87 "chip" is present(!)
62 49 */
63 50 ENTRY_NP(fpu_initial_probe)
64 51 CLTS
65 52 fninit
66 53 fnstsw %ax
67 54 movzbl %al, %eax
68 55 ret
69 56 SET_SIZE(fpu_initial_probe)
70 57
71 -#endif /* __lint */
72 -
73 -#if defined(__lint)
74 -
75 -/*ARGSUSED*/
76 -void
77 -fxsave_insn(struct fxsave_state *fx)
78 -{}
79 -
80 -#else /* __lint */
81 -
82 58 ENTRY_NP(fxsave_insn)
83 59 fxsaveq (%rdi)
84 60 ret
85 61 SET_SIZE(fxsave_insn)
86 62
87 -#endif /* __lint */
88 -
89 63 /*
90 64 * One of these routines is called from any lwp with floating
91 65 * point context as part of the prolog of a context switch.
92 66 */
93 67
94 -#if defined(__lint)
95 -
96 -/*ARGSUSED*/
97 -void
98 -xsave_ctxt(void *arg)
99 -{}
100 -
101 -/*ARGSUSED*/
102 -void
103 -xsaveopt_ctxt(void *arg)
104 -{}
105 -
106 -/*ARGSUSED*/
107 -void
108 -fpxsave_ctxt(void *arg)
109 -{}
110 -
111 -#else /* __lint */
112 -
113 68 /*
114 69 * These three functions define the Intel "xsave" handling for CPUs with
115 70 * different features. Newer AMD CPUs can also use these functions. See the
116 71 * 'exception pointers' comment below.
117 72 */
118 73 ENTRY_NP(fpxsave_ctxt) /* %rdi is a struct fpu_ctx */
119 74 cmpl $FPU_EN, FPU_CTX_FPU_FLAGS(%rdi)
120 75 jne 1f
121 76 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%rdi)
122 77 movq FPU_CTX_FPU_REGS(%rdi), %rdi /* fpu_regs.kfpu_u.kfpu_fx ptr */
123 78 fxsaveq (%rdi)
124 79 STTS(%rsi) /* trap on next fpu touch */
125 80 1: rep; ret /* use 2 byte return instruction when branch target */
126 81 /* AMD Software Optimization Guide - Section 6.2 */
127 82 SET_SIZE(fpxsave_ctxt)
128 83
129 84 ENTRY_NP(xsave_ctxt)
130 85 cmpl $FPU_EN, FPU_CTX_FPU_FLAGS(%rdi)
131 86 jne 1f
132 87 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%rdi)
133 88 movl FPU_CTX_FPU_XSAVE_MASK(%rdi), %eax /* xsave flags in EDX:EAX */
134 89 movl FPU_CTX_FPU_XSAVE_MASK+4(%rdi), %edx
135 90 movq FPU_CTX_FPU_REGS(%rdi), %rsi /* fpu_regs.kfpu_u.kfpu_xs ptr */
136 91 xsave (%rsi)
137 92 STTS(%rsi) /* trap on next fpu touch */
138 93 1: ret
139 94 SET_SIZE(xsave_ctxt)
140 95
141 96 ENTRY_NP(xsaveopt_ctxt)
142 97 cmpl $FPU_EN, FPU_CTX_FPU_FLAGS(%rdi)
143 98 jne 1f
144 99 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%rdi)
145 100 movl FPU_CTX_FPU_XSAVE_MASK(%rdi), %eax /* xsave flags in EDX:EAX */
146 101 movl FPU_CTX_FPU_XSAVE_MASK+4(%rdi), %edx
147 102 movq FPU_CTX_FPU_REGS(%rdi), %rsi /* fpu_regs.kfpu_u.kfpu_xs ptr */
148 103 xsaveopt (%rsi)
149 104 STTS(%rsi) /* trap on next fpu touch */
150 105 1: ret
151 106 SET_SIZE(xsaveopt_ctxt)
152 107
153 108 /*
154 109 * On certain AMD processors, the "exception pointers" (i.e. the last
155 110 * instruction pointer, last data pointer, and last opcode) are saved by the
156 111 * fxsave, xsave or xsaveopt instruction ONLY if the exception summary bit is
157 112 * set.
158 113 *
159 114 * On newer CPUs, AMD has changed their behavior to mirror the Intel behavior.
160 115 * We can detect this via an AMD specific cpuid feature bit
161 116 * (CPUID_AMD_EBX_ERR_PTR_ZERO) and use the simpler Intel-oriented functions.
162 117 * Otherwise we use these more complex functions on AMD CPUs. All three follow
163 118 * the same logic after the xsave* instruction.
164 119 */
165 120 ENTRY_NP(fpxsave_excp_clr_ctxt) /* %rdi is a struct fpu_ctx */
166 121 cmpl $FPU_EN, FPU_CTX_FPU_FLAGS(%rdi)
167 122 jne 1f
168 123 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%rdi)
169 124 movq FPU_CTX_FPU_REGS(%rdi), %rdi /* fpu_regs.kfpu_u.kfpu_fx ptr */
170 125 fxsaveq (%rdi)
171 126 /*
172 127 * To ensure that we don't leak these values into the next context
173 128 * on the cpu, we could just issue an fninit here, but that's
174 129 * rather slow and so we issue an instruction sequence that
175 130 * clears them more quickly, if a little obscurely.
176 131 */
177 132 btw $7, FXSAVE_STATE_FSW(%rdi) /* Test saved ES bit */
178 133 jnc 0f /* jump if ES = 0 */
179 134 fnclex /* clear pending x87 exceptions */
180 135 0: ffree %st(7) /* clear tag bit to remove possible stack overflow */
181 136 fildl .fpzero_const(%rip)
182 137 /* dummy load changes all exception pointers */
183 138 STTS(%rsi) /* trap on next fpu touch */
184 139 1: rep; ret /* use 2 byte return instruction when branch target */
185 140 /* AMD Software Optimization Guide - Section 6.2 */
186 141 SET_SIZE(fpxsave_excp_clr_ctxt)
187 142
188 143 ENTRY_NP(xsave_excp_clr_ctxt)
189 144 cmpl $FPU_EN, FPU_CTX_FPU_FLAGS(%rdi)
190 145 jne 1f
191 146 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%rdi)
192 147 movl FPU_CTX_FPU_XSAVE_MASK(%rdi), %eax
193 148 movl FPU_CTX_FPU_XSAVE_MASK+4(%rdi), %edx
194 149 movq FPU_CTX_FPU_REGS(%rdi), %rsi /* fpu_regs.kfpu_u.kfpu_xs ptr */
195 150 xsave (%rsi)
196 151 btw $7, FXSAVE_STATE_FSW(%rsi) /* Test saved ES bit */
197 152 jnc 0f /* jump if ES = 0 */
198 153 fnclex /* clear pending x87 exceptions */
199 154 0: ffree %st(7) /* clear tag bit to remove possible stack overflow */
200 155 fildl .fpzero_const(%rip) /* dummy load changes all excp. pointers */
201 156 STTS(%rsi) /* trap on next fpu touch */
202 157 1: ret
203 158 SET_SIZE(xsave_excp_clr_ctxt)
204 159
205 160 ENTRY_NP(xsaveopt_excp_clr_ctxt)
206 161 cmpl $FPU_EN, FPU_CTX_FPU_FLAGS(%rdi)
207 162 jne 1f
208 163 movl $_CONST(FPU_VALID|FPU_EN), FPU_CTX_FPU_FLAGS(%rdi)
209 164 movl FPU_CTX_FPU_XSAVE_MASK(%rdi), %eax
210 165 movl FPU_CTX_FPU_XSAVE_MASK+4(%rdi), %edx
211 166 movq FPU_CTX_FPU_REGS(%rdi), %rsi /* fpu_regs.kfpu_u.kfpu_xs ptr */
212 167 xsaveopt (%rsi)
213 168 btw $7, FXSAVE_STATE_FSW(%rsi) /* Test saved ES bit */
214 169 jnc 0f /* jump if ES = 0 */
215 170 fnclex /* clear pending x87 exceptions */
216 171 0: ffree %st(7) /* clear tag bit to remove possible stack overflow */
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217 172 fildl .fpzero_const(%rip) /* dummy load changes all excp. pointers */
218 173 STTS(%rsi) /* trap on next fpu touch */
219 174 1: ret
220 175 SET_SIZE(xsaveopt_excp_clr_ctxt)
221 176
222 177 .align 8
223 178 .fpzero_const:
224 179 .4byte 0x0
225 180 .4byte 0x0
226 181
227 -#endif /* __lint */
228 182
229 -
230 -#if defined(__lint)
231 -
232 -/*ARGSUSED*/
233 -void
234 -fpsave(struct fnsave_state *f)
235 -{}
236 -
237 -/*ARGSUSED*/
238 -void
239 -fpxsave(struct fxsave_state *f)
240 -{}
241 -
242 -/*ARGSUSED*/
243 -void
244 -xsave(struct xsave_state *f, uint64_t m)
245 -{}
246 -
247 -/*ARGSUSED*/
248 -void
249 -xsaveopt(struct xsave_state *f, uint64_t m)
250 -{}
251 -
252 -#else /* __lint */
253 -
254 183 ENTRY_NP(fpxsave)
255 184 CLTS
256 185 fxsaveq (%rdi)
257 186 fninit /* clear exceptions, init x87 tags */
258 187 STTS(%rdi) /* set TS bit in %cr0 (disable FPU) */
259 188 ret
260 189 SET_SIZE(fpxsave)
261 190
262 191 ENTRY_NP(xsave)
263 192 CLTS
264 193 movl %esi, %eax /* bv mask */
265 194 movq %rsi, %rdx
266 195 shrq $32, %rdx
267 196 xsave (%rdi)
268 197
269 198 fninit /* clear exceptions, init x87 tags */
270 199 STTS(%rdi) /* set TS bit in %cr0 (disable FPU) */
271 200 ret
272 201 SET_SIZE(xsave)
273 202
274 203 ENTRY_NP(xsaveopt)
275 204 CLTS
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276 205 movl %esi, %eax /* bv mask */
277 206 movq %rsi, %rdx
278 207 shrq $32, %rdx
279 208 xsaveopt (%rdi)
280 209
281 210 fninit /* clear exceptions, init x87 tags */
282 211 STTS(%rdi) /* set TS bit in %cr0 (disable FPU) */
283 212 ret
284 213 SET_SIZE(xsaveopt)
285 214
286 -#endif /* __lint */
287 -
288 215 /*
289 216 * These functions are used when restoring the FPU as part of the epilogue of a
290 217 * context switch.
291 218 */
292 219
293 -#if defined(__lint)
294 -
295 -/*ARGSUSED*/
296 -void
297 -fpxrestore_ctxt(void *arg)
298 -{}
299 -
300 -/*ARGSUSED*/
301 -void
302 -xrestore_ctxt(void *arg)
303 -{}
304 -
305 -#else /* __lint */
306 -
307 220 ENTRY(fpxrestore_ctxt)
308 221 cmpl $_CONST(FPU_EN|FPU_VALID), FPU_CTX_FPU_FLAGS(%rdi)
309 222 jne 1f
310 223 movl $_CONST(FPU_EN), FPU_CTX_FPU_FLAGS(%rdi)
311 224 movq FPU_CTX_FPU_REGS(%rdi), %rdi /* fpu_regs.kfpu_u.kfpu_fx ptr */
312 225 CLTS
313 226 fxrstorq (%rdi)
314 227 1:
315 228 ret
316 229 SET_SIZE(fpxrestore_ctxt)
317 230
318 231 ENTRY(xrestore_ctxt)
319 232 cmpl $_CONST(FPU_EN|FPU_VALID), FPU_CTX_FPU_FLAGS(%rdi)
320 233 jne 1f
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321 234 movl $_CONST(FPU_EN), FPU_CTX_FPU_FLAGS(%rdi)
322 235 movl FPU_CTX_FPU_XSAVE_MASK(%rdi), %eax /* xsave flags in EDX:EAX */
323 236 movl FPU_CTX_FPU_XSAVE_MASK+4(%rdi), %edx
324 237 movq FPU_CTX_FPU_REGS(%rdi), %rdi /* fpu_regs.kfpu_u.kfpu_xs ptr */
325 238 CLTS
326 239 xrstor (%rdi)
327 240 1:
328 241 ret
329 242 SET_SIZE(xrestore_ctxt)
330 243
331 -#endif /* __lint */
332 244
333 -
334 -#if defined(__lint)
335 -
336 -/*ARGSUSED*/
337 -void
338 -fpxrestore(struct fxsave_state *f)
339 -{}
340 -
341 -/*ARGSUSED*/
342 -void
343 -xrestore(struct xsave_state *f, uint64_t m)
344 -{}
345 -
346 -#else /* __lint */
347 -
348 245 ENTRY_NP(fpxrestore)
349 246 CLTS
350 247 fxrstorq (%rdi)
351 248 ret
352 249 SET_SIZE(fpxrestore)
353 250
354 251 ENTRY_NP(xrestore)
355 252 CLTS
356 253 movl %esi, %eax /* bv mask */
357 254 movq %rsi, %rdx
358 255 shrq $32, %rdx
359 256 xrstor (%rdi)
360 257 ret
361 258 SET_SIZE(xrestore)
362 259
363 -#endif /* __lint */
364 -
365 260 /*
366 261 * Disable the floating point unit.
367 262 */
368 263
369 -#if defined(__lint)
370 -
371 -void
372 -fpdisable(void)
373 -{}
374 -
375 -#else /* __lint */
376 -
377 264 ENTRY_NP(fpdisable)
378 265 STTS(%rdi) /* set TS bit in %cr0 (disable FPU) */
379 266 ret
380 267 SET_SIZE(fpdisable)
381 268
382 -#endif /* __lint */
383 -
384 269 /*
385 270 * Initialize the fpu hardware.
386 271 */
387 272
388 -#if defined(__lint)
389 -
390 -void
391 -fpinit(void)
392 -{}
393 -
394 -#else /* __lint */
395 -
396 273 ENTRY_NP(fpinit)
397 274 CLTS
398 275 cmpl $FP_XSAVE, fp_save_mech
399 276 je 1f
400 277
401 278 /* fxsave */
402 279 leaq sse_initial(%rip), %rax
403 280 fxrstorq (%rax) /* load clean initial state */
404 281 ret
405 282
406 283 1: /* xsave */
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407 284 leaq avx_initial(%rip), %rcx
408 285 xorl %edx, %edx
409 286 movl $XFEATURE_AVX, %eax
410 287 bt $X86FSET_AVX, x86_featureset
411 288 cmovael %edx, %eax
412 289 orl $(XFEATURE_LEGACY_FP | XFEATURE_SSE), %eax
413 290 xrstor (%rcx)
414 291 ret
415 292 SET_SIZE(fpinit)
416 293
417 -#endif /* __lint */
418 -
419 294 /*
420 295 * Clears FPU exception state.
421 296 * Returns the FP status word.
422 297 */
423 298
424 -#if defined(__lint)
425 -
426 -uint32_t
427 -fperr_reset(void)
428 -{ return (0); }
429 -
430 -uint32_t
431 -fpxerr_reset(void)
432 -{ return (0); }
433 -
434 -#else /* __lint */
435 -
436 299 ENTRY_NP(fperr_reset)
437 300 CLTS
438 301 xorl %eax, %eax
439 302 fnstsw %ax
440 303 fnclex
441 304 ret
442 305 SET_SIZE(fperr_reset)
443 306
444 307 ENTRY_NP(fpxerr_reset)
445 308 pushq %rbp
446 309 movq %rsp, %rbp
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447 310 subq $0x10, %rsp /* make some temporary space */
448 311 CLTS
449 312 stmxcsr (%rsp)
450 313 movl (%rsp), %eax
451 314 andl $_BITNOT(SSE_MXCSR_EFLAGS), (%rsp)
452 315 ldmxcsr (%rsp) /* clear processor exceptions */
453 316 leave
454 317 ret
455 318 SET_SIZE(fpxerr_reset)
456 319
457 -#endif /* __lint */
458 -
459 -#if defined(__lint)
460 -
461 -uint32_t
462 -fpgetcwsw(void)
463 -{
464 - return (0);
465 -}
466 -
467 -#else /* __lint */
468 -
469 320 ENTRY_NP(fpgetcwsw)
470 321 pushq %rbp
471 322 movq %rsp, %rbp
472 323 subq $0x10, %rsp /* make some temporary space */
473 324 CLTS
474 325 fnstsw (%rsp) /* store the status word */
475 326 fnstcw 2(%rsp) /* store the control word */
476 327 movl (%rsp), %eax /* put both in %eax */
477 328 leave
478 329 ret
479 330 SET_SIZE(fpgetcwsw)
480 331
481 -#endif /* __lint */
482 -
483 332 /*
484 333 * Returns the MXCSR register.
485 334 */
486 335
487 -#if defined(__lint)
488 -
489 -uint32_t
490 -fpgetmxcsr(void)
491 -{
492 - return (0);
493 -}
494 -
495 -#else /* __lint */
496 -
497 336 ENTRY_NP(fpgetmxcsr)
498 337 pushq %rbp
499 338 movq %rsp, %rbp
500 339 subq $0x10, %rsp /* make some temporary space */
501 340 CLTS
502 341 stmxcsr (%rsp)
503 342 movl (%rsp), %eax
504 343 leave
505 344 ret
506 345 SET_SIZE(fpgetmxcsr)
507 346
508 -#endif /* __lint */
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