1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26 
  27 /*
  28  * Hypervisor calls called by niu leaf driver.
  29  */
  30 
  31 #include <sys/asm_linkage.h>
  32 #include <sys/hypervisor_api.h>
  33 #include <sys/nxge/nxge_impl.h>
  34 
  35 #if defined(sun4v)
  36 
  37 /*
  38  * NIU HV API v1.0 definitions
  39  */
  40 #define N2NIU_RX_LP_SET         0x142
  41 #define N2NIU_RX_LP_GET         0x143
  42 #define N2NIU_TX_LP_SET         0x144
  43 #define N2NIU_TX_LP_GET         0x145
  44 
  45 /*
  46  * NIU HV API v1.1 definitions
  47  */
  48 #define N2NIU_VR_ASSIGN         0x146
  49 #define N2NIU_VR_UNASSIGN       0x147
  50 #define N2NIU_VR_GETINFO        0x148
  51 
  52 #define N2NIU_VR_RX_DMA_ASSIGN          0x149
  53 #define N2NIU_VR_RX_DMA_UNASSIGN        0x14a
  54 #define N2NIU_VR_TX_DMA_ASSIGN          0x14b
  55 #define N2NIU_VR_TX_DMA_UNASSIGN        0x14c
  56 
  57 #define N2NIU_VR_GET_RX_MAP     0x14d
  58 #define N2NIU_VR_GET_TX_MAP     0x14e
  59 
  60 #define N2NIU_VRRX_SET_INO      0x150
  61 #define N2NIU_VRTX_SET_INO      0x151
  62 
  63 #define N2NIU_VRRX_GET_INFO     0x152
  64 #define N2NIU_VRTX_GET_INFO     0x153
  65 
  66 #define N2NIU_VRRX_LP_SET       0x154
  67 #define N2NIU_VRRX_LP_GET       0x155
  68 #define N2NIU_VRTX_LP_SET       0x156
  69 #define N2NIU_VRTX_LP_GET       0x157
  70 
  71 #define N2NIU_VRRX_PARAM_GET    0x158
  72 #define N2NIU_VRRX_PARAM_SET    0x159
  73 
  74 #define N2NIU_VRTX_PARAM_GET    0x15a
  75 #define N2NIU_VRTX_PARAM_SET    0x15b
  76 
  77 /*
  78  * The new set of HV APIs to provide the ability
  79  * of a domain to manage multiple NIU resources at once to
  80  * support the KT familty chip having up to 4 NIUs
  81  * per system. The trap # will be the same as those defined
  82  * before 2.0
  83  */
  84 #define N2NIU_CFGH_RX_LP_SET    0x142
  85 #define N2NIU_CFGH_TX_LP_SET    0x143
  86 #define N2NIU_CFGH_RX_LP_GET    0x144
  87 #define N2NIU_CFGH_TX_LP_GET    0x145
  88 #define N2NIU_CFGH_VR_ASSIGN    0x146
  89 
  90         /*
  91          * hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
  92          *      uint64_t raddr, uint64_t size)
  93          */
  94         ENTRY(hv_niu_rx_logical_page_conf)
  95         mov     N2NIU_RX_LP_CONF, %o5
  96         ta      FAST_TRAP
  97         retl
  98         nop
  99         SET_SIZE(hv_niu_rx_logical_page_conf)
 100 
 101         /*
 102          * hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
 103          *      uint64_t *raddr, uint64_t *size)
 104          */
 105         ENTRY(hv_niu_rx_logical_page_info)
 106         mov     %o2, %g1
 107         mov     %o3, %g2
 108         mov     N2NIU_RX_LP_INFO, %o5
 109         ta      FAST_TRAP
 110         stx     %o1, [%g1]
 111         retl
 112         stx     %o2, [%g2]
 113         SET_SIZE(hv_niu_rx_logical_page_info)
 114 
 115         /*
 116          * hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
 117          *      uint64_t raddr, uint64_t size)
 118          */
 119         ENTRY(hv_niu_tx_logical_page_conf)
 120         mov     N2NIU_TX_LP_CONF, %o5
 121         ta      FAST_TRAP
 122         retl
 123         nop
 124         SET_SIZE(hv_niu_tx_logical_page_conf)
 125 
 126         /*
 127          * hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx,
 128          *      uint64_t *raddr, uint64_t *size)
 129          */
 130         ENTRY(hv_niu_tx_logical_page_info)
 131         mov     %o2, %g1
 132         mov     %o3, %g2
 133         mov     N2NIU_TX_LP_INFO, %o5
 134         ta      FAST_TRAP
 135         stx     %o1, [%g1]
 136         retl
 137         stx     %o2, [%g2]
 138         SET_SIZE(hv_niu_tx_logical_page_info)
 139 
 140         /*
 141          * hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id,
 142          *      uint32_t *cookie)
 143          */
 144         ENTRY(hv_niu_vr_assign)
 145         mov     %o2, %g1
 146         mov     N2NIU_VR_ASSIGN, %o5
 147         ta      FAST_TRAP
 148         retl
 149         stw     %o1, [%g1]
 150         SET_SIZE(hv_niu_vr_assign)
 151 
 152         /*
 153          * hv_niu_vr_unassign(uint32_t cookie)
 154          */
 155         ENTRY(hv_niu_vr_unassign)
 156         mov     N2NIU_VR_UNASSIGN, %o5
 157         ta      FAST_TRAP
 158         retl
 159         nop
 160         SET_SIZE(hv_niu_vr_unassign)
 161 
 162         /*
 163          * hv_niu_vr_getinfo(uint32_t cookie, uint64_t &real_start,
 164          *      uint64_t &size)
 165          */
 166         ENTRY(hv_niu_vr_getinfo)
 167         mov     %o1, %g1
 168         mov     %o2, %g2
 169         mov     N2NIU_VR_GETINFO, %o5
 170         ta      FAST_TRAP
 171         stx     %o1, [%g1]
 172         retl
 173         stx     %o2, [%g2]
 174         SET_SIZE(hv_niu_vr_getinfo)
 175 
 176         /*
 177          * hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
 178          */
 179         ENTRY(hv_niu_vr_get_rxmap)
 180         mov     %o1, %g1
 181         mov     N2NIU_VR_GET_RX_MAP, %o5
 182         ta      FAST_TRAP
 183         retl
 184         stx     %o1, [%g1]
 185         SET_SIZE(hv_niu_vr_get_rxmap)
 186 
 187         /*
 188          * hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
 189          */
 190         ENTRY(hv_niu_vr_get_txmap)
 191         mov     %o1, %g1
 192         mov     N2NIU_VR_GET_TX_MAP, %o5
 193         ta      FAST_TRAP
 194         retl
 195         stx     %o1, [%g1]
 196         SET_SIZE(hv_niu_vr_get_txmap)
 197 
 198         /*
 199          * hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx,
 200          *      uint64_t *vchidx)
 201          */
 202         ENTRY(hv_niu_rx_dma_assign)
 203         mov     %o2, %g1
 204         mov     N2NIU_VR_RX_DMA_ASSIGN, %o5
 205         ta      FAST_TRAP
 206         retl
 207         stx     %o1, [%g1]
 208         SET_SIZE(hv_niu_rx_dma_assign)
 209 
 210         /*
 211          * hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx)
 212          */
 213         ENTRY(hv_niu_rx_dma_unassign)
 214         mov     N2NIU_VR_RX_DMA_UNASSIGN, %o5
 215         ta      FAST_TRAP
 216         retl
 217         nop
 218         SET_SIZE(hv_niu_rx_dma_unassign)
 219 
 220         /*
 221          * hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx,
 222          *      uint64_t *vchidx)
 223          */
 224         ENTRY(hv_niu_tx_dma_assign)
 225         mov     %o2, %g1
 226         mov     N2NIU_VR_TX_DMA_ASSIGN, %o5
 227         ta      FAST_TRAP
 228         retl
 229         stx     %o1, [%g1]
 230         SET_SIZE(hv_niu_tx_dma_assign)
 231 
 232         /*
 233          * hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t vchidx)
 234          */
 235         ENTRY(hv_niu_tx_dma_unassign)
 236         mov     N2NIU_VR_TX_DMA_UNASSIGN, %o5
 237         ta      FAST_TRAP
 238         retl
 239         nop
 240         SET_SIZE(hv_niu_tx_dma_unassign)
 241 
 242         /*
 243          * hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx,
 244          *      uint64_t pgidx, uint64_t raddr, uint64_t size)
 245          */
 246         ENTRY(hv_niu_vrrx_logical_page_conf)
 247         mov     N2NIU_VRRX_LP_SET, %o5
 248         ta      FAST_TRAP
 249         retl
 250         nop
 251         SET_SIZE(hv_niu_vrrx_logical_page_conf)
 252 
 253         /*
 254          * hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx,
 255          *      uint64_t pgidx, uint64_t *raddr, uint64_t *size)
 256          */
 257         ENTRY(hv_niu_vrrx_logical_page_info)
 258         mov     %o3, %g1
 259         mov     %o4, %g2
 260         mov     N2NIU_VRRX_LP_GET, %o5
 261         ta      FAST_TRAP
 262         stx     %o1, [%g1]
 263         retl
 264         stx     %o2, [%g2]
 265         SET_SIZE(hv_niu_vrrx_logical_page_info)
 266 
 267         /*
 268          * hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx,
 269          *      uint64_t pgidx, uint64_t raddr, uint64_t size)
 270          */
 271         ENTRY(hv_niu_vrtx_logical_page_conf)
 272         mov     N2NIU_VRTX_LP_SET, %o5
 273         ta      FAST_TRAP
 274         retl
 275         nop
 276         SET_SIZE(hv_niu_vrtx_logical_page_conf)
 277 
 278         /*
 279          * hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx,
 280          *      uint64_t pgidx, uint64_t *raddr, uint64_t *size)
 281          */
 282         ENTRY(hv_niu_vrtx_logical_page_info)
 283         mov     %o3, %g1
 284         mov     %o4, %g2
 285         mov     N2NIU_VRTX_LP_GET, %o5
 286         ta      FAST_TRAP
 287         stx     %o1, [%g1]
 288         retl
 289         stx     %o2, [%g2]
 290         SET_SIZE(hv_niu_vrtx_logical_page_info)
 291 
 292         /*
 293          * hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx,
 294          *      uint64_t *group, uint64_t *logdev)
 295          */
 296         ENTRY(hv_niu_vrrx_getinfo)
 297         mov     %o2, %g1
 298         mov     %o3, %g2
 299         mov     N2NIU_VRRX_GET_INFO, %o5
 300         ta      FAST_TRAP
 301         stx     %o2, [%g2]
 302         retl
 303         stx     %o1, [%g1]
 304         SET_SIZE(hv_niu_vrrx_getinfo)
 305 
 306         /*
 307          * hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx,
 308          *      uint64_t *group, uint64_t *logdev)
 309          */
 310         ENTRY(hv_niu_vrtx_getinfo)
 311         mov     %o2, %g1
 312         mov     %o3, %g2
 313         mov     N2NIU_VRTX_GET_INFO, %o5
 314         ta      FAST_TRAP
 315         stx     %o2, [%g2]
 316         retl
 317         stx     %o1, [%g1]
 318         SET_SIZE(hv_niu_vrtx_getinfo)
 319 
 320         /*
 321          * hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
 322          */
 323         ENTRY(hv_niu_vrrx_set_ino)
 324         mov     N2NIU_VRRX_SET_INO, %o5
 325         ta      FAST_TRAP
 326         retl
 327         nop
 328         SET_SIZE(hv_niu_vrrx_set_ino)
 329 
 330         /*
 331          * hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
 332          */
 333         ENTRY(hv_niu_vrtx_set_ino)
 334         mov     N2NIU_VRTX_SET_INO, %o5
 335         ta      FAST_TRAP
 336         retl
 337         nop
 338         SET_SIZE(hv_niu_vrtx_set_ino)
 339 
 340         /*
 341          * hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx,
 342          *      uint64_t param, uint64_t *value)
 343          *
 344          */
 345         ENTRY(hv_niu_vrrx_param_get)
 346         mov     %o3, %g1
 347         mov     N2NIU_VRRX_PARAM_GET, %o5
 348         ta      FAST_TRAP
 349         retl
 350         stx     %o1, [%g1]
 351         SET_SIZE(hv_niu_vrrx_param_get)
 352 
 353         /*
 354          * hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx,
 355          *      uint64_t param, uint64_t value)
 356          *
 357          */
 358         ENTRY(hv_niu_vrrx_param_set)
 359         mov     N2NIU_VRRX_PARAM_SET, %o5
 360         ta      FAST_TRAP
 361         retl
 362         nop
 363         SET_SIZE(hv_niu_vrrx_param_set)
 364 
 365         /*
 366          * hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx,
 367          *      uint64_t param, uint64_t *value)
 368          *
 369          */
 370         ENTRY(hv_niu_vrtx_param_get)
 371         mov     %o3, %g1
 372         mov     N2NIU_VRTX_PARAM_GET, %o5
 373         ta      FAST_TRAP
 374         retl
 375         stx     %o1, [%g1]
 376         SET_SIZE(hv_niu_vrtx_param_get)
 377 
 378         /*
 379          * hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx,
 380          *      uint64_t param, uint64_t value)
 381          *
 382          */
 383         ENTRY(hv_niu_vrtx_param_set)
 384         mov     N2NIU_VRTX_PARAM_SET, %o5
 385         ta      FAST_TRAP
 386         retl
 387         nop
 388         SET_SIZE(hv_niu_vrtx_param_set)
 389 
 390         /*
 391          * Interfaces functions which require the configuration handle.
 392          */
 393         /*
 394          * hv_niu__cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
 395          *    uint64_t pgidx, uint64_t raddr, uint64_t size)
 396          */
 397         ENTRY(hv_niu_cfgh_rx_logical_page_conf)
 398         mov     N2NIU_RX_LP_CONF, %o5
 399         ta      FAST_TRAP
 400         retl
 401         nop
 402         SET_SIZE(hv_niu_cfgh_rx_logical_page_conf)
 403 
 404         /*
 405          * hv_niu__cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx,
 406          *    uint64_t pgidx, uint64_t *raddr, uint64_t *size)
 407          */
 408         ENTRY(hv_niu_cfgh_rx_logical_page_info)
 409         mov     %o3, %g1
 410         mov     %o4, %g2
 411         mov     N2NIU_RX_LP_INFO, %o5
 412         ta      FAST_TRAP
 413         stx     %o1, [%g1]
 414         retl
 415         stx     %o2, [%g2]
 416         SET_SIZE(hv_niu_cfgh_rx_logical_page_info)
 417 
 418         /*
 419          * hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
 420          *    uint64_t pgidx, uint64_t raddr, uint64_t size)
 421          */
 422         ENTRY(hv_niu_cfgh_tx_logical_page_conf)
 423         mov     N2NIU_TX_LP_CONF, %o5
 424         ta      FAST_TRAP
 425         retl
 426         nop
 427         SET_SIZE(hv_niu_cfgh_tx_logical_page_conf)
 428 
 429         /*
 430          * hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx,
 431          *    uint64_t pgidx, uint64_t *raddr, uint64_t *size)
 432          */
 433         ENTRY(hv_niu_cfgh_tx_logical_page_info)
 434         mov     %o3, %g1
 435         mov     %o4, %g2
 436         mov     N2NIU_TX_LP_INFO, %o5
 437         ta      FAST_TRAP
 438         stx     %o1, [%g1]
 439         retl
 440         stx     %o2, [%g2]
 441         SET_SIZE(hv_niu_cfgh_tx_logical_page_info)
 442 
 443         /*
 444          * hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id,
 445          *     uint32_t *cookie)
 446          */
 447         ENTRY(hv_niu_cfgh_vr_assign)
 448         mov     %o3, %g1
 449         mov     N2NIU_VR_ASSIGN, %o5
 450         ta      FAST_TRAP
 451         retl
 452         stw     %o1, [%g1]
 453         SET_SIZE(hv_niu_cfgh_vr_assign)
 454 
 455 #endif /*defined(sun4v)*/