16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1, (the "License").
26
27 * You may not use this file except in compliance with the License.
28
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35
36 #include "bcm_osal.h"
37 #include "ecore.h"
38 #include "ecore_sp_commands.h"
39 #include "ecore_dcbx.h"
40 #include "ecore_cxt.h"
41 #include "ecore_gtt_reg_addr.h"
42 #include "ecore_iro.h"
43 #ifdef CONFIG_ECORE_ROCE
44 #include "ecore_roce.h"
45 #endif
46 #include "ecore_iov_api.h"
47
48 #define ECORE_DCBX_MAX_MIB_READ_TRY (100)
49 #define ECORE_ETH_TYPE_DEFAULT (0)
50 #define ECORE_ETH_TYPE_ROCE (0x8915)
51 #define ECORE_UDP_PORT_TYPE_ROCE_V2 (0x12B7)
52 #define ECORE_ETH_TYPE_FCOE (0x8906)
53 #define ECORE_TCP_PORT_ISCSI (0xCBC)
54
55 #define ECORE_DCBX_INVALID_PRIORITY 0xFF
224 p_data->arr[type].update = UPDATE_DCB_DSCP;
225 else if (enable)
226 p_data->arr[type].update = UPDATE_DCB;
227 else
228 p_data->arr[type].update = DONT_UPDATE_DCB_DSCP;
229
230 /* QM reconf data */
231 if (p_hwfn->hw_info.personality == personality)
232 p_hwfn->hw_info.offload_tc = tc;
233 }
234
235 /* Update app protocol data and hw_info fields with the TLV info */
236 static void
237 ecore_dcbx_update_app_info(struct ecore_dcbx_results *p_data,
238 struct ecore_hwfn *p_hwfn,
239 bool enable, u8 prio, u8 tc,
240 enum dcbx_protocol_type type)
241 {
242 enum ecore_pci_personality personality;
243 enum dcbx_protocol_type id;
244 char *name;
245 int i;
246
247 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) {
248 id = ecore_dcbx_app_update[i].id;
249
250 if (type != id)
251 continue;
252
253 personality = ecore_dcbx_app_update[i].personality;
254 name = ecore_dcbx_app_update[i].name;
255
256 ecore_dcbx_set_params(p_data, p_hwfn, enable,
257 prio, tc, type, personality);
258 }
259 }
260
261 static enum _ecore_status_t
262 ecore_dcbx_get_app_priority(u8 pri_bitmap, u8 *priority)
263 {
264 u32 pri_mask, pri = ECORE_MAX_PFC_PRIORITIES;
265 u32 index = ECORE_MAX_PFC_PRIORITIES - 1;
266 enum _ecore_status_t rc = ECORE_SUCCESS;
267
268 /* Bitmap 1 corresponds to priority 0, return priority 0 */
269 if (pri_bitmap == 1) {
270 *priority = 0;
271 return rc;
272 }
273
274 /* Choose the highest priority */
982 * Read updated MIB.
983 * Reconfigure QM and invoke PF update ramrod command if operational MIB
984 * change is detected.
985 */
986 enum _ecore_status_t
987 ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
988 enum ecore_mib_read_type type)
989 {
990 enum _ecore_status_t rc = ECORE_SUCCESS;
991
992 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);
993 if (rc)
994 return rc;
995
996 if (type == ECORE_DCBX_OPERATIONAL_MIB) {
997 ecore_dcbx_get_dscp_params(p_hwfn, p_ptt,
998 &p_hwfn->p_dcbx_info->get);
999
1000 rc = ecore_dcbx_process_mib_info(p_hwfn);
1001 if (!rc) {
1002 bool enabled;
1003
1004 /* reconfigure tcs of QM queues according
1005 * to negotiation results
1006 */
1007 ecore_qm_reconf(p_hwfn, p_ptt);
1008
1009 /* update storm FW with negotiation results */
1010 ecore_sp_pf_update_dcbx(p_hwfn);
1011
1012 /* set eagle enigne 1 flow control workaround
1013 * according to negotiation results
1014 */
1015 enabled = p_hwfn->p_dcbx_info->results.dcbx_enabled;
1016
1017 #ifdef CONFIG_ECORE_ROCE
1018 /* for roce PFs, we may want to enable/disable DPM
1019 * when DCBx change occurs
1020 */
1021 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn))
1022 ecore_roce_dpm_dcbx(p_hwfn, p_ptt);
|
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1, (the "License").
26
27 * You may not use this file except in compliance with the License.
28
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35
36 /*
37 * Copyright 2018 Joyent, Inc.
38 */
39
40 #include "bcm_osal.h"
41 #include "ecore.h"
42 #include "ecore_sp_commands.h"
43 #include "ecore_dcbx.h"
44 #include "ecore_cxt.h"
45 #include "ecore_gtt_reg_addr.h"
46 #include "ecore_iro.h"
47 #ifdef CONFIG_ECORE_ROCE
48 #include "ecore_roce.h"
49 #endif
50 #include "ecore_iov_api.h"
51
52 #define ECORE_DCBX_MAX_MIB_READ_TRY (100)
53 #define ECORE_ETH_TYPE_DEFAULT (0)
54 #define ECORE_ETH_TYPE_ROCE (0x8915)
55 #define ECORE_UDP_PORT_TYPE_ROCE_V2 (0x12B7)
56 #define ECORE_ETH_TYPE_FCOE (0x8906)
57 #define ECORE_TCP_PORT_ISCSI (0xCBC)
58
59 #define ECORE_DCBX_INVALID_PRIORITY 0xFF
228 p_data->arr[type].update = UPDATE_DCB_DSCP;
229 else if (enable)
230 p_data->arr[type].update = UPDATE_DCB;
231 else
232 p_data->arr[type].update = DONT_UPDATE_DCB_DSCP;
233
234 /* QM reconf data */
235 if (p_hwfn->hw_info.personality == personality)
236 p_hwfn->hw_info.offload_tc = tc;
237 }
238
239 /* Update app protocol data and hw_info fields with the TLV info */
240 static void
241 ecore_dcbx_update_app_info(struct ecore_dcbx_results *p_data,
242 struct ecore_hwfn *p_hwfn,
243 bool enable, u8 prio, u8 tc,
244 enum dcbx_protocol_type type)
245 {
246 enum ecore_pci_personality personality;
247 enum dcbx_protocol_type id;
248 int i;
249
250 for (i = 0; i < OSAL_ARRAY_SIZE(ecore_dcbx_app_update); i++) {
251 id = ecore_dcbx_app_update[i].id;
252
253 if (type != id)
254 continue;
255
256 personality = ecore_dcbx_app_update[i].personality;
257
258 ecore_dcbx_set_params(p_data, p_hwfn, enable,
259 prio, tc, type, personality);
260 }
261 }
262
263 static enum _ecore_status_t
264 ecore_dcbx_get_app_priority(u8 pri_bitmap, u8 *priority)
265 {
266 u32 pri_mask, pri = ECORE_MAX_PFC_PRIORITIES;
267 u32 index = ECORE_MAX_PFC_PRIORITIES - 1;
268 enum _ecore_status_t rc = ECORE_SUCCESS;
269
270 /* Bitmap 1 corresponds to priority 0, return priority 0 */
271 if (pri_bitmap == 1) {
272 *priority = 0;
273 return rc;
274 }
275
276 /* Choose the highest priority */
984 * Read updated MIB.
985 * Reconfigure QM and invoke PF update ramrod command if operational MIB
986 * change is detected.
987 */
988 enum _ecore_status_t
989 ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
990 enum ecore_mib_read_type type)
991 {
992 enum _ecore_status_t rc = ECORE_SUCCESS;
993
994 rc = ecore_dcbx_read_mib(p_hwfn, p_ptt, type);
995 if (rc)
996 return rc;
997
998 if (type == ECORE_DCBX_OPERATIONAL_MIB) {
999 ecore_dcbx_get_dscp_params(p_hwfn, p_ptt,
1000 &p_hwfn->p_dcbx_info->get);
1001
1002 rc = ecore_dcbx_process_mib_info(p_hwfn);
1003 if (!rc) {
1004 bool enabled __unused;
1005
1006 /* reconfigure tcs of QM queues according
1007 * to negotiation results
1008 */
1009 ecore_qm_reconf(p_hwfn, p_ptt);
1010
1011 /* update storm FW with negotiation results */
1012 ecore_sp_pf_update_dcbx(p_hwfn);
1013
1014 /* set eagle enigne 1 flow control workaround
1015 * according to negotiation results
1016 */
1017 enabled = p_hwfn->p_dcbx_info->results.dcbx_enabled;
1018
1019 #ifdef CONFIG_ECORE_ROCE
1020 /* for roce PFs, we may want to enable/disable DPM
1021 * when DCBx change occurs
1022 */
1023 if (ECORE_IS_ROCE_PERSONALITY(p_hwfn))
1024 ecore_roce_dpm_dcbx(p_hwfn, p_ptt);
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