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9723 provide support for VMM's GDT handling
Reviewed by: Robert Mustacchi <rm@joyent.com>
Reviewed by: Patrick Mooney <patrick.mooney@joyent.com>
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--- old/usr/src/uts/intel/sys/x86_archext.h
+++ new/usr/src/uts/intel/sys/x86_archext.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright 2018 Joyent, Inc.
31 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 34 * Copyright 2018 Nexenta Systems, Inc.
35 35 */
36 36
37 37 #ifndef _SYS_X86_ARCHEXT_H
38 38 #define _SYS_X86_ARCHEXT_H
39 39
40 40 #if !defined(_ASM)
41 41 #include <sys/regset.h>
42 42 #include <sys/processor.h>
43 43 #include <vm/seg_enum.h>
44 44 #include <vm/page.h>
45 45 #endif /* _ASM */
46 46
47 47 #ifdef __cplusplus
48 48 extern "C" {
49 49 #endif
50 50
51 51 /*
52 52 * cpuid instruction feature flags in %edx (standard function 1)
53 53 */
54 54
55 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
56 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
57 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
58 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
59 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
60 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
61 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
62 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
63 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
64 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
65 65 /* 0x400 - reserved */
66 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
67 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
68 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 75 /* 0x100000 - reserved */
76 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87 87
88 88 /*
89 89 * cpuid instruction feature flags in %ecx (standard function 1)
90 90 */
91 91
92 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 103 /* 0x00000800 - reserved */
104 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 108 /* 0x00010000 - reserved */
109 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
117 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
118 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
119 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
120 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
121 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
122 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
123 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
124 124
125 125 /*
126 126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
127 127 */
128 128
129 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
130 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
131 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
132 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
133 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
134 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
135 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
136 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
137 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
138 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
139 139 /* 0x00000400 - sysc on K6m6 */
140 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
141 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
142 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
143 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
144 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
145 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
146 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
147 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
148 148 /* 0x00040000 - reserved */
149 149 /* 0x00080000 - reserved */
150 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
151 151 /* 0x00200000 - reserved */
152 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
153 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
154 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
155 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
156 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
157 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
158 158 /* 0x10000000 - reserved */
159 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
160 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
161 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
162 162
163 163 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
164 164 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
165 165 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
166 166 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
167 167 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
168 168 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
169 169 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
170 170 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
171 171 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
172 172 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
173 173 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
174 174 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: Extended AVX */
175 175 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
176 176 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
177 177 /* 0x00004000 - reserved */
178 178 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
179 179 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
180 180 /* 0x00020000 - reserved */
181 181 /* 0x00040000 - reserved */
182 182 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
183 183 /* 0x00100000 - reserved */
184 184 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
185 185 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
186 186
187 187 /*
188 188 * AMD uses %ebx for some of their features (extended function 0x80000008).
189 189 */
190 190 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x00000004 /* AMD: FP Err. Ptr. Zero */
191 191
192 192 /*
193 193 * Intel now seems to have claimed part of the "extended" function
194 194 * space that we previously for non-Intel implementors to use.
195 195 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
196 196 * is available in long mode i.e. what AMD indicate using bit 0.
197 197 * On the other hand, everything else is labelled as reserved.
198 198 */
199 199 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
200 200
201 201 /*
202 202 * Intel also uses cpuid leaf 7 to have additional instructions and features.
203 203 * Like some other leaves, but unlike the current ones we care about, it
204 204 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
205 205 * with the potential use of additional sub-leaves in the future, we now
206 206 * specifically label the EBX features with their leaf and sub-leaf.
207 207 */
208 208 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
209 209 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
210 210 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
211 211 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
212 212 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
213 213 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */
214 214 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
215 215 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
216 216 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
217 217 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
218 218 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
219 219 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
220 220 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
221 221 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
222 222 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
223 223 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
224 224 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
225 225 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
226 226 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
227 227 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
228 228
229 229 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
230 230 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
231 231 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
232 232 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
233 233 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
234 234
235 235 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
236 236 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
237 237 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
238 238 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
239 239 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
240 240
241 241 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
242 242 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
243 243
244 244 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
245 245 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
246 246
247 247 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
248 248 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
249 249
250 250 /*
251 251 * Intel also uses cpuid leaf 0xd to report additional instructions and features
252 252 * when the sub-leaf in %ecx == 1. We label these using the same convention as
253 253 * with leaf 7.
254 254 */
255 255 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
256 256 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
257 257 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
258 258
259 259 #define REG_PAT 0x277
260 260 #define REG_TSC 0x10 /* timestamp counter */
261 261 #define REG_APIC_BASE_MSR 0x1b
262 262 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
263 263
264 264 #if !defined(__xpv)
265 265 /*
266 266 * AMD C1E
267 267 */
268 268 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
269 269 #define AMD_ACTONCMPHALT_SHIFT 27
270 270 #define AMD_ACTONCMPHALT_MASK 3
271 271 #endif
272 272
273 273 #define MSR_DEBUGCTL 0x1d9
274 274
275 275 #define DEBUGCTL_LBR 0x01
276 276 #define DEBUGCTL_BTF 0x02
277 277
278 278 /* Intel P6, AMD */
279 279 #define MSR_LBR_FROM 0x1db
280 280 #define MSR_LBR_TO 0x1dc
281 281 #define MSR_LEX_FROM 0x1dd
282 282 #define MSR_LEX_TO 0x1de
283 283
284 284 /* Intel P4 (pre-Prescott, non P4 M) */
285 285 #define MSR_P4_LBSTK_TOS 0x1da
286 286 #define MSR_P4_LBSTK_0 0x1db
287 287 #define MSR_P4_LBSTK_1 0x1dc
288 288 #define MSR_P4_LBSTK_2 0x1dd
289 289 #define MSR_P4_LBSTK_3 0x1de
290 290
291 291 /* Intel Pentium M */
292 292 #define MSR_P6M_LBSTK_TOS 0x1c9
293 293 #define MSR_P6M_LBSTK_0 0x040
294 294 #define MSR_P6M_LBSTK_1 0x041
295 295 #define MSR_P6M_LBSTK_2 0x042
296 296 #define MSR_P6M_LBSTK_3 0x043
297 297 #define MSR_P6M_LBSTK_4 0x044
298 298 #define MSR_P6M_LBSTK_5 0x045
299 299 #define MSR_P6M_LBSTK_6 0x046
300 300 #define MSR_P6M_LBSTK_7 0x047
301 301
302 302 /* Intel P4 (Prescott) */
303 303 #define MSR_PRP4_LBSTK_TOS 0x1da
304 304 #define MSR_PRP4_LBSTK_FROM_0 0x680
305 305 #define MSR_PRP4_LBSTK_FROM_1 0x681
306 306 #define MSR_PRP4_LBSTK_FROM_2 0x682
307 307 #define MSR_PRP4_LBSTK_FROM_3 0x683
308 308 #define MSR_PRP4_LBSTK_FROM_4 0x684
309 309 #define MSR_PRP4_LBSTK_FROM_5 0x685
310 310 #define MSR_PRP4_LBSTK_FROM_6 0x686
311 311 #define MSR_PRP4_LBSTK_FROM_7 0x687
312 312 #define MSR_PRP4_LBSTK_FROM_8 0x688
313 313 #define MSR_PRP4_LBSTK_FROM_9 0x689
314 314 #define MSR_PRP4_LBSTK_FROM_10 0x68a
315 315 #define MSR_PRP4_LBSTK_FROM_11 0x68b
316 316 #define MSR_PRP4_LBSTK_FROM_12 0x68c
317 317 #define MSR_PRP4_LBSTK_FROM_13 0x68d
318 318 #define MSR_PRP4_LBSTK_FROM_14 0x68e
319 319 #define MSR_PRP4_LBSTK_FROM_15 0x68f
320 320 #define MSR_PRP4_LBSTK_TO_0 0x6c0
321 321 #define MSR_PRP4_LBSTK_TO_1 0x6c1
322 322 #define MSR_PRP4_LBSTK_TO_2 0x6c2
323 323 #define MSR_PRP4_LBSTK_TO_3 0x6c3
324 324 #define MSR_PRP4_LBSTK_TO_4 0x6c4
325 325 #define MSR_PRP4_LBSTK_TO_5 0x6c5
326 326 #define MSR_PRP4_LBSTK_TO_6 0x6c6
327 327 #define MSR_PRP4_LBSTK_TO_7 0x6c7
328 328 #define MSR_PRP4_LBSTK_TO_8 0x6c8
329 329 #define MSR_PRP4_LBSTK_TO_9 0x6c9
330 330 #define MSR_PRP4_LBSTK_TO_10 0x6ca
331 331 #define MSR_PRP4_LBSTK_TO_11 0x6cb
332 332 #define MSR_PRP4_LBSTK_TO_12 0x6cc
333 333 #define MSR_PRP4_LBSTK_TO_13 0x6cd
334 334 #define MSR_PRP4_LBSTK_TO_14 0x6ce
335 335 #define MSR_PRP4_LBSTK_TO_15 0x6cf
336 336
337 337 #define MCI_CTL_VALUE 0xffffffff
338 338
339 339 #define MTRR_TYPE_UC 0
340 340 #define MTRR_TYPE_WC 1
341 341 #define MTRR_TYPE_WT 4
342 342 #define MTRR_TYPE_WP 5
343 343 #define MTRR_TYPE_WB 6
344 344 #define MTRR_TYPE_UC_ 7
345 345
346 346 /*
347 347 * For Solaris we set up the page attritubute table in the following way:
348 348 * PAT0 Write-Back
349 349 * PAT1 Write-Through
350 350 * PAT2 Unchacheable-
351 351 * PAT3 Uncacheable
352 352 * PAT4 Write-Back
353 353 * PAT5 Write-Through
354 354 * PAT6 Write-Combine
355 355 * PAT7 Uncacheable
356 356 * The only difference from h/w default is entry 6.
357 357 */
358 358 #define PAT_DEFAULT_ATTRIBUTE \
359 359 ((uint64_t)MTRR_TYPE_WB | \
360 360 ((uint64_t)MTRR_TYPE_WT << 8) | \
361 361 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
362 362 ((uint64_t)MTRR_TYPE_UC << 24) | \
363 363 ((uint64_t)MTRR_TYPE_WB << 32) | \
364 364 ((uint64_t)MTRR_TYPE_WT << 40) | \
365 365 ((uint64_t)MTRR_TYPE_WC << 48) | \
366 366 ((uint64_t)MTRR_TYPE_UC << 56))
367 367
368 368 #define X86FSET_LARGEPAGE 0
369 369 #define X86FSET_TSC 1
370 370 #define X86FSET_MSR 2
371 371 #define X86FSET_MTRR 3
372 372 #define X86FSET_PGE 4
373 373 #define X86FSET_DE 5
374 374 #define X86FSET_CMOV 6
375 375 #define X86FSET_MMX 7
376 376 #define X86FSET_MCA 8
377 377 #define X86FSET_PAE 9
378 378 #define X86FSET_CX8 10
379 379 #define X86FSET_PAT 11
380 380 #define X86FSET_SEP 12
381 381 #define X86FSET_SSE 13
382 382 #define X86FSET_SSE2 14
383 383 #define X86FSET_HTT 15
384 384 #define X86FSET_ASYSC 16
385 385 #define X86FSET_NX 17
386 386 #define X86FSET_SSE3 18
387 387 #define X86FSET_CX16 19
388 388 #define X86FSET_CMP 20
389 389 #define X86FSET_TSCP 21
390 390 #define X86FSET_MWAIT 22
391 391 #define X86FSET_SSE4A 23
392 392 #define X86FSET_CPUID 24
393 393 #define X86FSET_SSSE3 25
394 394 #define X86FSET_SSE4_1 26
395 395 #define X86FSET_SSE4_2 27
396 396 #define X86FSET_1GPG 28
397 397 #define X86FSET_CLFSH 29
398 398 #define X86FSET_64 30
399 399 #define X86FSET_AES 31
400 400 #define X86FSET_PCLMULQDQ 32
401 401 #define X86FSET_XSAVE 33
402 402 #define X86FSET_AVX 34
403 403 #define X86FSET_VMX 35
404 404 #define X86FSET_SVM 36
405 405 #define X86FSET_TOPOEXT 37
406 406 #define X86FSET_F16C 38
407 407 #define X86FSET_RDRAND 39
408 408 #define X86FSET_X2APIC 40
409 409 #define X86FSET_AVX2 41
410 410 #define X86FSET_BMI1 42
411 411 #define X86FSET_BMI2 43
412 412 #define X86FSET_FMA 44
413 413 #define X86FSET_SMEP 45
414 414 #define X86FSET_SMAP 46
415 415 #define X86FSET_ADX 47
416 416 #define X86FSET_RDSEED 48
417 417 #define X86FSET_MPX 49
418 418 #define X86FSET_AVX512F 50
419 419 #define X86FSET_AVX512DQ 51
420 420 #define X86FSET_AVX512PF 52
421 421 #define X86FSET_AVX512ER 53
422 422 #define X86FSET_AVX512CD 54
423 423 #define X86FSET_AVX512BW 55
424 424 #define X86FSET_AVX512VL 56
425 425 #define X86FSET_AVX512FMA 57
426 426 #define X86FSET_AVX512VBMI 58
427 427 #define X86FSET_AVX512VPOPCDQ 59
428 428 #define X86FSET_AVX512NNIW 60
429 429 #define X86FSET_AVX512FMAPS 61
430 430 #define X86FSET_XSAVEOPT 62
431 431 #define X86FSET_XSAVEC 63
432 432 #define X86FSET_XSAVES 64
433 433 #define X86FSET_SHA 65
434 434 #define X86FSET_UMIP 66
435 435 #define X86FSET_PKU 67
436 436 #define X86FSET_OSPKE 68
437 437 #define X86FSET_PCID 69
438 438 #define X86FSET_INVPCID 70
439 439
440 440 /*
441 441 * Intel Deep C-State invariant TSC in leaf 0x80000007.
442 442 */
443 443 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
444 444
445 445 /*
446 446 * Intel Deep C-state always-running local APIC timer
447 447 */
448 448 #define CPUID_CSTATE_ARAT (0x4)
449 449
450 450 /*
451 451 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3].
452 452 */
453 453 #define CPUID_EPB_SUPPORT (1 << 3)
454 454
455 455 /*
456 456 * Intel TSC deadline timer
457 457 */
458 458 #define CPUID_DEADLINE_TSC (1 << 24)
459 459
460 460 /*
461 461 * x86_type is a legacy concept; this is supplanted
462 462 * for most purposes by x86_featureset; modern CPUs
463 463 * should be X86_TYPE_OTHER
464 464 */
465 465 #define X86_TYPE_OTHER 0
466 466 #define X86_TYPE_486 1
467 467 #define X86_TYPE_P5 2
468 468 #define X86_TYPE_P6 3
469 469 #define X86_TYPE_CYRIX_486 4
470 470 #define X86_TYPE_CYRIX_6x86L 5
471 471 #define X86_TYPE_CYRIX_6x86 6
472 472 #define X86_TYPE_CYRIX_GXm 7
473 473 #define X86_TYPE_CYRIX_6x86MX 8
474 474 #define X86_TYPE_CYRIX_MediaGX 9
475 475 #define X86_TYPE_CYRIX_MII 10
476 476 #define X86_TYPE_VIA_CYRIX_III 11
477 477 #define X86_TYPE_P4 12
478 478
479 479 /*
480 480 * x86_vendor allows us to select between
481 481 * implementation features and helps guide
482 482 * the interpretation of the cpuid instruction.
483 483 */
484 484 #define X86_VENDOR_Intel 0
485 485 #define X86_VENDORSTR_Intel "GenuineIntel"
486 486
487 487 #define X86_VENDOR_IntelClone 1
488 488
489 489 #define X86_VENDOR_AMD 2
490 490 #define X86_VENDORSTR_AMD "AuthenticAMD"
491 491
492 492 #define X86_VENDOR_Cyrix 3
493 493 #define X86_VENDORSTR_CYRIX "CyrixInstead"
494 494
495 495 #define X86_VENDOR_UMC 4
496 496 #define X86_VENDORSTR_UMC "UMC UMC UMC "
497 497
498 498 #define X86_VENDOR_NexGen 5
499 499 #define X86_VENDORSTR_NexGen "NexGenDriven"
500 500
501 501 #define X86_VENDOR_Centaur 6
502 502 #define X86_VENDORSTR_Centaur "CentaurHauls"
503 503
504 504 #define X86_VENDOR_Rise 7
505 505 #define X86_VENDORSTR_Rise "RiseRiseRise"
506 506
507 507 #define X86_VENDOR_SiS 8
508 508 #define X86_VENDORSTR_SiS "SiS SiS SiS "
509 509
510 510 #define X86_VENDOR_TM 9
511 511 #define X86_VENDORSTR_TM "GenuineTMx86"
512 512
513 513 #define X86_VENDOR_NSC 10
514 514 #define X86_VENDORSTR_NSC "Geode by NSC"
515 515
516 516 /*
517 517 * Vendor string max len + \0
518 518 */
519 519 #define X86_VENDOR_STRLEN 13
520 520
521 521 /*
522 522 * Some vendor/family/model/stepping ranges are commonly grouped under
523 523 * a single identifying banner by the vendor. The following encode
524 524 * that "revision" in a uint32_t with the 8 most significant bits
525 525 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
526 526 * family, and the remaining 16 typically forming a bitmask of revisions
527 527 * within that family with more significant bits indicating "later" revisions.
528 528 */
529 529
530 530 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
531 531 #define _X86_CHIPREV_VENDOR_SHIFT 24
532 532 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
533 533 #define _X86_CHIPREV_FAMILY_SHIFT 16
534 534 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
535 535
536 536 #define _X86_CHIPREV_VENDOR(x) \
537 537 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
538 538 #define _X86_CHIPREV_FAMILY(x) \
539 539 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
540 540 #define _X86_CHIPREV_REV(x) \
541 541 ((x) & _X86_CHIPREV_REV_MASK)
542 542
543 543 /* True if x matches in vendor and family and if x matches the given rev mask */
544 544 #define X86_CHIPREV_MATCH(x, mask) \
545 545 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
546 546 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
547 547 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
548 548
549 549 /* True if x matches in vendor and family, and rev is at least minx */
550 550 #define X86_CHIPREV_ATLEAST(x, minx) \
551 551 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
552 552 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
553 553 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
554 554
555 555 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
556 556 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
557 557 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
558 558
559 559 /* True if x matches in vendor, and family is at least minx */
560 560 #define X86_CHIPFAM_ATLEAST(x, minx) \
561 561 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
562 562 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
563 563
564 564 /* Revision default */
565 565 #define X86_CHIPREV_UNKNOWN 0x0
566 566
567 567 /*
568 568 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
569 569 * sufficiently different that we will distinguish them; in all other
570 570 * case we will identify the major revision.
571 571 */
572 572 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
573 573 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
574 574 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
575 575 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
576 576 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
577 577 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
578 578 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
579 579
580 580 /*
581 581 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
582 582 */
583 583 #define X86_CHIPREV_AMD_10_REV_A \
584 584 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
585 585 #define X86_CHIPREV_AMD_10_REV_B \
586 586 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
587 587 #define X86_CHIPREV_AMD_10_REV_C2 \
588 588 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
589 589 #define X86_CHIPREV_AMD_10_REV_C3 \
590 590 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
591 591 #define X86_CHIPREV_AMD_10_REV_D0 \
592 592 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
593 593 #define X86_CHIPREV_AMD_10_REV_D1 \
594 594 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
595 595 #define X86_CHIPREV_AMD_10_REV_E \
596 596 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
597 597
598 598 /*
599 599 * Definitions for AMD Family 0x11.
600 600 */
601 601 #define X86_CHIPREV_AMD_11_REV_B \
602 602 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
603 603
604 604 /*
605 605 * Definitions for AMD Family 0x12.
606 606 */
607 607 #define X86_CHIPREV_AMD_12_REV_B \
608 608 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
609 609
610 610 /*
611 611 * Definitions for AMD Family 0x14.
612 612 */
613 613 #define X86_CHIPREV_AMD_14_REV_B \
614 614 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
615 615 #define X86_CHIPREV_AMD_14_REV_C \
616 616 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
617 617
618 618 /*
619 619 * Definitions for AMD Family 0x15
620 620 */
621 621 #define X86_CHIPREV_AMD_15OR_REV_B2 \
622 622 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
623 623
624 624 #define X86_CHIPREV_AMD_15TN_REV_A1 \
625 625 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
626 626
627 627 /*
628 628 * Various socket/package types, extended as the need to distinguish
629 629 * a new type arises. The top 8 byte identfies the vendor and the
630 630 * remaining 24 bits describe 24 socket types.
631 631 */
632 632
633 633 #define _X86_SOCKET_VENDOR_SHIFT 24
634 634 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
635 635 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
636 636 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
637 637
638 638 #define _X86_SOCKET_MKVAL(vendor, bitval) \
639 639 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
640 640
641 641 #define X86_SOCKET_MATCH(s, mask) \
642 642 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
643 643 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
644 644
645 645 #define X86_SOCKET_UNKNOWN 0x0
646 646 /*
647 647 * AMD socket types
648 648 */
649 649 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001)
650 650 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002)
651 651 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004)
652 652 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008)
653 653 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010)
654 654 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020)
655 655 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040)
656 656 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080)
657 657 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100)
658 658 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200)
659 659 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400)
660 660 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800)
661 661 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000)
662 662 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000)
663 663 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x004000)
664 664 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x008000)
665 665 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x010000)
666 666 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x020000)
667 667 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x040000)
668 668 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x080000)
669 669 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x100000)
670 670 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x200000)
671 671
672 672 /*
673 673 * xgetbv/xsetbv support
674 674 * See section 13.3 in vol. 1 of the Intel devlopers manual.
675 675 */
676 676
677 677 #define XFEATURE_ENABLED_MASK 0x0
678 678 /*
679 679 * XFEATURE_ENABLED_MASK values (eax)
680 680 * See setup_xfem().
681 681 */
682 682 #define XFEATURE_LEGACY_FP 0x1
683 683 #define XFEATURE_SSE 0x2
684 684 #define XFEATURE_AVX 0x4
685 685 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */
686 686 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */
687 687 /* bit 8 unused */
688 688 #define XFEATURE_PKRU 0x200
689 689 #define XFEATURE_FP_ALL \
690 690 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
691 691 XFEATURE_AVX512 | XFEATURE_PKRU)
692 692
693 693 /*
694 694 * Define the set of xfeature flags that should be considered valid in the xsave
695 695 * state vector when we initialize an lwp. This is distinct from the full set so
696 696 * that all of the processor's normal logic and tracking of the xsave state is
697 697 * usable. This should correspond to the state that's been initialized by the
698 698 * ABI to hold meaningful values. Adding additional bits here can have serious
699 699 * performance implications and cause performance degradations when using the
700 700 * FPU vector (xmm) registers.
701 701 */
702 702 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
703 703
704 704 #if !defined(_ASM)
705 705
706 706 #if defined(_KERNEL) || defined(_KMEMUSER)
707 707
708 708 #define NUM_X86_FEATURES 71
709 709 extern uchar_t x86_featureset[];
710 710
711 711 extern void free_x86_featureset(void *featureset);
712 712 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
713 713 extern void add_x86_feature(void *featureset, uint_t feature);
714 714 extern void remove_x86_feature(void *featureset, uint_t feature);
715 715 extern boolean_t compare_x86_featureset(void *setA, void *setB);
716 716 extern void print_x86_featureset(void *featureset);
717 717
718 718
719 719 extern uint_t x86_type;
720 720 extern uint_t x86_vendor;
721 721 extern uint_t x86_clflush_size;
722 722
723 723 extern uint_t pentiumpro_bug4046376;
724 724
725 725 extern const char CyrixInstead[];
726 726
727 727 #endif
728 728
729 729 #if defined(_KERNEL)
730 730
731 731 /*
732 732 * This structure is used to pass arguments and get return values back
733 733 * from the CPUID instruction in __cpuid_insn() routine.
734 734 */
735 735 struct cpuid_regs {
736 736 uint32_t cp_eax;
737 737 uint32_t cp_ebx;
738 738 uint32_t cp_ecx;
739 739 uint32_t cp_edx;
740 740 };
741 741
742 742 extern int x86_use_pcid;
743 743 extern int x86_use_invpcid;
744 744
745 745 /*
746 746 * Utility functions to get/set extended control registers (XCR)
747 747 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
748 748 */
749 749 extern uint64_t get_xcr(uint_t);
750 750 extern void set_xcr(uint_t, uint64_t);
751 751
752 752 extern uint64_t rdmsr(uint_t);
753 753 extern void wrmsr(uint_t, const uint64_t);
754 754 extern uint64_t xrdmsr(uint_t);
755 755 extern void xwrmsr(uint_t, const uint64_t);
756 756 extern int checked_rdmsr(uint_t, uint64_t *);
757 757 extern int checked_wrmsr(uint_t, uint64_t);
758 758
759 759 extern void invalidate_cache(void);
760 760 extern ulong_t getcr4(void);
761 761 extern void setcr4(ulong_t);
762 762
763 763 extern void mtrr_sync(void);
764 764
765 765 extern void cpu_fast_syscall_enable(void);
766 766 extern void cpu_fast_syscall_disable(void);
767 767
768 768 struct cpu;
769 769
770 770 extern int cpuid_checkpass(struct cpu *, int);
771 771 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
772 772 extern uint32_t __cpuid_insn(struct cpuid_regs *);
773 773 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
774 774 extern int cpuid_getidstr(struct cpu *, char *, size_t);
775 775 extern const char *cpuid_getvendorstr(struct cpu *);
776 776 extern uint_t cpuid_getvendor(struct cpu *);
777 777 extern uint_t cpuid_getfamily(struct cpu *);
778 778 extern uint_t cpuid_getmodel(struct cpu *);
779 779 extern uint_t cpuid_getstep(struct cpu *);
780 780 extern uint_t cpuid_getsig(struct cpu *);
781 781 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
782 782 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
783 783 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
784 784 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
785 785 extern int cpuid_get_chipid(struct cpu *);
786 786 extern id_t cpuid_get_coreid(struct cpu *);
787 787 extern int cpuid_get_pkgcoreid(struct cpu *);
788 788 extern int cpuid_get_clogid(struct cpu *);
789 789 extern int cpuid_get_cacheid(struct cpu *);
790 790 extern uint32_t cpuid_get_apicid(struct cpu *);
791 791 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
792 792 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
793 793 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
794 794 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
795 795 extern size_t cpuid_get_xsave_size();
796 796 extern boolean_t cpuid_need_fp_excp_handling();
797 797 extern int cpuid_is_cmt(struct cpu *);
798 798 extern int cpuid_syscall32_insn(struct cpu *);
799 799 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
800 800
801 801 extern uint32_t cpuid_getchiprev(struct cpu *);
802 802 extern const char *cpuid_getchiprevstr(struct cpu *);
803 803 extern uint32_t cpuid_getsockettype(struct cpu *);
804 804 extern const char *cpuid_getsocketstr(struct cpu *);
805 805
806 806 extern int cpuid_have_cr8access(struct cpu *);
807 807
808 808 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
809 809
810 810 struct cpuid_info;
811 811
812 812 extern void setx86isalist(void);
813 813 extern void cpuid_alloc_space(struct cpu *);
814 814 extern void cpuid_free_space(struct cpu *);
815 815 extern void cpuid_pass1(struct cpu *, uchar_t *);
816 816 extern void cpuid_pass2(struct cpu *);
817 817 extern void cpuid_pass3(struct cpu *);
818 818 extern void cpuid_pass4(struct cpu *, uint_t *);
819 819 extern void cpuid_set_cpu_properties(void *, processorid_t,
820 820 struct cpuid_info *);
821 821
822 822 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
823 823 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
824 824
825 825 #if !defined(__xpv)
826 826 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
827 827 extern void cpuid_mwait_free(struct cpu *);
828 828 extern int cpuid_deep_cstates_supported(void);
829 829 extern int cpuid_arat_supported(void);
830 830 extern int cpuid_iepb_supported(struct cpu *);
831 831 extern int cpuid_deadline_tsc_supported(void);
832 832 extern void vmware_port(int, uint32_t *);
833 833 #endif
834 834
835 835 struct cpu_ucode_info;
836 836
837 837 extern void ucode_alloc_space(struct cpu *);
838 838 extern void ucode_free_space(struct cpu *);
839 839 extern void ucode_check(struct cpu *);
840 840 extern void ucode_cleanup();
841 841
842 842 #if !defined(__xpv)
843 843 extern char _tsc_mfence_start;
844 844 extern char _tsc_mfence_end;
845 845 extern char _tscp_start;
846 846 extern char _tscp_end;
847 847 extern char _no_rdtsc_start;
848 848 extern char _no_rdtsc_end;
849 849 extern char _tsc_lfence_start;
850 850 extern char _tsc_lfence_end;
851 851 #endif
852 852
853 853 #if !defined(__xpv)
854 854 extern char bcopy_patch_start;
855 855 extern char bcopy_patch_end;
856 856 extern char bcopy_ck_size;
857 857 #endif
858 858
859 859 extern void post_startup_cpu_fixups(void);
860 860
861 861 extern uint_t workaround_errata(struct cpu *);
862 862
863 863 #if defined(OPTERON_ERRATUM_93)
864 864 extern int opteron_erratum_93;
865 865 #endif
866 866
867 867 #if defined(OPTERON_ERRATUM_91)
868 868 extern int opteron_erratum_91;
869 869 #endif
870 870
871 871 #if defined(OPTERON_ERRATUM_100)
872 872 extern int opteron_erratum_100;
873 873 #endif
874 874
875 875 #if defined(OPTERON_ERRATUM_121)
876 876 extern int opteron_erratum_121;
877 877 #endif
878 878
879 879 #if defined(OPTERON_WORKAROUND_6323525)
880 880 extern int opteron_workaround_6323525;
881 881 extern void patch_workaround_6323525(void);
882 882 #endif
883 883
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884 884 #if !defined(__xpv)
885 885 extern void determine_platform(void);
886 886 #endif
887 887 extern int get_hwenv(void);
888 888 extern int is_controldom(void);
889 889
890 890 extern void enable_pcid(void);
891 891
892 892 extern void xsave_setup_msr(struct cpu *);
893 893
894 +#if !defined(__xpv)
895 +extern void reset_gdtr_limit(void);
896 +#endif
897 +
894 898 /*
895 899 * Hypervisor signatures
896 900 */
897 901 #define HVSIG_XEN_HVM "XenVMMXenVMM"
898 902 #define HVSIG_VMWARE "VMwareVMware"
899 903 #define HVSIG_KVM "KVMKVMKVM"
900 904 #define HVSIG_MICROSOFT "Microsoft Hv"
901 905
902 906 /*
903 907 * Defined hardware environments
904 908 */
905 909 #define HW_NATIVE (1 << 0) /* Running on bare metal */
906 910 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
907 911
908 912 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
909 913 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
910 914 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
911 915 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
912 916
913 917 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT)
914 918
915 919 #endif /* _KERNEL */
916 920
917 921 #endif /* !_ASM */
918 922
919 923 /*
920 924 * VMware hypervisor related defines
921 925 */
922 926 #define VMWARE_HVMAGIC 0x564d5868
923 927 #define VMWARE_HVPORT 0x5658
924 928 #define VMWARE_HVCMD_GETVERSION 0x0a
925 929 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
926 930
927 931 #ifdef __cplusplus
928 932 }
929 933 #endif
930 934
931 935 #endif /* _SYS_X86_ARCHEXT_H */
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