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--- old/usr/src/uts/sun4v/ml/mach_subr_asm.s
+++ new/usr/src/uts/sun4v/ml/mach_subr_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
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19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 */
24 24
25 25 /*
26 26 * General machine architecture & implementation specific
27 27 * assembly language routines.
28 28 */
29 -#if defined(lint)
30 -#include <sys/types.h>
31 -#include <sys/t_lock.h>
32 -#else /* lint */
33 29 #include "assym.h"
34 -#endif /* lint */
35 30
36 31 #define CPU_MODULE /* need it for NSEC_SHIFT used by NATIVE_TIME_TO_NSEC() */
37 32
38 33 #include <sys/asm_linkage.h>
39 34 #include <sys/machsystm.h>
40 35 #include <sys/machthread.h>
41 36 #include <sys/machclock.h>
42 37 #include <sys/privregs.h>
43 38 #include <sys/cmpregs.h>
44 39 #include <sys/clock.h>
45 40 #include <sys/fpras.h>
46 41 #include <sys/soft_state.h>
47 42
48 -#if defined(lint)
49 -
50 -uint64_t
51 -ultra_gettick(void)
52 -{ return (0); }
53 -
54 -#else /* lint */
55 -
56 43 /*
57 44 * This isn't the routine you're looking for.
58 45 *
59 46 * The routine simply returns the value of %tick on the *current* processor.
60 47 * Most of the time, gettick() [which in turn maps to %stick on platforms
61 48 * that have different CPU %tick rates] is what you want.
62 49 */
63 50
64 51 ENTRY(ultra_gettick)
65 52 RD_TICK(%o0,%o1,%o2,__LINE__)
66 53 retl
67 54 nop
68 55 SET_SIZE(ultra_gettick)
69 56
70 -#endif /* lint */
71 -
72 -#if defined(lint)
73 -/* ARGSUSED */
74 -void
75 -set_mmfsa_scratchpad(caddr_t vaddr)
76 -{ }
77 -
78 -#else /* lint */
79 -
80 57 ENTRY(set_mmfsa_scratchpad)
81 58 stxa %o0, [%g0]ASI_SCRATCHPAD
82 59 retl
83 60 nop
84 61 SET_SIZE(set_mmfsa_scratchpad)
85 -#endif /* lint */
86 62
87 -#if defined(lint)
88 -caddr_t
89 -get_mmfsa_scratchpad()
90 -{ return (0); }
91 -
92 -#else /* lint */
93 -
94 63 ENTRY(get_mmfsa_scratchpad)
95 64 ldxa [%g0]ASI_SCRATCHPAD, %o0
96 65 retl
97 66 nop
98 67 SET_SIZE(get_mmfsa_scratchpad)
99 -#endif /* lint */
100 68
101 69
102 70
103 -#if defined(lint)
104 -/* ARGSUSED */
105 -void
106 -cpu_intrq_unregister_powerdown(uint64_t doneflag_va)
107 -{}
108 -
109 -#else /* lint */
110 -
111 71 /*
112 72 * Called from a x-trap at tl1 must use %g1 as arg
113 73 * and save/restore %o0-%o5 after hypervisor calls
114 74 */
115 75
116 76 ENTRY(cpu_intrq_unregister_powerdown)
117 77
118 78 CPU_ADDR(%g2, %g3)
119 79 add %g2, CPU_MCPU, %g2
120 80 /*
121 81 * Save %o regs
122 82 */
123 83 mov %o0, %g3
124 84 mov %o1, %g4
125 85 mov %o2, %g5
126 86 mov %o5, %g6
127 87
128 88 ldx [%g2 + MCPU_CPU_Q_BASE], %o1
129 89 mov INTR_CPU_Q, %o0
130 90 call hv_cpu_qconf
131 91 mov %g0, %o2
132 92
133 93 ldx [%g2 + MCPU_DEV_Q_BASE], %o1
134 94 mov INTR_DEV_Q, %o0
135 95 call hv_cpu_qconf
136 96 mov %g0, %o2
137 97
138 98 ldx [%g2 + MCPU_RQ_BASE], %o1
139 99 mov CPU_RQ, %o0
140 100 call hv_cpu_qconf
141 101 mov %g0, %o2
142 102
143 103 ldx [%g2 + MCPU_NRQ_BASE], %o1
144 104 mov CPU_NRQ, %o0
145 105 call hv_cpu_qconf
146 106 mov %g0, %o2
147 107
148 108 /*
149 109 * set done flag to 0
150 110 */
151 111 stub %g0, [%g1]
152 112
153 113 /*
154 114 * Restore %o regs
155 115 */
156 116 mov %g3, %o0
157 117 mov %g4, %o1
158 118 mov %g5, %o2
159 119 mov %g6, %o5
160 120
161 121 /*
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162 122 * This CPU is on its way out. Spin here
163 123 * until the DR unconfigure code stops it.
164 124 * Returning would put it back in the OS
165 125 * where it might grab resources like locks,
166 126 * causing some nastiness to occur.
167 127 */
168 128 0:
169 129 ba,a 0b
170 130
171 131 SET_SIZE(cpu_intrq_unregister_powerdown)
172 -#endif /* lint */
173 132
174 133
175 -#if defined(lint)
176 -/* ARGSUSED */
177 -int
178 -getprocessorid(void)
179 -{ return (0); }
180 -
181 -#else /* lint */
182 -
183 134 /*
184 135 * Get the processor ID.
185 136 * === MID reg as specified in 15dec89 sun4u spec, sec 5.4.3
186 137 */
187 138
188 139 ENTRY(getprocessorid)
189 140 CPU_INDEX(%o0, %o1)
190 141 retl
191 142 nop
192 143 SET_SIZE(getprocessorid)
193 144
194 -#endif /* lint */
195 -
196 -#if defined(lint) || defined(__lint)
197 -
198 -/* ARGSUSED */
199 -hrtime_t
200 -tick2ns(hrtime_t tick, uint_t cpuid)
201 -{ return 0; }
202 -
203 -#else /* lint */
204 -
205 145 ENTRY_NP(tick2ns)
206 146 !
207 147 ! Use nsec_scale for sun4v which is based on %stick
208 148 !
209 149 NATIVE_TIME_TO_NSEC(%o0, %o2, %o3)
210 150 retl
211 151 nop
212 152 SET_SIZE(tick2ns)
213 153
214 -#endif /* lint */
215 -
216 -#if defined(lint)
217 -
218 -/* ARGSUSED */
219 -void
220 -set_cmp_error_steering(void)
221 -{}
222 -
223 -#else /* lint */
224 -
225 154 ENTRY(set_cmp_error_steering)
226 155 retl
227 156 nop
228 157 SET_SIZE(set_cmp_error_steering)
229 158
230 -#endif /* lint */
231 -
232 -#if defined(lint)
233 -
234 -/* ARGSUSED */
235 -uint64_t
236 -ultra_getver(void)
237 -{
238 - return (0);
239 -}
240 -
241 -#else /* lint */
242 -
243 159 ENTRY(ultra_getver)
244 160 retl
245 161 mov -1, %o0 ! XXXQ no version available
246 162 SET_SIZE(ultra_getver)
247 163
248 -#endif /* lint */
249 -
250 -#if defined(lint)
251 -
252 -int
253 -fpras_chkfn_type1(void)
254 -{ return 0; }
255 -
256 -#else /* lint */
257 -
258 164 /*
259 165 * Check instructions using just the AX pipelines, designed by
260 166 * C.B. Liaw of PNP.
261 167 *
262 168 * This function must match a struct fpras_chkfn and must be
263 169 * block aligned. A zero return means all was well. These
264 170 * instructions are chosen to be sensitive to bit corruptions
265 171 * on the fpras rewrite, so if a bit corruption still produces
266 172 * a valid instruction we should still get an incorrect result
267 173 * here. This function is never called directly - it is copied
268 174 * into per-cpu and per-operation buffers; it must therefore
269 175 * be absolutely position independent. If an illegal instruction
270 176 * is encountered then the trap handler trampolines to the final
271 177 * three instructions of this function.
272 178 *
273 179 * We want two instructions that are complements of one another,
274 180 * and which can perform a calculation with a known result.
275 181 *
276 182 * SETHI:
277 183 *
278 184 * | 0 0 | rd | 1 0 0 | imm22 |
279 185 * 31 30 29 25 24 22 21 0
280 186 *
281 187 * ADDCCC with two source registers:
282 188 *
283 189 * | 1 0 | rd | 0 1 1 0 0 0 | rs1 | 0 | - | rs2 |
284 190 * 31 30 29 25 24 19 18 14 13 12 5 4 0
285 191 *
286 192 * We can choose rd and imm2 of the SETHI and rd, rs1 and rs2 of
287 193 * the ADDCCC to obtain instructions that are complements in all but
288 194 * bit 30.
289 195 *
290 196 * Registers are numbered as follows:
291 197 *
292 198 * r[31] %i7
293 199 * r[30] %i6
294 200 * r[29] %i5
295 201 * r[28] %i4
296 202 * r[27] %i3
297 203 * r[26] %i2
298 204 * r[25] %i1
299 205 * r[24] %i0
300 206 * r[23] %l7
301 207 * r[22] %l6
302 208 * r[21] %l5
303 209 * r[20] %l4
304 210 * r[19] %l3
305 211 * r[18] %l2
306 212 * r[17] %l1
307 213 * r[16] %l0
308 214 * r[15] %o7
309 215 * r[14] %o6
310 216 * r[13] %o5
311 217 * r[12] %o4
312 218 * r[11] %o3
313 219 * r[10] %o2
314 220 * r[9] %o1
315 221 * r[8] %o0
316 222 * r[7] %g7
317 223 * r[6] %g6
318 224 * r[5] %g5
319 225 * r[4] %g4
320 226 * r[3] %g3
321 227 * r[2] %g2
322 228 * r[1] %g1
323 229 * r[0] %g0
324 230 *
325 231 * For register r[n], register r[31-n] is the complement. We must
326 232 * avoid use of %i6/%i7 and %o6/%o7 as well as %g7. Clearly we need
327 233 * to use a local or input register as one half of the pair, which
328 234 * requires us to obtain our own register window or take steps
329 235 * to preserve any local or input we choose to use. We choose
330 236 * %o1 as rd for the SETHI, so rd of the ADDCCC must be %l6.
331 237 * We'll use %o1 as rs1 and %l6 as rs2 of the ADDCCC, which then
332 238 * requires that imm22 be 0b111 10110 1 11111111 01001 or 0x3dbfe9,
333 239 * or %hi(0xf6ffa400). This determines the value of the constant
334 240 * CBV2 below.
335 241 *
336 242 * The constant CBV1 is chosen such that an initial subcc %g0, CBV1
337 243 * will set the carry bit and every addccc thereafter will continue
338 244 * to generate a carry. Other values are possible for CBV1 - this
339 245 * is just one that works this way.
340 246 *
341 247 * Finally CBV3 is the expected answer when we perform our repeated
342 248 * calculations on CBV1 and CBV2 - it is not otherwise specially
343 249 * derived. If this result is not obtained then a corruption has
344 250 * occured during the FPRAS_REWRITE of one of the two blocks of
345 251 * 16 instructions. A corruption could also result in an illegal
346 252 * instruction or other unexpected trap - we catch illegal
347 253 * instruction traps in the PC range and trampoline to the
348 254 * last instructions of the function to return a failure indication.
349 255 *
350 256 */
351 257
352 258 #define CBV1 0xc11
353 259 #define CBV2 0xf6ffa400
354 260 #define CBV3 0x66f9d800
355 261 #define CBR1 %o1
356 262 #define CBR2 %l6
357 263 #define CBO2 %o2
358 264 #define SETHI_CBV2_CBR1 sethi %hi(CBV2), CBR1
359 265 #define ADDCCC_CBR1_CBR2_CBR2 addccc CBR1, CBR2, CBR2
360 266
361 267 .align 64
362 268 ENTRY_NP(fpras_chkfn_type1)
363 269 mov CBR2, CBO2 ! 1, preserve CBR2 of (callers) window
364 270 mov FPRAS_OK, %o0 ! 2, default return value
365 271 ba,pt %icc, 1f ! 3
366 272 subcc %g0, CBV1, CBR2 ! 4
367 273 ! 5 - 16
368 274 .align 64
369 275 1: SETHI_CBV2_CBR1 ! 1
370 276 ADDCCC_CBR1_CBR2_CBR2 ! 2
371 277 SETHI_CBV2_CBR1 ! 3
372 278 ADDCCC_CBR1_CBR2_CBR2 ! 4
373 279 SETHI_CBV2_CBR1 ! 5
374 280 ADDCCC_CBR1_CBR2_CBR2 ! 6
375 281 SETHI_CBV2_CBR1 ! 7
376 282 ADDCCC_CBR1_CBR2_CBR2 ! 8
377 283 SETHI_CBV2_CBR1 ! 9
378 284 ADDCCC_CBR1_CBR2_CBR2 ! 10
379 285 SETHI_CBV2_CBR1 ! 11
380 286 ADDCCC_CBR1_CBR2_CBR2 ! 12
381 287 SETHI_CBV2_CBR1 ! 13
382 288 ADDCCC_CBR1_CBR2_CBR2 ! 14
383 289 SETHI_CBV2_CBR1 ! 15
384 290 ADDCCC_CBR1_CBR2_CBR2 ! 16
385 291
386 292 ADDCCC_CBR1_CBR2_CBR2 ! 1
387 293 SETHI_CBV2_CBR1 ! 2
388 294 ADDCCC_CBR1_CBR2_CBR2 ! 3
389 295 SETHI_CBV2_CBR1 ! 4
390 296 ADDCCC_CBR1_CBR2_CBR2 ! 5
391 297 SETHI_CBV2_CBR1 ! 6
392 298 ADDCCC_CBR1_CBR2_CBR2 ! 7
393 299 SETHI_CBV2_CBR1 ! 8
394 300 ADDCCC_CBR1_CBR2_CBR2 ! 9
395 301 SETHI_CBV2_CBR1 ! 10
396 302 ADDCCC_CBR1_CBR2_CBR2 ! 11
397 303 SETHI_CBV2_CBR1 ! 12
398 304 ADDCCC_CBR1_CBR2_CBR2 ! 13
399 305 SETHI_CBV2_CBR1 ! 14
400 306 ADDCCC_CBR1_CBR2_CBR2 ! 15
401 307 SETHI_CBV2_CBR1 ! 16
402 308
403 309 addc CBR1, CBR2, CBR2 ! 1
404 310 sethi %hi(CBV3), CBR1 ! 2
405 311 cmp CBR1, CBR2 ! 3
406 312 movnz %icc, FPRAS_BADCALC, %o0! 4, how detected
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407 313 retl ! 5
408 314 mov CBO2, CBR2 ! 6, restore borrowed register
409 315 .skip 4*(13-7+1) ! 7 - 13
410 316 !
411 317 ! illegal instr'n trap comes here
412 318 !
413 319 mov CBO2, CBR2 ! 14, restore borrowed register
414 320 retl ! 15
415 321 mov FPRAS_BADTRAP, %o0 ! 16, how detected
416 322 SET_SIZE(fpras_chkfn_type1)
417 -#endif /* lint */
418 323
419 -#if defined(lint)
420 -char soft_state_message_strings[SOLARIS_SOFT_STATE_MSG_CNT][SSM_SIZE];
421 -#else /* lint */
422 324 .seg ".data"
423 325 .global soft_state_message_strings
424 326
425 327 .align SSM_SIZE
426 328 soft_state_message_strings:
427 329 .asciz SOLARIS_SOFT_STATE_BOOT_MSG_STR
428 330 .align SSM_SIZE
429 331 .asciz SOLARIS_SOFT_STATE_RUN_MSG_STR
430 332 .align SSM_SIZE
431 333 .asciz SOLARIS_SOFT_STATE_HALT_MSG_STR
432 334 .align SSM_SIZE
433 335 .asciz SOLARIS_SOFT_STATE_POWER_MSG_STR
434 336 .align SSM_SIZE
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435 337 .asciz SOLARIS_SOFT_STATE_PANIC_MSG_STR
436 338 .align SSM_SIZE
437 339 .asciz SOLARIS_SOFT_STATE_REBOOT_MSG_STR
438 340 .align SSM_SIZE
439 341 .asciz SOLARIS_SOFT_STATE_DEBUG_MSG_STR
440 342 .align SSM_SIZE
441 343 .skip SSM_SIZE /* saved message */
442 344 .nword 0
443 345
444 346 .seg ".text"
445 -#endif /* lint */
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