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de-linting of .s files


   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  23  */
  24 
  25 /*
  26  * General machine architecture & implementation specific
  27  * assembly language routines.
  28  */
  29 #if defined(lint)
  30 #include <sys/types.h>
  31 #include <sys/t_lock.h>
  32 #else   /* lint */
  33 #include "assym.h"
  34 #endif  /* lint */
  35 
  36 #define CPU_MODULE /* need it for NSEC_SHIFT used by NATIVE_TIME_TO_NSEC() */
  37 
  38 #include <sys/asm_linkage.h>
  39 #include <sys/machsystm.h>
  40 #include <sys/machthread.h>
  41 #include <sys/machclock.h>
  42 #include <sys/privregs.h>
  43 #include <sys/cmpregs.h>
  44 #include <sys/clock.h>
  45 #include <sys/fpras.h>
  46 #include <sys/soft_state.h>
  47 
  48 #if defined(lint)
  49 
  50 uint64_t
  51 ultra_gettick(void)
  52 { return (0); }
  53 
  54 #else   /* lint */
  55 
  56 /*
  57  * This isn't the routine you're looking for.
  58  *
  59  * The routine simply returns the value of %tick on the *current* processor.
  60  * Most of the time, gettick() [which in turn maps to %stick on platforms
  61  * that have different CPU %tick rates] is what you want.
  62  */
  63 
  64         ENTRY(ultra_gettick)
  65         RD_TICK(%o0,%o1,%o2,__LINE__)
  66         retl
  67         nop
  68         SET_SIZE(ultra_gettick)
  69 
  70 #endif  /* lint */
  71 
  72 #if defined(lint)
  73 /* ARGSUSED */
  74 void
  75 set_mmfsa_scratchpad(caddr_t vaddr)
  76 { }
  77 
  78 #else   /* lint */
  79 
  80         ENTRY(set_mmfsa_scratchpad)
  81         stxa    %o0, [%g0]ASI_SCRATCHPAD 
  82         retl
  83         nop
  84         SET_SIZE(set_mmfsa_scratchpad)
  85 #endif  /* lint */
  86 
  87 #if defined(lint)
  88 caddr_t
  89 get_mmfsa_scratchpad()
  90 {  return (0); }
  91 
  92 #else   /* lint */
  93 
  94         ENTRY(get_mmfsa_scratchpad)
  95         ldxa    [%g0]ASI_SCRATCHPAD, %o0 
  96         retl
  97         nop
  98         SET_SIZE(get_mmfsa_scratchpad)
  99 #endif  /* lint */
 100 
 101 
 102 
 103 #if defined(lint)
 104 /* ARGSUSED */
 105 void
 106 cpu_intrq_unregister_powerdown(uint64_t doneflag_va)
 107 {}
 108 
 109 #else   /* lint */
 110 
 111 /*
 112  * Called from a x-trap at tl1 must use %g1 as arg
 113  * and save/restore %o0-%o5 after hypervisor calls
 114  */
 115 
 116         ENTRY(cpu_intrq_unregister_powerdown)
 117 
 118         CPU_ADDR(%g2, %g3)
 119         add %g2, CPU_MCPU, %g2 
 120         /*
 121          * Save %o regs
 122          */
 123         mov %o0, %g3
 124         mov %o1, %g4
 125         mov %o2, %g5
 126         mov %o5, %g6
 127 
 128         ldx [%g2 + MCPU_CPU_Q_BASE], %o1
 129         mov INTR_CPU_Q, %o0
 130         call hv_cpu_qconf


 152 
 153         /*
 154          * Restore %o regs
 155          */
 156         mov %g3, %o0
 157         mov %g4, %o1
 158         mov %g5, %o2
 159         mov %g6, %o5
 160 
 161         /*
 162          * This CPU is on its way out. Spin here
 163          * until the DR unconfigure code stops it.
 164          * Returning would put it back in the OS
 165          * where it might grab resources like locks,
 166          * causing some nastiness to occur.
 167          */
 168 0:
 169         ba,a    0b
 170 
 171         SET_SIZE(cpu_intrq_unregister_powerdown)
 172 #endif  /* lint */
 173 
 174 
 175 #if defined(lint)
 176 /* ARGSUSED */
 177 int
 178 getprocessorid(void)
 179 { return (0); }
 180 
 181 #else   /* lint */
 182 
 183 /*
 184  * Get the processor ID.
 185  * === MID reg as specified in 15dec89 sun4u spec, sec 5.4.3
 186  */
 187 
 188         ENTRY(getprocessorid)
 189         CPU_INDEX(%o0, %o1)
 190         retl
 191         nop
 192         SET_SIZE(getprocessorid)
 193 
 194 #endif  /* lint */
 195 
 196 #if defined(lint) || defined(__lint)
 197 
 198 /* ARGSUSED */
 199 hrtime_t
 200 tick2ns(hrtime_t tick, uint_t cpuid)
 201 { return 0; }
 202 
 203 #else   /* lint */
 204 
 205         ENTRY_NP(tick2ns)
 206         !
 207         ! Use nsec_scale for sun4v which is based on %stick
 208         !
 209         NATIVE_TIME_TO_NSEC(%o0, %o2, %o3)
 210         retl
 211         nop
 212         SET_SIZE(tick2ns)
 213 
 214 #endif  /* lint */
 215 
 216 #if defined(lint)
 217 
 218 /* ARGSUSED */
 219 void
 220 set_cmp_error_steering(void)
 221 {}
 222 
 223 #else   /* lint */
 224 
 225         ENTRY(set_cmp_error_steering)
 226         retl
 227         nop
 228         SET_SIZE(set_cmp_error_steering)
 229 
 230 #endif  /* lint */
 231 
 232 #if defined(lint)
 233 
 234 /* ARGSUSED */
 235 uint64_t
 236 ultra_getver(void)
 237 {
 238         return (0); 
 239 }
 240 
 241 #else /* lint */
 242 
 243         ENTRY(ultra_getver)
 244         retl
 245         mov     -1, %o0         ! XXXQ no version available
 246         SET_SIZE(ultra_getver)
 247 
 248 #endif /* lint */
 249 
 250 #if defined(lint)
 251 
 252 int
 253 fpras_chkfn_type1(void)
 254 { return 0; }
 255 
 256 #else   /* lint */
 257 
 258         /*
 259          * Check instructions using just the AX pipelines, designed by
 260          * C.B. Liaw of PNP.
 261          *
 262          * This function must match a struct fpras_chkfn and must be
 263          * block aligned.  A zero return means all was well.  These
 264          * instructions are chosen to be sensitive to bit corruptions
 265          * on the fpras rewrite, so if a bit corruption still produces
 266          * a valid instruction we should still get an incorrect result
 267          * here.  This function is never called directly - it is copied
 268          * into per-cpu and per-operation buffers;  it must therefore
 269          * be absolutely position independent.  If an illegal instruction
 270          * is encountered then the trap handler trampolines to the final
 271          * three instructions of this function.
 272          *
 273          * We want two instructions that are complements of one another,
 274          * and which can perform a calculation with a known result.
 275          *
 276          * SETHI:
 277          *


 397         SETHI_CBV2_CBR1                 ! 12
 398         ADDCCC_CBR1_CBR2_CBR2           ! 13
 399         SETHI_CBV2_CBR1                 ! 14
 400         ADDCCC_CBR1_CBR2_CBR2           ! 15
 401         SETHI_CBV2_CBR1                 ! 16
 402 
 403         addc    CBR1, CBR2, CBR2        ! 1
 404         sethi   %hi(CBV3), CBR1         ! 2
 405         cmp     CBR1, CBR2              ! 3
 406         movnz   %icc, FPRAS_BADCALC, %o0! 4, how detected
 407         retl                            ! 5
 408           mov   CBO2, CBR2              ! 6, restore borrowed register
 409         .skip 4*(13-7+1)                ! 7 - 13
 410                                         !
 411                                         ! illegal instr'n trap comes here
 412                                         !
 413         mov     CBO2, CBR2              ! 14, restore borrowed register
 414         retl                            ! 15
 415           mov   FPRAS_BADTRAP, %o0      ! 16, how detected
 416         SET_SIZE(fpras_chkfn_type1)
 417 #endif  /* lint */
 418 
 419 #if defined(lint)
 420 char    soft_state_message_strings[SOLARIS_SOFT_STATE_MSG_CNT][SSM_SIZE];
 421 #else   /* lint */
 422         .seg    ".data"
 423         .global soft_state_message_strings
 424 
 425         .align  SSM_SIZE
 426 soft_state_message_strings:
 427         .asciz  SOLARIS_SOFT_STATE_BOOT_MSG_STR
 428         .align  SSM_SIZE
 429         .asciz  SOLARIS_SOFT_STATE_RUN_MSG_STR
 430         .align  SSM_SIZE
 431         .asciz  SOLARIS_SOFT_STATE_HALT_MSG_STR
 432         .align  SSM_SIZE
 433         .asciz  SOLARIS_SOFT_STATE_POWER_MSG_STR
 434         .align  SSM_SIZE
 435         .asciz  SOLARIS_SOFT_STATE_PANIC_MSG_STR
 436         .align  SSM_SIZE
 437         .asciz  SOLARIS_SOFT_STATE_REBOOT_MSG_STR
 438         .align  SSM_SIZE
 439         .asciz  SOLARIS_SOFT_STATE_DEBUG_MSG_STR
 440         .align  SSM_SIZE
 441         .skip   SSM_SIZE                        /* saved message */
 442         .nword  0
 443 
 444         .seg    ".text"
 445 #endif  /* lint */


   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved.
  23  */
  24 
  25 /*
  26  * General machine architecture & implementation specific
  27  * assembly language routines.
  28  */




  29 #include "assym.h"

  30 
  31 #define CPU_MODULE /* need it for NSEC_SHIFT used by NATIVE_TIME_TO_NSEC() */
  32 
  33 #include <sys/asm_linkage.h>
  34 #include <sys/machsystm.h>
  35 #include <sys/machthread.h>
  36 #include <sys/machclock.h>
  37 #include <sys/privregs.h>
  38 #include <sys/cmpregs.h>
  39 #include <sys/clock.h>
  40 #include <sys/fpras.h>
  41 #include <sys/soft_state.h>
  42 








  43 /*
  44  * This isn't the routine you're looking for.
  45  *
  46  * The routine simply returns the value of %tick on the *current* processor.
  47  * Most of the time, gettick() [which in turn maps to %stick on platforms
  48  * that have different CPU %tick rates] is what you want.
  49  */
  50 
  51         ENTRY(ultra_gettick)
  52         RD_TICK(%o0,%o1,%o2,__LINE__)
  53         retl
  54         nop
  55         SET_SIZE(ultra_gettick)
  56 










  57         ENTRY(set_mmfsa_scratchpad)
  58         stxa    %o0, [%g0]ASI_SCRATCHPAD 
  59         retl
  60         nop
  61         SET_SIZE(set_mmfsa_scratchpad)

  62 







  63         ENTRY(get_mmfsa_scratchpad)
  64         ldxa    [%g0]ASI_SCRATCHPAD, %o0 
  65         retl
  66         nop
  67         SET_SIZE(get_mmfsa_scratchpad)

  68 
  69 
  70 








  71 /*
  72  * Called from a x-trap at tl1 must use %g1 as arg
  73  * and save/restore %o0-%o5 after hypervisor calls
  74  */
  75 
  76         ENTRY(cpu_intrq_unregister_powerdown)
  77 
  78         CPU_ADDR(%g2, %g3)
  79         add %g2, CPU_MCPU, %g2 
  80         /*
  81          * Save %o regs
  82          */
  83         mov %o0, %g3
  84         mov %o1, %g4
  85         mov %o2, %g5
  86         mov %o5, %g6
  87 
  88         ldx [%g2 + MCPU_CPU_Q_BASE], %o1
  89         mov INTR_CPU_Q, %o0
  90         call hv_cpu_qconf


 112 
 113         /*
 114          * Restore %o regs
 115          */
 116         mov %g3, %o0
 117         mov %g4, %o1
 118         mov %g5, %o2
 119         mov %g6, %o5
 120 
 121         /*
 122          * This CPU is on its way out. Spin here
 123          * until the DR unconfigure code stops it.
 124          * Returning would put it back in the OS
 125          * where it might grab resources like locks,
 126          * causing some nastiness to occur.
 127          */
 128 0:
 129         ba,a    0b
 130 
 131         SET_SIZE(cpu_intrq_unregister_powerdown)

 132 
 133 








 134 /*
 135  * Get the processor ID.
 136  * === MID reg as specified in 15dec89 sun4u spec, sec 5.4.3
 137  */
 138 
 139         ENTRY(getprocessorid)
 140         CPU_INDEX(%o0, %o1)
 141         retl
 142         nop
 143         SET_SIZE(getprocessorid)
 144 











 145         ENTRY_NP(tick2ns)
 146         !
 147         ! Use nsec_scale for sun4v which is based on %stick
 148         !
 149         NATIVE_TIME_TO_NSEC(%o0, %o2, %o3)
 150         retl
 151         nop
 152         SET_SIZE(tick2ns)
 153 











 154         ENTRY(set_cmp_error_steering)
 155         retl
 156         nop
 157         SET_SIZE(set_cmp_error_steering)
 158 













 159         ENTRY(ultra_getver)
 160         retl
 161         mov     -1, %o0         ! XXXQ no version available
 162         SET_SIZE(ultra_getver)
 163 










 164         /*
 165          * Check instructions using just the AX pipelines, designed by
 166          * C.B. Liaw of PNP.
 167          *
 168          * This function must match a struct fpras_chkfn and must be
 169          * block aligned.  A zero return means all was well.  These
 170          * instructions are chosen to be sensitive to bit corruptions
 171          * on the fpras rewrite, so if a bit corruption still produces
 172          * a valid instruction we should still get an incorrect result
 173          * here.  This function is never called directly - it is copied
 174          * into per-cpu and per-operation buffers;  it must therefore
 175          * be absolutely position independent.  If an illegal instruction
 176          * is encountered then the trap handler trampolines to the final
 177          * three instructions of this function.
 178          *
 179          * We want two instructions that are complements of one another,
 180          * and which can perform a calculation with a known result.
 181          *
 182          * SETHI:
 183          *


 303         SETHI_CBV2_CBR1                 ! 12
 304         ADDCCC_CBR1_CBR2_CBR2           ! 13
 305         SETHI_CBV2_CBR1                 ! 14
 306         ADDCCC_CBR1_CBR2_CBR2           ! 15
 307         SETHI_CBV2_CBR1                 ! 16
 308 
 309         addc    CBR1, CBR2, CBR2        ! 1
 310         sethi   %hi(CBV3), CBR1         ! 2
 311         cmp     CBR1, CBR2              ! 3
 312         movnz   %icc, FPRAS_BADCALC, %o0! 4, how detected
 313         retl                            ! 5
 314           mov   CBO2, CBR2              ! 6, restore borrowed register
 315         .skip 4*(13-7+1)                ! 7 - 13
 316                                         !
 317                                         ! illegal instr'n trap comes here
 318                                         !
 319         mov     CBO2, CBR2              ! 14, restore borrowed register
 320         retl                            ! 15
 321           mov   FPRAS_BADTRAP, %o0      ! 16, how detected
 322         SET_SIZE(fpras_chkfn_type1)

 323 



 324         .seg    ".data"
 325         .global soft_state_message_strings
 326 
 327         .align  SSM_SIZE
 328 soft_state_message_strings:
 329         .asciz  SOLARIS_SOFT_STATE_BOOT_MSG_STR
 330         .align  SSM_SIZE
 331         .asciz  SOLARIS_SOFT_STATE_RUN_MSG_STR
 332         .align  SSM_SIZE
 333         .asciz  SOLARIS_SOFT_STATE_HALT_MSG_STR
 334         .align  SSM_SIZE
 335         .asciz  SOLARIS_SOFT_STATE_POWER_MSG_STR
 336         .align  SSM_SIZE
 337         .asciz  SOLARIS_SOFT_STATE_PANIC_MSG_STR
 338         .align  SSM_SIZE
 339         .asciz  SOLARIS_SOFT_STATE_REBOOT_MSG_STR
 340         .align  SSM_SIZE
 341         .asciz  SOLARIS_SOFT_STATE_DEBUG_MSG_STR
 342         .align  SSM_SIZE
 343         .skip   SSM_SIZE                        /* saved message */
 344         .nword  0
 345 
 346         .seg    ".text"