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--- old/usr/src/uts/sun4v/ml/mach_proc_init.s
+++ new/usr/src/uts/sun4v/ml/mach_proc_init.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
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17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 -#pragma ident "%Z%%M% %I% %E% SMI"
28 -
29 27 /*
30 28 * sun4v processor initialization
31 29 *
32 30 * This is the kernel entry point for CPUs that enter Solaris
33 31 * directly from the hypervisor. i.e. without going through OBP.
34 32 */
35 33
36 -#if !defined(lint)
37 34 #include "assym.h"
38 -#endif /* !lint */
39 35
40 36 #include <sys/asm_linkage.h>
41 37 #include <sys/hypervisor_api.h>
42 38 #include <sys/machasi.h>
43 39 #include <sys/machpcb.h>
44 40 #include <sys/machlock.h>
45 41 #include <sys/mmu.h>
46 42 #include <sys/lpad.h>
47 43
48 -#if defined(lint)
49 -
50 -/* ARGSUSED */
51 -void
52 -mach_cpu_startup(uint64_t rabase, uint64_t memsz)
53 -{}
54 -
55 -#else /* lint */
56 -
57 44 /*
58 45 * %o0 - hcall specified arg (cpuid)
59 46 * %i0 - real memory base
60 47 * %i1 - memory size
61 48 */
62 49 ENTRY_NP(mach_cpu_startup)
63 50 /*
64 51 * Calculate the data pointer. The landing pad
65 52 * data immediately follows the landing pad text.
66 53 */
67 54 rd %pc, %l0
68 55 add %l0, LPAD_TEXT_SIZE, %l1 ! %l1 has start of data
69 56
70 57 /*
71 58 * Setup the initial state of the CPU.
72 59 */
73 60 wrpr %g0, 0, %tl
74 61 wrpr %g0, 0, %gl
75 62 wrpr %g0, MAXWIN - 2, %cansave
76 63 wrpr %g0, MAXWIN - 2, %cleanwin
77 64 wrpr %g0, 0, %canrestore
78 65 wrpr %g0, 0, %otherwin
79 66 wrpr %g0, 0, %cwp
80 67 wrpr %g0, 0, %wstate
81 68 wr %g0, %y
82 69 wrpr %g0, PIL_MAX, %pil
83 70
84 71 set trap_table, %g1
85 72 wrpr %g1, %tba
86 73
87 74 ! initialize cpuid into scratchpad register
88 75 mov SCRATCHPAD_CPUID, %g1
89 76 stxa %o0, [%g1]ASI_SCRATCHPAD
90 77
91 78 ! sanity check the data section
92 79 setx LPAD_MAGIC_VAL, %g2, %g1
93 80 ldx [%l1 + LPAD_MAGIC], %g2
94 81 cmp %g1, %g2
95 82 bne startup_error
96 83 nop
97 84
98 85 /*
99 86 * Loop through the array of TTE's, installing the
100 87 * VA to RA mapping for each one.
101 88 */
102 89 ldx [%l1 + LPAD_NMAP], %l2 ! %l2 = number of mappings
103 90 add %l1, LPAD_MAP, %l3 ! %l3 = the current mapping
104 91
105 92 /*
106 93 * Sanity check the number of mappings.
107 94 */
108 95 mulx %l2, LPAD_MAP_SIZE, %g1
109 96 add %l3, %g1, %g1 ! %g1 = end of the array
110 97 add %l1, LPAD_DATA_SIZE, %g2 ! %g2 = end of data section
111 98 sub %g2, %g1, %g2
112 99 brlz %g2, startup_error
113 100 nop
114 101
115 102 0:
116 103 cmp %l2, %g0
117 104 be 3f
118 105 nop
119 106
120 107 ldx [%l3 + LPAD_MAP_FLAGS], %l4 ! %l4 = flags
121 108
122 109 /*
123 110 * Generate args for the HV call
124 111 */
125 112 ldx [%l3 + LPAD_MAP_VA], %o0 ! %o0 = virtual address
126 113 mov KCONTEXT, %o1 ! %o1 = context
127 114 ldx [%l3 + LPAD_MAP_TTE], %o2 ! %o2 = TTE
128 115 and %l4, FLAG_MMUFLAGS_MASK, %o3 ! %o3 = MMU flags
129 116
130 117 ! check if this is a locked TTE
131 118 and %l4, FLAG_LOCK_MASK, %l4
132 119 cmp %l4, %g0
133 120 bne 1f
134 121 nop
135 122
136 123 ! install an unlocked entry
137 124 ta MMU_MAP_ADDR
138 125 ba 2f
139 126 nop
140 127 1:
141 128 ! install a locked entry
142 129 mov MAP_PERM_ADDR, %o5
143 130 ta FAST_TRAP
144 131
145 132 2:
146 133 ! check for errors from the hcall
147 134 cmp %o0, %g0
148 135 bne startup_error
149 136 nop
150 137
151 138 sub %l2, 1, %l2 ! decrement counter
152 139 add %l3, LPAD_MAP_SIZE, %l3 ! increment pointer
153 140
154 141 ba 0b
155 142 nop
156 143
157 144 3:
158 145 /*
159 146 * Set the MMU fault status area
160 147 */
161 148 ldx [%l1 + LPAD_MMFSA_RA], %o0
162 149
163 150 mov MMU_SET_INFOPTR, %o5
164 151 ta FAST_TRAP
165 152
166 153 ! check for errors from the hcall
167 154 cmp %o0, %g0
168 155 bne startup_error
169 156 nop
170 157
171 158 /*
172 159 * Load remaining arguments before enabling the
173 160 * MMU so that the loads can be done using real
174 161 * addresses.
175 162 */
176 163 ldx [%l1 + LPAD_PC], %l3 ! %l3 = specified entry point
177 164 ldx [%l1 + LPAD_ARG], %l4 ! %l4 = specified argument
178 165 ldx [%l1 + LPAD_INUSE], %l5 ! %l5 = va of inuse mailbox
179 166
180 167 /*
181 168 * Enable the MMU. On success, it returns to the
182 169 * global version of the landing pad text, rather
183 170 * than the text copied into the lpad buffer.
184 171 */
185 172 mov 1, %o0 ! %o0 = enable flag (1 = enable)
186 173 set startup_complete, %o1 ! VA of return address
187 174 mov MMU_ENABLE, %o5
188 175 ta FAST_TRAP
189 176
190 177 /*
191 178 * On errors, just enter a spin loop until the
192 179 * CPU that initiated the start recovers the CPU.
193 180 */
194 181 startup_error:
195 182 ba startup_error
196 183 nop
197 184
198 185 /*
199 186 * Jump to the generic CPU initialization code.
200 187 */
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201 188 startup_complete:
202 189 mov %l4, %o0
203 190 jmpl %l3, %g0
204 191 stx %g0, [%l5] ! clear the inuse mailbox
205 192
206 193 SET_SIZE(mach_cpu_startup)
207 194
208 195 .global mach_cpu_startup_end
209 196 mach_cpu_startup_end:
210 197
211 -#endif /* lint */
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