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--- old/usr/src/uts/sun4v/io/px/px_hcall.s
+++ new/usr/src/uts/sun4v/io/px/px_hcall.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26
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27 27 /*
28 28 * Hypervisor calls called by px nexus driver.
29 29 */
30 30
31 31 #include <sys/asm_linkage.h>
32 32 #include <sys/hypervisor_api.h>
33 33 #include <sys/dditypes.h>
34 34 #include <px_ioapi.h>
35 35 #include "px_lib4v.h"
36 36
37 -#if defined(lint) || defined(__lint)
38 -
39 -/*ARGSUSED*/
40 -uint64_t
41 -hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
42 - io_attributes_t attr, io_page_list_t *io_page_list_p,
43 - pages_t *pages_mapped)
44 -{ return (0); }
45 -
46 -/*ARGSUSED*/
47 -uint64_t
48 -hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
49 - pages_t *pages_demapped)
50 -{ return (0); }
51 -
52 -/*ARGSUSED*/
53 -uint64_t
54 -hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p,
55 - r_addr_t *r_addr_p)
56 -{ return (0); }
57 -
58 -/*ARGSUSED*/
59 -uint64_t
60 -hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr,
61 - io_addr_t *io_addr_p)
62 -{ return (0); }
63 -
64 -/*ARGSUSED*/
65 -uint64_t
66 -hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status,
67 - uint64_t *data_p)
68 -{ return (0); }
69 -
70 -/*ARGSUSED*/
71 -uint64_t
72 -hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data,
73 - r_addr_t ra2, uint32_t *rdbk_status)
74 -{ return (0); }
75 -
76 -/*ARGSUSED*/
77 -uint64_t
78 -hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes,
79 - io_sync_direction_t io_sync_direction, size_t *bytes_synched)
80 -{ return (0); }
81 -
82 -/*ARGSUSED*/
83 -uint64_t
84 -hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra,
85 - uint_t msiq_rec_cnt)
86 -{ return (0); }
87 -
88 -/*ARGSUSED*/
89 -uint64_t
90 -hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p,
91 - uint_t *msiq_rec_cnt_p)
92 -{ return (0); }
93 -
94 -/*ARGSUSED*/
95 -uint64_t
96 -hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
97 - pci_msiq_valid_state_t *msiq_valid_state)
98 -{ return (0); }
99 -
100 -/*ARGSUSED*/
101 -uint64_t
102 -hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
103 - pci_msiq_valid_state_t msiq_valid_state)
104 -{ return (0); }
105 -
106 -/*ARGSUSED*/
107 -uint64_t
108 -hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
109 - pci_msiq_state_t *msiq_state)
110 -{ return (0); }
111 -
112 -/*ARGSUSED*/
113 -uint64_t
114 -hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
115 - pci_msiq_state_t msiq_state)
116 -{ return (0); }
117 -
118 -/*ARGSUSED*/
119 -uint64_t
120 -hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
121 - msiqhead_t *msiq_head)
122 -{ return (0); }
123 -
124 -/*ARGSUSED*/
125 -uint64_t
126 -hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
127 - msiqhead_t msiq_head)
128 -{ return (0); }
129 -
130 -/*ARGSUSED*/
131 -uint64_t
132 -hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
133 - msiqtail_t *msiq_tail)
134 -{ return (0); }
135 -
136 -/*ARGSUSED*/
137 -uint64_t
138 -hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
139 - msiqid_t *msiq_id)
140 -{ return (0); }
141 -
142 -/*ARGSUSED*/
143 -uint64_t
144 -hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
145 - msiqid_t msiq_id, msi_type_t msitype)
146 -{ return (0); }
147 -
148 -/*ARGSUSED*/
149 -uint64_t
150 -hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
151 - pci_msi_valid_state_t *msi_valid_state)
152 -{ return (0); }
153 -
154 -/*ARGSUSED*/
155 -uint64_t
156 -hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
157 - pci_msi_valid_state_t msi_valid_state)
158 -{ return (0); }
159 -
160 -/*ARGSUSED*/
161 -uint64_t
162 -hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
163 - pci_msi_state_t *msi_state)
164 -{ return (0); }
165 -
166 -/*ARGSUSED*/
167 -uint64_t
168 -hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
169 - pci_msi_state_t msi_state)
170 -{ return (0); }
171 -
172 -/*ARGSUSED*/
173 -uint64_t
174 -hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
175 - msiqid_t *msiq_id)
176 -{ return (0); }
177 -
178 -/*ARGSUSED*/
179 -uint64_t
180 -hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
181 - msiqid_t msiq_id)
182 -{ return (0); }
183 -
184 -/*ARGSUSED*/
185 -uint64_t
186 -hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
187 - pcie_msg_valid_state_t *msg_valid_state)
188 -{ return (0); }
189 -
190 -/*ARGSUSED*/
191 -uint64_t
192 -hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
193 - pcie_msg_valid_state_t msg_valid_state)
194 -{ return (0); }
195 -
196 -/*ARGSUSED*/
197 -uint64_t
198 -pci_error_send(devhandle_t dev_hdl, devino_t devino, pci_device_t bdf)
199 -{ return (0); }
200 -
201 -/*
202 - * First arg to both of these functions is a dummy, to accomodate how
203 - * hv_hpriv() works.
204 - */
205 -/*ARGSUSED*/
206 -int
207 -px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr)
208 -{ return (0); }
209 -
210 -/*ARGSUSED*/
211 -uint64_t
212 -pci_iov_root_configured(devhandle_t dev_hdl)
213 -{ return (0); }
214 -
215 -#else /* lint || __lint */
216 -
217 37 /*
218 38 * arg0 - devhandle
219 39 * arg1 - tsbid
220 40 * arg2 - pages
221 41 * arg3 - io_attributes
222 42 * arg4 - io_page_list_p
223 43 *
224 44 * ret1 - pages_mapped
225 45 */
226 46 ENTRY(hvio_iommu_map)
227 47 save %sp, -SA(MINFRAME64), %sp
228 48 mov %i0, %o0
229 49 mov %i1, %o1
230 50 mov %i2, %o2
231 51 mov %i3, %o3
232 52 mov %i4, %o4
233 53 mov HVIO_IOMMU_MAP, %o5
234 54 ta FAST_TRAP
235 55 brnz %o0, 1f
236 56 mov %o0, %i0
237 57 stuw %o1, [%i5]
238 58 1:
239 59 ret
240 60 restore
241 61 SET_SIZE(hvio_iommu_map)
242 62
243 63 /*
244 64 * arg0 - devhandle
245 65 * arg1 - tsbid
246 66 * arg2 - pages
247 67 *
248 68 * ret1 - pages_demapped
249 69 */
250 70 ENTRY(hvio_iommu_demap)
251 71 mov HVIO_IOMMU_DEMAP, %o5
252 72 ta FAST_TRAP
253 73 brz,a %o0, 1f
254 74 stuw %o1, [%o3]
255 75 1: retl
256 76 nop
257 77 SET_SIZE(hvio_iommu_demap)
258 78
259 79 /*
260 80 * arg0 - devhandle
261 81 * arg1 - tsbid
262 82 *
263 83 *
264 84 * ret0 - status
265 85 * ret1 - io_attributes
266 86 * ret2 - r_addr
267 87 */
268 88 ENTRY(hvio_iommu_getmap)
269 89 mov %o2, %o4
270 90 mov HVIO_IOMMU_GETMAP, %o5
271 91 ta FAST_TRAP
272 92 brnz %o0, 1f
273 93 nop
274 94 stx %o2, [%o3]
275 95 st %o1, [%o4]
276 96 1:
277 97 retl
278 98 nop
279 99 SET_SIZE(hvio_iommu_getmap)
280 100
281 101 /*
282 102 * arg0 - devhandle
283 103 * arg1 - r_addr
284 104 * arg2 - io_attributes
285 105 *
286 106 *
287 107 * ret0 - status
288 108 * ret1 - io_addr
289 109 */
290 110 ENTRY(hvio_iommu_getbypass)
291 111 mov HVIO_IOMMU_GETBYPASS, %o5
292 112 ta FAST_TRAP
293 113 brz,a %o0, 1f
294 114 stx %o1, [%o3]
295 115 1: retl
296 116 nop
297 117 SET_SIZE(hvio_iommu_getbypass)
298 118
299 119 /*
300 120 * arg0 - devhandle
301 121 * arg1 - r_addr
302 122 * arg2 - size
303 123 *
304 124 * ret1 - error_flag
305 125 * ret2 - data
306 126 */
307 127 ENTRY(hvio_peek)
308 128 mov HVIO_PEEK, %o5
309 129 ta FAST_TRAP
310 130 brnz %o0, 1f
311 131 nop
312 132 stx %o2, [%o4]
313 133 st %o1, [%o3]
314 134 1:
315 135 retl
316 136 nop
317 137 SET_SIZE(hvio_peek)
318 138
319 139 /*
320 140 * arg0 - devhandle
321 141 * arg1 - r_addr
322 142 * arg2 - sizes
323 143 * arg3 - data
324 144 * arg4 - r_addr2
325 145 *
326 146 * ret1 - error_flag
327 147 */
328 148 ENTRY(hvio_poke)
329 149 save %sp, -SA(MINFRAME64), %sp
330 150 mov %i0, %o0
331 151 mov %i1, %o1
332 152 mov %i2, %o2
333 153 mov %i3, %o3
334 154 mov %i4, %o4
335 155 mov HVIO_POKE, %o5
336 156 ta FAST_TRAP
337 157 brnz %o0, 1f
338 158 mov %o0, %i0
339 159 stuw %o1, [%i5]
340 160 1:
341 161 ret
342 162 restore
343 163 SET_SIZE(hvio_poke)
344 164
345 165 /*
346 166 * arg0 - devhandle
347 167 * arg1 - r_addr
348 168 * arg2 - num_bytes
349 169 * arg3 - io_sync_direction
350 170 *
351 171 * ret0 - status
352 172 * ret1 - bytes_synched
353 173 */
354 174 ENTRY(hvio_dma_sync)
355 175 mov HVIO_DMA_SYNC, %o5
356 176 ta FAST_TRAP
357 177 brz,a %o0, 1f
358 178 stx %o1, [%o4]
359 179 1: retl
360 180 nop
361 181 SET_SIZE(hvio_dma_sync)
362 182
363 183 /*
364 184 * arg0 - devhandle
365 185 * arg1 - msiq_id
366 186 * arg2 - r_addr
367 187 * arg3 - nentries
368 188 *
369 189 * ret0 - status
370 190 */
371 191 ENTRY(hvio_msiq_conf)
372 192 mov HVIO_MSIQ_CONF, %o5
373 193 ta FAST_TRAP
374 194 retl
375 195 nop
376 196 SET_SIZE(hvio_msiq_conf)
377 197
378 198 /*
379 199 * arg0 - devhandle
380 200 * arg1 - msiq_id
381 201 *
382 202 * ret0 - status
383 203 * ret1 - r_addr
384 204 * ret1 - nentries
385 205 */
386 206 ENTRY(hvio_msiq_info)
387 207 mov %o2, %o4
388 208 mov HVIO_MSIQ_INFO, %o5
389 209 ta FAST_TRAP
390 210 brnz %o0, 1f
391 211 nop
392 212 stx %o1, [%o4]
393 213 stuw %o2, [%o3]
394 214 1: retl
395 215 nop
396 216 SET_SIZE(hvio_msiq_info)
397 217
398 218 /*
399 219 * arg0 - devhandle
400 220 * arg1 - msiq_id
401 221 *
402 222 * ret0 - status
403 223 * ret1 - msiq_valid_state
404 224 */
405 225 ENTRY(hvio_msiq_getvalid)
406 226 mov HVIO_MSIQ_GETVALID, %o5
407 227 ta FAST_TRAP
408 228 brz,a %o0, 1f
409 229 stuw %o1, [%o2]
410 230 1: retl
411 231 nop
412 232 SET_SIZE(hvio_msiq_getvalid)
413 233
414 234 /*
415 235 * arg0 - devhandle
416 236 * arg1 - msiq_id
417 237 * arg2 - msiq_valid_state
418 238 *
419 239 * ret0 - status
420 240 */
421 241 ENTRY(hvio_msiq_setvalid)
422 242 mov HVIO_MSIQ_SETVALID, %o5
423 243 ta FAST_TRAP
424 244 retl
425 245 nop
426 246 SET_SIZE(hvio_msiq_setvalid)
427 247
428 248 /*
429 249 * arg0 - devhandle
430 250 * arg1 - msiq_id
431 251 *
432 252 * ret0 - status
433 253 * ret1 - msiq_state
434 254 */
435 255 ENTRY(hvio_msiq_getstate)
436 256 mov HVIO_MSIQ_GETSTATE, %o5
437 257 ta FAST_TRAP
438 258 brz,a %o0, 1f
439 259 stuw %o1, [%o2]
440 260 1: retl
441 261 nop
442 262 SET_SIZE(hvio_msiq_getstate)
443 263
444 264 /*
445 265 * arg0 - devhandle
446 266 * arg1 - msiq_id
447 267 * arg2 - msiq_state
448 268 *
449 269 * ret0 - status
450 270 */
451 271 ENTRY(hvio_msiq_setstate)
452 272 mov HVIO_MSIQ_SETSTATE, %o5
453 273 ta FAST_TRAP
454 274 retl
455 275 nop
456 276 SET_SIZE(hvio_msiq_setstate)
457 277
458 278 /*
459 279 * arg0 - devhandle
460 280 * arg1 - msiq_id
461 281 *
462 282 * ret0 - status
463 283 * ret1 - msiq_head
464 284 */
465 285 ENTRY(hvio_msiq_gethead)
466 286 mov HVIO_MSIQ_GETHEAD, %o5
467 287 ta FAST_TRAP
468 288 brz,a %o0, 1f
469 289 stx %o1, [%o2]
470 290 1: retl
471 291 nop
472 292 SET_SIZE(hvio_msiq_gethead)
473 293
474 294 /*
475 295 * arg0 - devhandle
476 296 * arg1 - msiq_id
477 297 * arg2 - msiq_head
478 298 *
479 299 * ret0 - status
480 300 */
481 301 ENTRY(hvio_msiq_sethead)
482 302 mov HVIO_MSIQ_SETHEAD, %o5
483 303 ta FAST_TRAP
484 304 retl
485 305 nop
486 306 SET_SIZE(hvio_msiq_sethead)
487 307
488 308 /*
489 309 * arg0 - devhandle
490 310 * arg1 - msiq_id
491 311 *
492 312 * ret0 - status
493 313 * ret1 - msiq_tail
494 314 */
495 315 ENTRY(hvio_msiq_gettail)
496 316 mov HVIO_MSIQ_GETTAIL, %o5
497 317 ta FAST_TRAP
498 318 brz,a %o0, 1f
499 319 stx %o1, [%o2]
500 320 1: retl
501 321 nop
502 322 SET_SIZE(hvio_msiq_gettail)
503 323
504 324 /*
505 325 * arg0 - devhandle
506 326 * arg1 - msi_num
507 327 *
508 328 * ret0 - status
509 329 * ret1 - msiq_id
510 330 */
511 331 ENTRY(hvio_msi_getmsiq)
512 332 mov HVIO_MSI_GETMSIQ, %o5
513 333 ta FAST_TRAP
514 334 brz,a %o0, 1f
515 335 stuw %o1, [%o2]
516 336 1: retl
517 337 nop
518 338 SET_SIZE(hvio_msi_getmsiq)
519 339
520 340 /*
521 341 * arg0 - devhandle
522 342 * arg1 - msi_num
523 343 * arg2 - msiq_id
524 344 * arg2 - msitype
525 345 *
526 346 * ret0 - status
527 347 */
528 348 ENTRY(hvio_msi_setmsiq)
529 349 mov HVIO_MSI_SETMSIQ, %o5
530 350 ta FAST_TRAP
531 351 retl
532 352 nop
533 353 SET_SIZE(hvio_msi_setmsiq)
534 354
535 355 /*
536 356 * arg0 - devhandle
537 357 * arg1 - msi_num
538 358 *
539 359 * ret0 - status
540 360 * ret1 - msi_valid_state
541 361 */
542 362 ENTRY(hvio_msi_getvalid)
543 363 mov HVIO_MSI_GETVALID, %o5
544 364 ta FAST_TRAP
545 365 brz,a %o0, 1f
546 366 stuw %o1, [%o2]
547 367 1: retl
548 368 nop
549 369 SET_SIZE(hvio_msi_getvalid)
550 370
551 371 /*
552 372 * arg0 - devhandle
553 373 * arg1 - msi_num
554 374 * arg2 - msi_valid_state
555 375 *
556 376 * ret0 - status
557 377 */
558 378 ENTRY(hvio_msi_setvalid)
559 379 mov HVIO_MSI_SETVALID, %o5
560 380 ta FAST_TRAP
561 381 retl
562 382 nop
563 383 SET_SIZE(hvio_msi_setvalid)
564 384
565 385 /*
566 386 * arg0 - devhandle
567 387 * arg1 - msi_num
568 388 *
569 389 * ret0 - status
570 390 * ret1 - msi_state
571 391 */
572 392 ENTRY(hvio_msi_getstate)
573 393 mov HVIO_MSI_GETSTATE, %o5
574 394 ta FAST_TRAP
575 395 brz,a %o0, 1f
576 396 stuw %o1, [%o2]
577 397 1: retl
578 398 nop
579 399 SET_SIZE(hvio_msi_getstate)
580 400
581 401 /*
582 402 * arg0 - devhandle
583 403 * arg1 - msi_num
584 404 * arg2 - msi_state
585 405 *
586 406 * ret0 - status
587 407 */
588 408 ENTRY(hvio_msi_setstate)
589 409 mov HVIO_MSI_SETSTATE, %o5
590 410 ta FAST_TRAP
591 411 retl
592 412 nop
593 413 SET_SIZE(hvio_msi_setstate)
594 414
595 415 /*
596 416 * arg0 - devhandle
597 417 * arg1 - msg_type
598 418 *
599 419 * ret0 - status
600 420 * ret1 - msiq_id
601 421 */
602 422 ENTRY(hvio_msg_getmsiq)
603 423 mov HVIO_MSG_GETMSIQ, %o5
604 424 ta FAST_TRAP
605 425 brz,a %o0, 1f
606 426 stuw %o1, [%o2]
607 427 1: retl
608 428 nop
609 429 SET_SIZE(hvio_msg_getmsiq)
610 430
611 431 /*
612 432 * arg0 - devhandle
613 433 * arg1 - msg_type
614 434 * arg2 - msiq_id
615 435 *
616 436 * ret0 - status
617 437 */
618 438 ENTRY(hvio_msg_setmsiq)
619 439 mov HVIO_MSG_SETMSIQ, %o5
620 440 ta FAST_TRAP
621 441 retl
622 442 nop
623 443 SET_SIZE(hvio_msg_setmsiq)
624 444
625 445 /*
626 446 * arg0 - devhandle
627 447 * arg1 - msg_type
628 448 *
629 449 * ret0 - status
630 450 * ret1 - msg_valid_state
631 451 */
632 452 ENTRY(hvio_msg_getvalid)
633 453 mov HVIO_MSG_GETVALID, %o5
634 454 ta FAST_TRAP
635 455 brz,a %o0, 1f
636 456 stuw %o1, [%o2]
637 457 1: retl
638 458 nop
639 459 SET_SIZE(hvio_msg_getvalid)
640 460
641 461 /*
642 462 * arg0 - devhandle
643 463 * arg1 - msg_type
644 464 * arg2 - msg_valid_state
645 465 *
646 466 * ret0 - status
647 467 */
648 468 ENTRY(hvio_msg_setvalid)
649 469 mov HVIO_MSG_SETVALID, %o5
650 470 ta FAST_TRAP
651 471 retl
652 472 nop
653 473 SET_SIZE(hvio_msg_setvalid)
654 474
655 475 /*
656 476 * arg0 - devhandle
657 477 * arg1 - devino
658 478 * arg2 - pci_device
659 479 *
660 480 * ret0 - status
661 481 */
662 482 ENTRY(pci_error_send)
663 483 mov PCI_ERROR_SEND, %o5
664 484 ta FAST_TRAP
665 485 retl
666 486 nop
667 487 SET_SIZE(pci_error_send)
668 488
669 489 #define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3
670 490
671 491 ! px_phys_acc_4v: Do physical address read.
672 492 !
673 493 ! After SHIFT_REGS:
674 494 ! %o0 is "from" address
675 495 ! %o1 is "to" address
676 496 !
677 497 ! Assumes 8 byte data and that alignment is correct.
678 498 !
679 499 ! Always returns success (0) in %o0
680 500
681 501 ! px_phys_acc_4v must not be split across pages.
682 502 !
683 503 ! ATTN: Be sure that the alignment value is larger than the size of
684 504 ! the px_phys_acc_4v function.
685 505 !
686 506 .align 0x40
687 507
688 508 ENTRY(px_phys_acc_4v)
689 509
690 510 SHIFT_REGS
691 511 ldx [%o0], %g1
692 512 stx %g1, [%o1]
693 513 membar #Sync ! Make sure the loads take
694 514 mov %g0, %o0
695 515 done
696 516 SET_SIZE(px_phys_acc_4v)
697 517
698 518 /*
699 519 * arg0 - devhandle
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700 520 *
701 521 * ret0 - status
702 522 */
703 523 ENTRY(pci_iov_root_configured)
704 524 mov PCI_IOV_ROOT_CONFIGURED, %o5
705 525 ta FAST_TRAP
706 526 retl
707 527 nop
708 528 SET_SIZE(pci_iov_root_configured)
709 529
710 -#endif /* lint || __lint */
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