17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26
27 /*
28 * Hypervisor calls called by px nexus driver.
29 */
30
31 #include <sys/asm_linkage.h>
32 #include <sys/hypervisor_api.h>
33 #include <sys/dditypes.h>
34 #include <px_ioapi.h>
35 #include "px_lib4v.h"
36
37 #if defined(lint) || defined(__lint)
38
39 /*ARGSUSED*/
40 uint64_t
41 hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
42 io_attributes_t attr, io_page_list_t *io_page_list_p,
43 pages_t *pages_mapped)
44 { return (0); }
45
46 /*ARGSUSED*/
47 uint64_t
48 hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
49 pages_t *pages_demapped)
50 { return (0); }
51
52 /*ARGSUSED*/
53 uint64_t
54 hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p,
55 r_addr_t *r_addr_p)
56 { return (0); }
57
58 /*ARGSUSED*/
59 uint64_t
60 hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr,
61 io_addr_t *io_addr_p)
62 { return (0); }
63
64 /*ARGSUSED*/
65 uint64_t
66 hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status,
67 uint64_t *data_p)
68 { return (0); }
69
70 /*ARGSUSED*/
71 uint64_t
72 hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data,
73 r_addr_t ra2, uint32_t *rdbk_status)
74 { return (0); }
75
76 /*ARGSUSED*/
77 uint64_t
78 hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes,
79 io_sync_direction_t io_sync_direction, size_t *bytes_synched)
80 { return (0); }
81
82 /*ARGSUSED*/
83 uint64_t
84 hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra,
85 uint_t msiq_rec_cnt)
86 { return (0); }
87
88 /*ARGSUSED*/
89 uint64_t
90 hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p,
91 uint_t *msiq_rec_cnt_p)
92 { return (0); }
93
94 /*ARGSUSED*/
95 uint64_t
96 hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
97 pci_msiq_valid_state_t *msiq_valid_state)
98 { return (0); }
99
100 /*ARGSUSED*/
101 uint64_t
102 hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
103 pci_msiq_valid_state_t msiq_valid_state)
104 { return (0); }
105
106 /*ARGSUSED*/
107 uint64_t
108 hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
109 pci_msiq_state_t *msiq_state)
110 { return (0); }
111
112 /*ARGSUSED*/
113 uint64_t
114 hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
115 pci_msiq_state_t msiq_state)
116 { return (0); }
117
118 /*ARGSUSED*/
119 uint64_t
120 hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
121 msiqhead_t *msiq_head)
122 { return (0); }
123
124 /*ARGSUSED*/
125 uint64_t
126 hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
127 msiqhead_t msiq_head)
128 { return (0); }
129
130 /*ARGSUSED*/
131 uint64_t
132 hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
133 msiqtail_t *msiq_tail)
134 { return (0); }
135
136 /*ARGSUSED*/
137 uint64_t
138 hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
139 msiqid_t *msiq_id)
140 { return (0); }
141
142 /*ARGSUSED*/
143 uint64_t
144 hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
145 msiqid_t msiq_id, msi_type_t msitype)
146 { return (0); }
147
148 /*ARGSUSED*/
149 uint64_t
150 hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
151 pci_msi_valid_state_t *msi_valid_state)
152 { return (0); }
153
154 /*ARGSUSED*/
155 uint64_t
156 hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
157 pci_msi_valid_state_t msi_valid_state)
158 { return (0); }
159
160 /*ARGSUSED*/
161 uint64_t
162 hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
163 pci_msi_state_t *msi_state)
164 { return (0); }
165
166 /*ARGSUSED*/
167 uint64_t
168 hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
169 pci_msi_state_t msi_state)
170 { return (0); }
171
172 /*ARGSUSED*/
173 uint64_t
174 hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
175 msiqid_t *msiq_id)
176 { return (0); }
177
178 /*ARGSUSED*/
179 uint64_t
180 hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
181 msiqid_t msiq_id)
182 { return (0); }
183
184 /*ARGSUSED*/
185 uint64_t
186 hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
187 pcie_msg_valid_state_t *msg_valid_state)
188 { return (0); }
189
190 /*ARGSUSED*/
191 uint64_t
192 hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
193 pcie_msg_valid_state_t msg_valid_state)
194 { return (0); }
195
196 /*ARGSUSED*/
197 uint64_t
198 pci_error_send(devhandle_t dev_hdl, devino_t devino, pci_device_t bdf)
199 { return (0); }
200
201 /*
202 * First arg to both of these functions is a dummy, to accomodate how
203 * hv_hpriv() works.
204 */
205 /*ARGSUSED*/
206 int
207 px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr)
208 { return (0); }
209
210 /*ARGSUSED*/
211 uint64_t
212 pci_iov_root_configured(devhandle_t dev_hdl)
213 { return (0); }
214
215 #else /* lint || __lint */
216
217 /*
218 * arg0 - devhandle
219 * arg1 - tsbid
220 * arg2 - pages
221 * arg3 - io_attributes
222 * arg4 - io_page_list_p
223 *
224 * ret1 - pages_mapped
225 */
226 ENTRY(hvio_iommu_map)
227 save %sp, -SA(MINFRAME64), %sp
228 mov %i0, %o0
229 mov %i1, %o1
230 mov %i2, %o2
231 mov %i3, %o3
232 mov %i4, %o4
233 mov HVIO_IOMMU_MAP, %o5
234 ta FAST_TRAP
235 brnz %o0, 1f
236 mov %o0, %i0
690 SHIFT_REGS
691 ldx [%o0], %g1
692 stx %g1, [%o1]
693 membar #Sync ! Make sure the loads take
694 mov %g0, %o0
695 done
696 SET_SIZE(px_phys_acc_4v)
697
698 /*
699 * arg0 - devhandle
700 *
701 * ret0 - status
702 */
703 ENTRY(pci_iov_root_configured)
704 mov PCI_IOV_ROOT_CONFIGURED, %o5
705 ta FAST_TRAP
706 retl
707 nop
708 SET_SIZE(pci_iov_root_configured)
709
710 #endif /* lint || __lint */
|
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26
27 /*
28 * Hypervisor calls called by px nexus driver.
29 */
30
31 #include <sys/asm_linkage.h>
32 #include <sys/hypervisor_api.h>
33 #include <sys/dditypes.h>
34 #include <px_ioapi.h>
35 #include "px_lib4v.h"
36
37 /*
38 * arg0 - devhandle
39 * arg1 - tsbid
40 * arg2 - pages
41 * arg3 - io_attributes
42 * arg4 - io_page_list_p
43 *
44 * ret1 - pages_mapped
45 */
46 ENTRY(hvio_iommu_map)
47 save %sp, -SA(MINFRAME64), %sp
48 mov %i0, %o0
49 mov %i1, %o1
50 mov %i2, %o2
51 mov %i3, %o3
52 mov %i4, %o4
53 mov HVIO_IOMMU_MAP, %o5
54 ta FAST_TRAP
55 brnz %o0, 1f
56 mov %o0, %i0
510 SHIFT_REGS
511 ldx [%o0], %g1
512 stx %g1, [%o1]
513 membar #Sync ! Make sure the loads take
514 mov %g0, %o0
515 done
516 SET_SIZE(px_phys_acc_4v)
517
518 /*
519 * arg0 - devhandle
520 *
521 * ret0 - status
522 */
523 ENTRY(pci_iov_root_configured)
524 mov PCI_IOV_ROOT_CONFIGURED, %o5
525 ta FAST_TRAP
526 retl
527 nop
528 SET_SIZE(pci_iov_root_configured)
529
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