1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26
27 /*
28 * Hypervisor calls called by px nexus driver.
29 */
30
31 #include <sys/asm_linkage.h>
32 #include <sys/hypervisor_api.h>
33 #include <sys/dditypes.h>
34 #include <px_ioapi.h>
35 #include "px_lib4v.h"
36
37 #if defined(lint) || defined(__lint)
38
39 /*ARGSUSED*/
40 uint64_t
41 hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
42 io_attributes_t attr, io_page_list_t *io_page_list_p,
43 pages_t *pages_mapped)
44 { return (0); }
45
46 /*ARGSUSED*/
47 uint64_t
48 hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages,
49 pages_t *pages_demapped)
50 { return (0); }
51
52 /*ARGSUSED*/
53 uint64_t
54 hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p,
55 r_addr_t *r_addr_p)
56 { return (0); }
57
58 /*ARGSUSED*/
59 uint64_t
60 hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr,
61 io_addr_t *io_addr_p)
62 { return (0); }
63
64 /*ARGSUSED*/
65 uint64_t
66 hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status,
67 uint64_t *data_p)
68 { return (0); }
69
70 /*ARGSUSED*/
71 uint64_t
72 hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data,
73 r_addr_t ra2, uint32_t *rdbk_status)
74 { return (0); }
75
76 /*ARGSUSED*/
77 uint64_t
78 hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes,
79 io_sync_direction_t io_sync_direction, size_t *bytes_synched)
80 { return (0); }
81
82 /*ARGSUSED*/
83 uint64_t
84 hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra,
85 uint_t msiq_rec_cnt)
86 { return (0); }
87
88 /*ARGSUSED*/
89 uint64_t
90 hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p,
91 uint_t *msiq_rec_cnt_p)
92 { return (0); }
93
94 /*ARGSUSED*/
95 uint64_t
96 hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
97 pci_msiq_valid_state_t *msiq_valid_state)
98 { return (0); }
99
100 /*ARGSUSED*/
101 uint64_t
102 hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
103 pci_msiq_valid_state_t msiq_valid_state)
104 { return (0); }
105
106 /*ARGSUSED*/
107 uint64_t
108 hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
109 pci_msiq_state_t *msiq_state)
110 { return (0); }
111
112 /*ARGSUSED*/
113 uint64_t
114 hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
115 pci_msiq_state_t msiq_state)
116 { return (0); }
117
118 /*ARGSUSED*/
119 uint64_t
120 hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
121 msiqhead_t *msiq_head)
122 { return (0); }
123
124 /*ARGSUSED*/
125 uint64_t
126 hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
127 msiqhead_t msiq_head)
128 { return (0); }
129
130 /*ARGSUSED*/
131 uint64_t
132 hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
133 msiqtail_t *msiq_tail)
134 { return (0); }
135
136 /*ARGSUSED*/
137 uint64_t
138 hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
139 msiqid_t *msiq_id)
140 { return (0); }
141
142 /*ARGSUSED*/
143 uint64_t
144 hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
145 msiqid_t msiq_id, msi_type_t msitype)
146 { return (0); }
147
148 /*ARGSUSED*/
149 uint64_t
150 hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
151 pci_msi_valid_state_t *msi_valid_state)
152 { return (0); }
153
154 /*ARGSUSED*/
155 uint64_t
156 hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
157 pci_msi_valid_state_t msi_valid_state)
158 { return (0); }
159
160 /*ARGSUSED*/
161 uint64_t
162 hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
163 pci_msi_state_t *msi_state)
164 { return (0); }
165
166 /*ARGSUSED*/
167 uint64_t
168 hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
169 pci_msi_state_t msi_state)
170 { return (0); }
171
172 /*ARGSUSED*/
173 uint64_t
174 hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
175 msiqid_t *msiq_id)
176 { return (0); }
177
178 /*ARGSUSED*/
179 uint64_t
180 hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
181 msiqid_t msiq_id)
182 { return (0); }
183
184 /*ARGSUSED*/
185 uint64_t
186 hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
187 pcie_msg_valid_state_t *msg_valid_state)
188 { return (0); }
189
190 /*ARGSUSED*/
191 uint64_t
192 hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
193 pcie_msg_valid_state_t msg_valid_state)
194 { return (0); }
195
196 /*ARGSUSED*/
197 uint64_t
198 pci_error_send(devhandle_t dev_hdl, devino_t devino, pci_device_t bdf)
199 { return (0); }
200
201 /*
202 * First arg to both of these functions is a dummy, to accomodate how
203 * hv_hpriv() works.
204 */
205 /*ARGSUSED*/
206 int
207 px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr)
208 { return (0); }
209
210 /*ARGSUSED*/
211 uint64_t
212 pci_iov_root_configured(devhandle_t dev_hdl)
213 { return (0); }
214
215 #else /* lint || __lint */
216
217 /*
218 * arg0 - devhandle
219 * arg1 - tsbid
220 * arg2 - pages
221 * arg3 - io_attributes
222 * arg4 - io_page_list_p
223 *
224 * ret1 - pages_mapped
225 */
226 ENTRY(hvio_iommu_map)
227 save %sp, -SA(MINFRAME64), %sp
228 mov %i0, %o0
229 mov %i1, %o1
230 mov %i2, %o2
231 mov %i3, %o3
232 mov %i4, %o4
233 mov HVIO_IOMMU_MAP, %o5
234 ta FAST_TRAP
235 brnz %o0, 1f
236 mov %o0, %i0
237 stuw %o1, [%i5]
238 1:
239 ret
240 restore
241 SET_SIZE(hvio_iommu_map)
242
243 /*
244 * arg0 - devhandle
245 * arg1 - tsbid
246 * arg2 - pages
247 *
248 * ret1 - pages_demapped
249 */
250 ENTRY(hvio_iommu_demap)
251 mov HVIO_IOMMU_DEMAP, %o5
252 ta FAST_TRAP
253 brz,a %o0, 1f
254 stuw %o1, [%o3]
255 1: retl
256 nop
257 SET_SIZE(hvio_iommu_demap)
258
259 /*
260 * arg0 - devhandle
261 * arg1 - tsbid
262 *
263 *
264 * ret0 - status
265 * ret1 - io_attributes
266 * ret2 - r_addr
267 */
268 ENTRY(hvio_iommu_getmap)
269 mov %o2, %o4
270 mov HVIO_IOMMU_GETMAP, %o5
271 ta FAST_TRAP
272 brnz %o0, 1f
273 nop
274 stx %o2, [%o3]
275 st %o1, [%o4]
276 1:
277 retl
278 nop
279 SET_SIZE(hvio_iommu_getmap)
280
281 /*
282 * arg0 - devhandle
283 * arg1 - r_addr
284 * arg2 - io_attributes
285 *
286 *
287 * ret0 - status
288 * ret1 - io_addr
289 */
290 ENTRY(hvio_iommu_getbypass)
291 mov HVIO_IOMMU_GETBYPASS, %o5
292 ta FAST_TRAP
293 brz,a %o0, 1f
294 stx %o1, [%o3]
295 1: retl
296 nop
297 SET_SIZE(hvio_iommu_getbypass)
298
299 /*
300 * arg0 - devhandle
301 * arg1 - r_addr
302 * arg2 - size
303 *
304 * ret1 - error_flag
305 * ret2 - data
306 */
307 ENTRY(hvio_peek)
308 mov HVIO_PEEK, %o5
309 ta FAST_TRAP
310 brnz %o0, 1f
311 nop
312 stx %o2, [%o4]
313 st %o1, [%o3]
314 1:
315 retl
316 nop
317 SET_SIZE(hvio_peek)
318
319 /*
320 * arg0 - devhandle
321 * arg1 - r_addr
322 * arg2 - sizes
323 * arg3 - data
324 * arg4 - r_addr2
325 *
326 * ret1 - error_flag
327 */
328 ENTRY(hvio_poke)
329 save %sp, -SA(MINFRAME64), %sp
330 mov %i0, %o0
331 mov %i1, %o1
332 mov %i2, %o2
333 mov %i3, %o3
334 mov %i4, %o4
335 mov HVIO_POKE, %o5
336 ta FAST_TRAP
337 brnz %o0, 1f
338 mov %o0, %i0
339 stuw %o1, [%i5]
340 1:
341 ret
342 restore
343 SET_SIZE(hvio_poke)
344
345 /*
346 * arg0 - devhandle
347 * arg1 - r_addr
348 * arg2 - num_bytes
349 * arg3 - io_sync_direction
350 *
351 * ret0 - status
352 * ret1 - bytes_synched
353 */
354 ENTRY(hvio_dma_sync)
355 mov HVIO_DMA_SYNC, %o5
356 ta FAST_TRAP
357 brz,a %o0, 1f
358 stx %o1, [%o4]
359 1: retl
360 nop
361 SET_SIZE(hvio_dma_sync)
362
363 /*
364 * arg0 - devhandle
365 * arg1 - msiq_id
366 * arg2 - r_addr
367 * arg3 - nentries
368 *
369 * ret0 - status
370 */
371 ENTRY(hvio_msiq_conf)
372 mov HVIO_MSIQ_CONF, %o5
373 ta FAST_TRAP
374 retl
375 nop
376 SET_SIZE(hvio_msiq_conf)
377
378 /*
379 * arg0 - devhandle
380 * arg1 - msiq_id
381 *
382 * ret0 - status
383 * ret1 - r_addr
384 * ret1 - nentries
385 */
386 ENTRY(hvio_msiq_info)
387 mov %o2, %o4
388 mov HVIO_MSIQ_INFO, %o5
389 ta FAST_TRAP
390 brnz %o0, 1f
391 nop
392 stx %o1, [%o4]
393 stuw %o2, [%o3]
394 1: retl
395 nop
396 SET_SIZE(hvio_msiq_info)
397
398 /*
399 * arg0 - devhandle
400 * arg1 - msiq_id
401 *
402 * ret0 - status
403 * ret1 - msiq_valid_state
404 */
405 ENTRY(hvio_msiq_getvalid)
406 mov HVIO_MSIQ_GETVALID, %o5
407 ta FAST_TRAP
408 brz,a %o0, 1f
409 stuw %o1, [%o2]
410 1: retl
411 nop
412 SET_SIZE(hvio_msiq_getvalid)
413
414 /*
415 * arg0 - devhandle
416 * arg1 - msiq_id
417 * arg2 - msiq_valid_state
418 *
419 * ret0 - status
420 */
421 ENTRY(hvio_msiq_setvalid)
422 mov HVIO_MSIQ_SETVALID, %o5
423 ta FAST_TRAP
424 retl
425 nop
426 SET_SIZE(hvio_msiq_setvalid)
427
428 /*
429 * arg0 - devhandle
430 * arg1 - msiq_id
431 *
432 * ret0 - status
433 * ret1 - msiq_state
434 */
435 ENTRY(hvio_msiq_getstate)
436 mov HVIO_MSIQ_GETSTATE, %o5
437 ta FAST_TRAP
438 brz,a %o0, 1f
439 stuw %o1, [%o2]
440 1: retl
441 nop
442 SET_SIZE(hvio_msiq_getstate)
443
444 /*
445 * arg0 - devhandle
446 * arg1 - msiq_id
447 * arg2 - msiq_state
448 *
449 * ret0 - status
450 */
451 ENTRY(hvio_msiq_setstate)
452 mov HVIO_MSIQ_SETSTATE, %o5
453 ta FAST_TRAP
454 retl
455 nop
456 SET_SIZE(hvio_msiq_setstate)
457
458 /*
459 * arg0 - devhandle
460 * arg1 - msiq_id
461 *
462 * ret0 - status
463 * ret1 - msiq_head
464 */
465 ENTRY(hvio_msiq_gethead)
466 mov HVIO_MSIQ_GETHEAD, %o5
467 ta FAST_TRAP
468 brz,a %o0, 1f
469 stx %o1, [%o2]
470 1: retl
471 nop
472 SET_SIZE(hvio_msiq_gethead)
473
474 /*
475 * arg0 - devhandle
476 * arg1 - msiq_id
477 * arg2 - msiq_head
478 *
479 * ret0 - status
480 */
481 ENTRY(hvio_msiq_sethead)
482 mov HVIO_MSIQ_SETHEAD, %o5
483 ta FAST_TRAP
484 retl
485 nop
486 SET_SIZE(hvio_msiq_sethead)
487
488 /*
489 * arg0 - devhandle
490 * arg1 - msiq_id
491 *
492 * ret0 - status
493 * ret1 - msiq_tail
494 */
495 ENTRY(hvio_msiq_gettail)
496 mov HVIO_MSIQ_GETTAIL, %o5
497 ta FAST_TRAP
498 brz,a %o0, 1f
499 stx %o1, [%o2]
500 1: retl
501 nop
502 SET_SIZE(hvio_msiq_gettail)
503
504 /*
505 * arg0 - devhandle
506 * arg1 - msi_num
507 *
508 * ret0 - status
509 * ret1 - msiq_id
510 */
511 ENTRY(hvio_msi_getmsiq)
512 mov HVIO_MSI_GETMSIQ, %o5
513 ta FAST_TRAP
514 brz,a %o0, 1f
515 stuw %o1, [%o2]
516 1: retl
517 nop
518 SET_SIZE(hvio_msi_getmsiq)
519
520 /*
521 * arg0 - devhandle
522 * arg1 - msi_num
523 * arg2 - msiq_id
524 * arg2 - msitype
525 *
526 * ret0 - status
527 */
528 ENTRY(hvio_msi_setmsiq)
529 mov HVIO_MSI_SETMSIQ, %o5
530 ta FAST_TRAP
531 retl
532 nop
533 SET_SIZE(hvio_msi_setmsiq)
534
535 /*
536 * arg0 - devhandle
537 * arg1 - msi_num
538 *
539 * ret0 - status
540 * ret1 - msi_valid_state
541 */
542 ENTRY(hvio_msi_getvalid)
543 mov HVIO_MSI_GETVALID, %o5
544 ta FAST_TRAP
545 brz,a %o0, 1f
546 stuw %o1, [%o2]
547 1: retl
548 nop
549 SET_SIZE(hvio_msi_getvalid)
550
551 /*
552 * arg0 - devhandle
553 * arg1 - msi_num
554 * arg2 - msi_valid_state
555 *
556 * ret0 - status
557 */
558 ENTRY(hvio_msi_setvalid)
559 mov HVIO_MSI_SETVALID, %o5
560 ta FAST_TRAP
561 retl
562 nop
563 SET_SIZE(hvio_msi_setvalid)
564
565 /*
566 * arg0 - devhandle
567 * arg1 - msi_num
568 *
569 * ret0 - status
570 * ret1 - msi_state
571 */
572 ENTRY(hvio_msi_getstate)
573 mov HVIO_MSI_GETSTATE, %o5
574 ta FAST_TRAP
575 brz,a %o0, 1f
576 stuw %o1, [%o2]
577 1: retl
578 nop
579 SET_SIZE(hvio_msi_getstate)
580
581 /*
582 * arg0 - devhandle
583 * arg1 - msi_num
584 * arg2 - msi_state
585 *
586 * ret0 - status
587 */
588 ENTRY(hvio_msi_setstate)
589 mov HVIO_MSI_SETSTATE, %o5
590 ta FAST_TRAP
591 retl
592 nop
593 SET_SIZE(hvio_msi_setstate)
594
595 /*
596 * arg0 - devhandle
597 * arg1 - msg_type
598 *
599 * ret0 - status
600 * ret1 - msiq_id
601 */
602 ENTRY(hvio_msg_getmsiq)
603 mov HVIO_MSG_GETMSIQ, %o5
604 ta FAST_TRAP
605 brz,a %o0, 1f
606 stuw %o1, [%o2]
607 1: retl
608 nop
609 SET_SIZE(hvio_msg_getmsiq)
610
611 /*
612 * arg0 - devhandle
613 * arg1 - msg_type
614 * arg2 - msiq_id
615 *
616 * ret0 - status
617 */
618 ENTRY(hvio_msg_setmsiq)
619 mov HVIO_MSG_SETMSIQ, %o5
620 ta FAST_TRAP
621 retl
622 nop
623 SET_SIZE(hvio_msg_setmsiq)
624
625 /*
626 * arg0 - devhandle
627 * arg1 - msg_type
628 *
629 * ret0 - status
630 * ret1 - msg_valid_state
631 */
632 ENTRY(hvio_msg_getvalid)
633 mov HVIO_MSG_GETVALID, %o5
634 ta FAST_TRAP
635 brz,a %o0, 1f
636 stuw %o1, [%o2]
637 1: retl
638 nop
639 SET_SIZE(hvio_msg_getvalid)
640
641 /*
642 * arg0 - devhandle
643 * arg1 - msg_type
644 * arg2 - msg_valid_state
645 *
646 * ret0 - status
647 */
648 ENTRY(hvio_msg_setvalid)
649 mov HVIO_MSG_SETVALID, %o5
650 ta FAST_TRAP
651 retl
652 nop
653 SET_SIZE(hvio_msg_setvalid)
654
655 /*
656 * arg0 - devhandle
657 * arg1 - devino
658 * arg2 - pci_device
659 *
660 * ret0 - status
661 */
662 ENTRY(pci_error_send)
663 mov PCI_ERROR_SEND, %o5
664 ta FAST_TRAP
665 retl
666 nop
667 SET_SIZE(pci_error_send)
668
669 #define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3
670
671 ! px_phys_acc_4v: Do physical address read.
672 !
673 ! After SHIFT_REGS:
674 ! %o0 is "from" address
675 ! %o1 is "to" address
676 !
677 ! Assumes 8 byte data and that alignment is correct.
678 !
679 ! Always returns success (0) in %o0
680
681 ! px_phys_acc_4v must not be split across pages.
682 !
683 ! ATTN: Be sure that the alignment value is larger than the size of
684 ! the px_phys_acc_4v function.
685 !
686 .align 0x40
687
688 ENTRY(px_phys_acc_4v)
689
690 SHIFT_REGS
691 ldx [%o0], %g1
692 stx %g1, [%o1]
693 membar #Sync ! Make sure the loads take
694 mov %g0, %o0
695 done
696 SET_SIZE(px_phys_acc_4v)
697
698 /*
699 * arg0 - devhandle
700 *
701 * ret0 - status
702 */
703 ENTRY(pci_iov_root_configured)
704 mov PCI_IOV_ROOT_CONFIGURED, %o5
705 ta FAST_TRAP
706 retl
707 nop
708 SET_SIZE(pci_iov_root_configured)
709
710 #endif /* lint || __lint */