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--- old/usr/src/uts/sun4v/cpu/niagara2_asm.s
+++ new/usr/src/uts/sun4v/cpu/niagara2_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
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16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 -#if !defined(lint)
27 26 #include "assym.h"
28 -#endif
29 27
30 28 /*
31 29 * Niagara2 processor specific assembly routines
32 30 */
33 31
34 32 #include <sys/asm_linkage.h>
35 33 #include <sys/machasi.h>
36 34 #include <sys/machparam.h>
37 35 #include <sys/hypervisor_api.h>
38 36 #include <sys/niagara2regs.h>
39 37 #include <sys/machasi.h>
40 38 #include <sys/niagaraasi.h>
41 39 #include <vm/hat_sfmmu.h>
42 40
43 -#if defined(lint)
44 -/*ARGSUSED*/
45 -uint64_t
46 -hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
47 -{ return (0); }
48 -
49 -/*ARGSUSED*/
50 -uint64_t
51 -hv_niagara_setperf(uint64_t perfreg, uint64_t data)
52 -{ return (0); }
53 -
54 -#else /* lint */
55 -
56 41 /*
57 42 * hv_niagara_getperf(uint64_t perfreg, uint64_t *datap)
58 43 */
59 44 ENTRY(hv_niagara_getperf)
60 45 mov %o1, %o4 ! save datap
61 46 #if defined(NIAGARA2_IMPL)
62 47 mov HV_NIAGARA2_GETPERF, %o5
63 48 #elif defined(VFALLS_IMPL)
64 49 mov HV_VFALLS_GETPERF, %o5
65 50 #elif defined(KT_IMPL)
66 51 mov HV_KT_GETPERF, %o5
67 52 #endif
68 53 ta FAST_TRAP
69 54 brz,a %o0, 1f
70 55 stx %o1, [%o4]
71 56 1:
72 57 retl
73 58 nop
74 59 SET_SIZE(hv_niagara_getperf)
75 60
76 61 /*
77 62 * hv_niagara_setperf(uint64_t perfreg, uint64_t data)
78 63 */
79 64 ENTRY(hv_niagara_setperf)
80 65 #if defined(NIAGARA2_IMPL)
81 66 mov HV_NIAGARA2_SETPERF, %o5
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82 67 #elif defined(VFALLS_IMPL)
83 68 mov HV_VFALLS_SETPERF, %o5
84 69 #elif defined(KT_IMPL)
85 70 mov HV_KT_SETPERF, %o5
86 71 #endif
87 72 ta FAST_TRAP
88 73 retl
89 74 nop
90 75 SET_SIZE(hv_niagara_setperf)
91 76
92 -#endif /* !lint */
93 -
94 -#if defined (lint)
95 77 /*
96 78 * Invalidate all of the entries within the TSB, by setting the inv bit
97 79 * in the tte_tag field of each tsbe.
98 80 *
99 81 * We take advantage of the fact that the TSBs are page aligned and a
100 82 * multiple of PAGESIZE to use ASI_BLK_INIT_xxx ASI.
101 83 *
102 84 * See TSB_LOCK_ENTRY and the miss handlers for how this works in practice
103 85 * (in short, we set all bits in the upper word of the tag, and we give the
104 86 * invalid bit precedence over other tag bits in both places).
105 87 */
106 -/*ARGSUSED*/
107 -void
108 -cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes)
109 -{}
110 -
111 -#else /* lint */
112 -
113 88 ENTRY(cpu_inv_tsb)
114 89
115 90 /*
116 91 * The following code assumes that the tsb_base (%o0) is 256 bytes
117 92 * aligned and the tsb_bytes count is multiple of 256 bytes.
118 93 */
119 94
120 95 wr %g0, ASI_BLK_INIT_ST_QUAD_LDD_P, %asi
121 96 set TSBTAG_INVALID, %o2
122 97 sllx %o2, 32, %o2 ! INV bit in upper 32 bits of the tag
123 98 1:
124 99 stxa %o2, [%o0+0x0]%asi
125 100 stxa %o2, [%o0+0x40]%asi
126 101 stxa %o2, [%o0+0x80]%asi
127 102 stxa %o2, [%o0+0xc0]%asi
128 103
129 104 stxa %o2, [%o0+0x10]%asi
130 105 stxa %o2, [%o0+0x20]%asi
131 106 stxa %o2, [%o0+0x30]%asi
132 107
133 108 stxa %o2, [%o0+0x50]%asi
134 109 stxa %o2, [%o0+0x60]%asi
135 110 stxa %o2, [%o0+0x70]%asi
136 111
137 112 stxa %o2, [%o0+0x90]%asi
138 113 stxa %o2, [%o0+0xa0]%asi
139 114 stxa %o2, [%o0+0xb0]%asi
140 115
141 116 stxa %o2, [%o0+0xd0]%asi
142 117 stxa %o2, [%o0+0xe0]%asi
143 118 stxa %o2, [%o0+0xf0]%asi
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144 119
145 120 subcc %o1, 0x100, %o1
146 121 bgu,pt %ncc, 1b
147 122 add %o0, 0x100, %o0
148 123
149 124 membar #Sync
150 125 retl
151 126 nop
152 127
153 128 SET_SIZE(cpu_inv_tsb)
154 -#endif /* lint */
155 129
156 -#if defined (lint)
157 -/*
158 - * This is CPU specific delay routine for atomic backoff. It is used in case
159 - * of Niagara2 and VF CPUs. The rd instruction uses less resources than casx
160 - * on these CPUs.
161 - */
162 -void
163 -cpu_atomic_delay(void)
164 -{}
165 -#else /* lint */
166 130 ENTRY(cpu_atomic_delay)
167 131 rd %ccr, %g0
168 132 rd %ccr, %g0
169 133 retl
170 134 rd %ccr, %g0
171 135 SET_SIZE(cpu_atomic_delay)
172 -#endif /* lint */
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