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--- old/usr/src/uts/sun4u/opl/ml/drmach_asm.s
+++ new/usr/src/uts/sun4u/opl/ml/drmach_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
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23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 /*
28 28 * This file is through cpp before being used as
29 29 * an inline. It contains support routines used
30 30 * only by DR for the copy-rename sequence.
31 31 */
32 32
33 -#if defined(lint)
34 -#include <sys/types.h>
35 -#else
36 33 #include "assym.h"
37 34 #include "drmach_offsets.h"
38 -#endif /* lint */
39 35
40 36 #include <sys/asm_linkage.h>
41 37 #include <sys/param.h>
42 38 #include <sys/privregs.h>
43 39 #include <sys/spitregs.h>
44 40 #include <sys/mmu.h>
45 41 #include <sys/machthread.h>
46 42 #include <sys/pte.h>
47 43 #include <sys/stack.h>
48 44 #include <sys/vis.h>
49 45 #include <sys/intreg.h>
50 46 #include <sys/cheetahregs.h>
51 47 #include <sys/drmach.h>
52 48 #include <sys/sbd_ioctl.h>
53 49
54 -#if !defined(lint)
55 -
56 50 /*
57 51 * turn off speculative mode to prevent unwanted memory access
58 52 * when we are in the FMEM loops
59 53 */
60 54
61 55 #define FJSV_SPECULATIVE_OFF(reg, tmp1, tmp2) \
62 56 rdpr %pstate, reg ;\
63 57 andn reg, PSTATE_IE, tmp1 ;\
64 58 wrpr %g0, tmp1, %pstate ;\
65 59 ldxa [%g0]ASI_MCNTL, tmp1 ;\
66 60 set 1, tmp2 ;\
67 61 sllx tmp2, MCNTL_SPECULATIVE_SHIFT, tmp2 ;\
68 62 or tmp1, tmp2, tmp1 ;\
69 63 stxa tmp1, [%g0]ASI_MCNTL ;\
70 64 membar #Sync
71 -#endif
72 65
73 66
74 -#if defined(lint)
75 -/*ARGSUSED*/
76 -void
77 -drmach_fmem_loop_script(caddr_t critical, int size, caddr_t stat)
78 -{ return; }
79 -#else /* lint */
80 67 .align 8
81 68 ENTRY_NP(drmach_fmem_loop_script)
82 69 /* turn off speculative mode */
83 70 FJSV_SPECULATIVE_OFF(%o5, %o3, %o4);
84 71
85 72 /* read the critical region to get everything in the cache */
86 73 mov %o0, %o3
87 74 0:
88 75 ldx [%o3], %o4
89 76 sub %o1, 8, %o1
90 77 brnz %o1, 0b
91 78 add %o3, 8, %o3
92 79
93 80 /* clear L2_CTRL_UGE_TRAP error bit */
94 81 mov ASI_L2_CTRL_RW_ADDR, %o1
95 82 ldxa [%o1]ASI_L2_CTRL, %o3
96 83 sethi %hi(ASI_L2_CTRL_UGE_TRAP), %o4
97 84 btst %o3, %o4
98 85 bz,pn %xcc, 1f
99 86 nop
100 87 stxa %o4, [%o1]ASI_L2_CTRL
101 88
102 89 /* now tell the master CPU that we are ready */
103 90 1:
104 91 set FMEM_LOOP_FMEM_READY, %o3
105 92 stb %o3, [%o2]
106 93 membar #Sync
107 94 ba 5f
108 95 nop
109 96
110 97 /*
111 98 * note that we branch to 5f, which branches right back to 2 here.
112 99 * The trick is that when that branch instruction has already been
113 100 * patched to a branch to itself - an infinite loop.
114 101 * The master thread will patch it back to "ba 2b" when it
115 102 * completes.
116 103 */
117 104
118 105 /* Once we are back, we first check if there has been any
119 106 * L2_CTRL_UGE_TRAP errors, if so we have to fail the
120 107 * operation. This will cause a panic because the system
121 108 * is already in inconsistent state.
122 109 */
123 110 2:
124 111 mov ASI_L2_CTRL_RW_ADDR, %o3
125 112 ldxa [%o3]ASI_L2_CTRL, %o3
126 113 sethi %hi(ASI_L2_CTRL_UGE_TRAP), %o4
127 114 btst %o3, %o4
128 115 bz,pn %xcc, 3f
129 116 mov %g0, %o4
130 117 set EOPL_FMEM_HW_ERROR, %o4
131 118
132 119 /* set error code and stat code */
133 120 3:
134 121 set FMEM_LOOP_DONE, %o3
135 122 stb %o3, [%o2]
136 123
137 124 /* turn on speculative mode again */
138 125 ldxa [%g0]ASI_MCNTL, %o0
139 126 set 1, %o1
140 127 sllx %o1, MCNTL_SPECULATIVE_SHIFT, %o1
141 128 andn %o0, %o1, %o0
142 129 ba 4f
143 130 nop
144 131 .align 32
145 132 4:
146 133 stxa %o0, [%g0]ASI_MCNTL
147 134 membar #Sync
148 135 wrpr %g0, %o5, %pstate
149 136 retl
150 137 mov %o4, %o0
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151 138 .align 8
152 139 5:
153 140 ALTENTRY(drmach_fmem_loop_script_rtn)
154 141 /*
155 142 * busy wait will affect sibling strands so
156 143 * we put sleep instruction in the delay slot
157 144 */
158 145 ba 2b
159 146 .word 0x81b01060
160 147 SET_SIZE(drmach_fmem_loop_script)
161 -#endif /* lint */
162 148
163 -#if defined(lint)
164 -/*ARGSUSED*/
165 -void
166 -drmach_flush_icache(void)
167 -{ return; }
168 -#else /* lint */
169 149 .align 8
170 150 ENTRY_NP(drmach_flush_icache)
171 151 stxa %g0, [%g0]ASI_ALL_FLUSH_L1I
172 152 membar #Sync
173 153 retl
174 154 nop
175 155 SET_SIZE(drmach_flush_icache)
176 -#endif
177 156
178 -#if defined(lint)
179 -/*ARGSUSED*/
180 -int
181 -drmach_fmem_exec_script(caddr_t critical, int size)
182 -{ return (0); }
183 -#else /* lint */
184 157 .align 32
185 158 ENTRY_NP(drmach_fmem_exec_script)
186 159 /* turn off speculative mode */
187 160 FJSV_SPECULATIVE_OFF(%o5, %o3, %o4);
188 161 /* save locals to save area */
189 162 add %o0, SAVE_LOCAL, %o2
190 163 stx %l0, [%o2+8*0]
191 164 stx %l1, [%o2+8*1]
192 165 stx %l2, [%o2+8*2]
193 166 stx %l3, [%o2+8*3]
194 167 stx %l4, [%o2+8*4]
195 168 stx %l5, [%o2+8*5]
196 169 stx %l6, [%o2+8*6]
197 170 stx %l7, [%o2+8*7]
198 171 mov %o5, %l6
199 172 /* l7 is set only when FMEM cmd is issued to SCF */
200 173 mov %g0, %l7
201 174
202 175 /* read the critical region to put everything in the cache */
203 176 mov %o0, %o2
204 177 0:
205 178 ldx [%o2], %o4
206 179 sub %o1, 8, %o1
207 180 brnz %o1, 0b
208 181 add %o2, 8, %o2
209 182 ba 4f
210 183 nop
211 184
212 185 /* we branch to 4f but eventually we branch back here to finish up */
213 186 1:
214 187 mov %l6, %o5
215 188 /*
216 189 * save some registers for debugging
217 190 * l0 - SCF_REG_BASE
218 191 * l1 - SCF_TD
219 192 * l2 - SCF_TD + 8
220 193 * l5 - DELAY
221 194 */
222 195 add %o0, SAVE_LOG, %o1
223 196 stx %l0, [%o1+8*0]
224 197 stx %l1, [%o1+8*1]
225 198 stx %l2, [%o1+8*2]
226 199 stx %l5, [%o1+8*3]
227 200
228 201 add %o0, FMEM_ISSUED, %o1
229 202 st %l7, [%o1]
230 203
231 204 /* Check for L2_CTRL_UGE_TRAP error */
232 205 mov ASI_L2_CTRL_RW_ADDR, %l0
233 206 ldxa [%l0]ASI_L2_CTRL, %l1
234 207 sethi %hi(ASI_L2_CTRL_UGE_TRAP), %l2
235 208 btst %l1, %l2
236 209 bz,pn %xcc, 2f
237 210 nop
238 211 set EOPL_FMEM_HW_ERROR, %o4
239 212 2:
240 213 /* restore all locals */
241 214 add %o0, SAVE_LOCAL, %o1
242 215 ldx [%o1+8*0], %l0
243 216 ldx [%o1+8*1], %l1
244 217 ldx [%o1+8*2], %l2
245 218 ldx [%o1+8*3], %l3
246 219 ldx [%o1+8*4], %l4
247 220 ldx [%o1+8*5], %l5
248 221 ldx [%o1+8*6], %l6
249 222 ldx [%o1+8*7], %l7
250 223
251 224 /* turn on speculative mode */
252 225 ldxa [%g0]ASI_MCNTL, %o1
253 226 set 1, %o2
254 227 sllx %o2, MCNTL_SPECULATIVE_SHIFT, %o2
255 228 andn %o1, %o2, %o1
256 229 ba 3f
257 230 nop
258 231 .align 32
259 232 3:
260 233 stxa %o1, [%g0]ASI_MCNTL
261 234 membar #Sync
262 235 /* return error code here */
263 236 mov %o4, %o0
264 237 retl
265 238 wrpr %g0, %o5, %pstate
266 239
267 240 /* clear L2_CTRL_UGE_TRAP error bit */
268 241 4:
269 242 mov ASI_L2_CTRL_RW_ADDR, %l0
270 243 ldxa [%l0]ASI_L2_CTRL, %l1
271 244 sethi %hi(ASI_L2_CTRL_UGE_TRAP), %l2
272 245 btst %l1, %l2
273 246 bz,pn %xcc, 5f
274 247 nop
275 248 stxa %l2, [%l0]ASI_L2_CTRL
276 249 5:
277 250 /* set up the register locations and parameters */
278 251 ldx [%o0 + SCF_REG_BASE], %l0
279 252 ldx [%o0 + SCF_TD], %l1
280 253 ldx [%o0 + SCF_TD+8], %l2
281 254 ldx [%o0 + DELAY], %l5
282 255
283 256 /* check if SCF is ONLINE */
284 257 add %l0, SCF_STATUS_EX, %o1
285 258 lduwa [%o1]ASI_IO, %o2
286 259 sethi %hi(SCF_STATUS_EX_ONLINE), %o3
287 260 btst %o2, %o3
288 261 bne %xcc, 6f
289 262 nop
290 263 set EOPL_FMEM_SCF_OFFLINE, %o4
291 264 ba 1b
292 265 nop
293 266
294 267 /* check if SCF is busy */
295 268 add %l0, SCF_COMMAND, %o1
296 269 lduha [%o1]ASI_IO, %o2
297 270 sethi %hi(SCF_CMD_BUSY), %o3
298 271 btst %o2, %o3
299 272 be %xcc, 6f
300 273 nop
301 274 set EOPL_FMEM_SCF_BUSY, %o4
302 275 ba 1b
303 276 nop
304 277
305 278 /* clear STATUS bit */
306 279 6:
307 280 add %l0, SCF_STATUS, %o1
308 281 lduha [%o1]ASI_IO, %o2
309 282 sethi %hi(SCF_STATUS_READY), %o3
310 283 btst %o2, %o3
311 284 be %xcc, 7f
312 285 nop
313 286 stha %o3, [%o1]ASI_IO
314 287
315 288 /* clear CMD_COMPLETE bit */
316 289 7:
317 290 mov SCF_STATUS_CMD_COMPLETE, %o3
318 291 btst %o2, %o3
319 292 be,a %xcc, 8f
320 293 nop
321 294 stha %o3, [%o1]ASI_IO
322 295 8:
323 296 add %l0, (SCF_TDATA+0xe), %o1
324 297 mov %l2, %o4
325 298 mov SCF_RETRY_CNT, %o5
326 299
327 300 sethi %hi(0xffff), %l2
328 301 or %l2, %lo(0xffff), %l2
329 302
330 303 and %o4, %l2, %o3
331 304
332 305 /*
333 306 * o1 points to SCFBASE.SCF_TDATA[0xe]
334 307 * l0 points to SCFBASE
335 308 * crticial->SCF_TD[0] = source board #
336 309 * crticial->SCF_TD[1] = target board #
337 310 * l1 = critical->SCF_TD[0 - 7]
338 311 * l2 = 0xffff
339 312 * o4 = critical->SCF_TD[8 - 15]
340 313 * o3 = (*o4) & 0xffff
341 314
342 315 /*
343 316 * Because there is no parity protection on the ebus
344 317 * we read the data back after the write to verify
345 318 * we write 2 bytes at a time.
346 319 * If the data read is not the same as data written
347 320 * we retry up to a limit of SCF_RETRY_CNT
348 321 */
349 322 9:
350 323 stha %o3, [%o1]ASI_IO
351 324 lduha [%o1]ASI_IO, %o2
352 325 sub %o5, 1, %o5
353 326 brnz %o5, 7f
354 327 nop
355 328 set EOPL_FMEM_RETRY_OUT, %o4
356 329 ba 1b
357 330 nop
358 331 7:
359 332 cmp %o2, %o3
360 333 bne,a 9b
361 334 nop
362 335
363 336 sub %o1, %l0, %o2
364 337 cmp %o2, (SCF_TDATA+0x8)
365 338 bne %xcc, 2f
366 339 srlx %o4, 16, %o4
367 340 mov %l1, %o4
368 341
369 342 /* if we have reach TDATA+8, we switch to l1 */
370 343 /* XXX: Why we need 2 loops??? */
371 344 2:
372 345 sub %o1, 2, %o1
373 346 mov SCF_RETRY_CNT, %o5
374 347 and %o4, %l2, %o3
375 348
376 349 sub %o1, %l0, %o2
377 350 cmp %o2, (SCF_TDATA)
378 351 bge,a 9b
379 352 nop
380 353
381 354 /* if we reach TDATA, we are done */
382 355
383 356 /* read from SCF back to our buffer for debugging */
384 357 add %l0, (SCF_TDATA), %o1
385 358 ldxa [%o1]ASI_IO, %o2
386 359 stx %o2, [%o0+SCF_TD]
387 360
388 361 add %l0, (SCF_TDATA+8), %o1
389 362 ldxa [%o1]ASI_IO, %o2
390 363 stx %o2, [%o0+SCF_TD+8]
391 364
392 365 /* The following code conforms to the FMEM
393 366 sequence (4) as described in the Columbus2
394 367 logical spec section 4.6
395 368 */
396 369
397 370 /* read from SCF SB INFO register */
398 371 sethi %hi(SCF_SB_INFO_OFFSET), %o2
399 372 or %o2, %lo(SCF_SB_INFO_OFFSET), %o2
400 373 add %l0, %o2, %o1
401 374 lduba [%o1]ASI_IO, %o2
402 375
403 376 /* If BUSY bit is set, abort */
404 377 or %g0, (SCF_SB_INFO_BUSY), %o1
405 378 btst %o1, %o2
406 379 set EOPL_FMEM_SCF_BUSY, %o4
407 380 bne 1b
408 381 nop
409 382
410 383 rd STICK, %l1
411 384 add %l5, %l1, %l5
412 385
413 386 /* Now tell SCF to do it */
414 387 add %l0, SCF_COMMAND, %o1
415 388
416 389 /* 0x10A6 is the magic command */
417 390 sethi %hi(0x10A6), %o2
418 391 or %o2, %lo(0x10A6), %o2
419 392 stha %o2, [%o1]ASI_IO
420 393
421 394 mov 1, %l7 ! FMEM is issued
422 395
423 396 add %l0, SCF_STATUS, %o1
424 397 sethi %hi(SCF_STATUS_READY), %o2
425 398 mov SCF_STATUS_CMD_COMPLETE, %o3
426 399
427 400 /* read STATUS_READY bit and clear it only if it is set */
428 401 /* XXX: this STATUS_READY checking seems meaningless */
429 402 3:
430 403 lduha [%o1]ASI_IO, %o4
431 404 btst %o2, %o4
432 405 be %xcc, 4f ! STATUS_READY is not set
433 406 nop
434 407 stha %o2, [%o1]ASI_IO ! Clear if the bit is set
435 408
436 409 /* check CMD_COMPLETE bit and clear */
437 410 4:
438 411 btst %o3, %o4
439 412 be %xcc, 5f ! CMD_COMPLETE is not set
440 413 nop
441 414 stha %o3, [%o1]ASI_IO ! Now we are done and clear it
442 415 ba %xcc, 6f
443 416 mov ESBD_NOERROR, %o4
444 417
445 418 /* timeout delay checking */
446 419 5:
447 420 rd STICK, %l2
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448 421 cmp %l5, %l2
449 422 bge %xcc, 3b
450 423 nop
451 424 set EOPL_FMEM_TIMEOUT, %o4
452 425
453 426 /* we are done or timed out */
454 427 6:
455 428 ba,a 1b
456 429 nop
457 430 SET_SIZE(drmach_fmem_exec_script)
458 -#endif /* lint */
459 431
460 -#if defined(lint)
461 -/*ARGSUSED*/
462 -void
463 -drmach_fmem_exec_script_end(caddr_t critical, int size)
464 -{ return; }
465 -#else /* lint */
466 432 ENTRY_NP(drmach_fmem_exec_script_end)
467 433 nop
468 434 SET_SIZE(drmach_fmem_exec_script_end)
469 -#endif /* lint */
470 435
471 -#if defined(lint)
472 -uint64_t
473 -patch_inst(uint64_t *x, uint64_t y)
474 -{
475 - *x = y;
476 - return (0);
477 -}
478 -
479 -#else /* lint */
480 -
481 436 ENTRY_NP(patch_inst)
482 437 ldx [%o0], %o2
483 438 casx [%o0], %o2, %o1
484 439 flush %o0
485 440 membar #Sync
486 441 ldx [%o0], %o2
487 442 retl
488 443 mov %o2, %o0
489 444 SET_SIZE(patch_inst)
490 445
491 -#endif /* lint */
492 -
493 -#if defined(lint)
494 -void
495 -drmach_sys_trap()
496 -{
497 -}
498 -#else /* lint */
499 446 ENTRY_NP(drmach_sys_trap)
500 447 mov -1, %g4
501 448 set sys_trap, %g5
502 449 jmp %g5
503 450 nop
504 451 SET_SIZE(drmach_sys_trap)
505 -#endif /* lint */
506 452
507 -#if defined(lint)
508 -uint64_t
509 -drmach_get_stick()
510 -{
511 - return (0);
512 -}
513 -#else /* lint */
514 453 ENTRY_NP(drmach_get_stick)
515 454 retl
516 455 rd STICK, %o0
517 456 SET_SIZE(drmach_get_stick)
518 -#endif /* lint */
519 457
520 -#if defined(lint)
521 -/*ARGSUSED*/
522 -void
523 -drmach_flush(drmach_copy_rename_critical_t *x, uint_t y)
524 -{}
525 -
526 -#else /* lint */
527 458 ENTRY_NP(drmach_flush)
528 459 mov %o0, %o2
529 460 0:
530 461 flush %o2
531 462 sub %o1, 8, %o1
532 463 brnz %o1, 0b
533 464 add %o2, 8, %o2
534 465 retl
535 466 nop
536 467 SET_SIZE(drmach_flush)
537 -#endif /* lint */
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