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--- old/usr/src/uts/sun4u/ml/mach_subr_asm.s
+++ new/usr/src/uts/sun4u/ml/mach_subr_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
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20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 26 /*
27 27 * General machine architecture & implementation specific
28 28 * assembly language routines.
29 29 */
30 -#if defined(lint)
31 -#include <sys/types.h>
32 -#include <sys/t_lock.h>
33 -#else /* lint */
34 30 #include "assym.h"
35 -#endif /* lint */
36 31
37 32 #include <sys/asm_linkage.h>
38 33 #include <sys/machsystm.h>
39 34 #include <sys/machthread.h>
40 35 #include <sys/privregs.h>
41 36 #include <sys/cmpregs.h>
42 37 #include <sys/clock.h>
43 38 #include <sys/fpras.h>
44 39
45 -#if defined(lint)
46 -
47 -uint64_t
48 -ultra_gettick(void)
49 -{ return (0); }
50 -
51 -#else /* lint */
52 -
53 40 /*
54 41 * This isn't the routine you're looking for.
55 42 *
56 43 * The routine simply returns the value of %tick on the *current* processor.
57 44 * Most of the time, gettick() [which in turn maps to %stick on platforms
58 45 * that have different CPU %tick rates] is what you want.
59 46 */
60 47
61 48 ENTRY(ultra_gettick)
62 49 retl
63 50 rdpr %tick, %o0
64 51 SET_SIZE(ultra_gettick)
65 52
66 -#endif /* lint */
67 -
68 -#if defined(lint)
69 -
70 -/*ARGSUSED*/
71 -int
72 -getprocessorid(void)
73 -{ return (0); }
74 -
75 -#else /* lint */
76 -
77 53 /*
78 54 * Get the processor ID.
79 55 * === MID reg as specified in 15dec89 sun4u spec, sec 5.4.3
80 56 */
81 57
82 58 ENTRY(getprocessorid)
83 59 CPU_INDEX(%o0, %o1)
84 60 retl
85 61 nop
86 62 SET_SIZE(getprocessorid)
87 63
88 -#endif /* lint */
89 -
90 -#if defined(lint)
91 -/*ARGSUSED*/
92 -void
93 -set_error_enable_tl1(uint64_t neer, uint64_t action)
94 -{}
95 -
96 -/* ARGSUSED */
97 -void
98 -set_error_enable(uint64_t neer)
99 -{}
100 -
101 -uint64_t
102 -get_error_enable()
103 -{
104 - return ((uint64_t)0);
105 -}
106 -#else /* lint */
107 -
108 64 ENTRY(set_error_enable_tl1)
109 65 cmp %g2, EER_SET_ABSOLUTE
110 66 be %xcc, 1f
111 67 nop
112 68 ldxa [%g0]ASI_ESTATE_ERR, %g3
113 69 membar #Sync
114 70 cmp %g2, EER_SET_SETBITS
115 71 be,a %xcc, 1f
116 72 or %g3, %g1, %g1
117 73 andn %g3, %g1, %g1 /* EER_SET_CLRBITS */
118 74 1:
119 75 stxa %g1, [%g0]ASI_ESTATE_ERR /* ecache error enable reg */
120 76 membar #Sync
121 77 retry
122 78 SET_SIZE(set_error_enable_tl1)
123 79
124 80 ENTRY(set_error_enable)
125 81 stxa %o0, [%g0]ASI_ESTATE_ERR /* ecache error enable reg */
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126 82 membar #Sync
127 83 retl
128 84 nop
129 85 SET_SIZE(set_error_enable)
130 86
131 87 ENTRY(get_error_enable)
132 88 retl
133 89 ldxa [%g0]ASI_ESTATE_ERR, %o0 /* ecache error enable reg */
134 90 SET_SIZE(get_error_enable)
135 91
136 -#endif /* lint */
137 -
138 -#if defined(lint)
139 -void
140 -get_asyncflt(uint64_t *afsr)
141 -{
142 - afsr = afsr;
143 -}
144 -#else /* lint */
145 -
146 92 ENTRY(get_asyncflt)
147 93 ldxa [%g0]ASI_AFSR, %o1 ! afsr reg
148 94 retl
149 95 stx %o1, [%o0]
150 96 SET_SIZE(get_asyncflt)
151 97
152 -#endif /* lint */
153 -
154 -#if defined(lint)
155 -void
156 -set_asyncflt(uint64_t afsr)
157 -{
158 - afsr = afsr;
159 -}
160 -#else /* lint */
161 -
162 98 ENTRY(set_asyncflt)
163 99 stxa %o0, [%g0]ASI_AFSR ! afsr reg
164 100 membar #Sync
165 101 retl
166 102 nop
167 103 SET_SIZE(set_asyncflt)
168 104
169 -#endif /* lint */
170 -
171 -#if defined(lint)
172 -void
173 -get_asyncaddr(uint64_t *afar)
174 -{
175 - afar = afar;
176 -}
177 -#else /* lint */
178 -
179 105 ENTRY(get_asyncaddr)
180 106 ldxa [%g0]ASI_AFAR, %o1 ! afar reg
181 107 retl
182 108 stx %o1, [%o0]
183 109 SET_SIZE(get_asyncaddr)
184 110
185 -#endif /* lint */
186 -
187 -#if defined(lint) || defined(__lint)
188 -
189 -/* ARGSUSED */
190 -hrtime_t
191 -tick2ns(hrtime_t tick, uint_t cpuid)
192 -{ return 0; }
193 -
194 -#else /* lint */
195 -
196 111 ENTRY_NP(tick2ns)
197 112 sethi %hi(cpunodes), %o4
198 113 or %o4, %lo(cpunodes), %o4 ! %o4 = &cpunodes
199 114 ! Register usage:
200 115 !
201 116 ! o0 = timestamp
202 117 ! o2 = byte offset into cpunodes for tick_nsec_scale of this CPU
203 118 ! o4 = &cpunodes
204 119 !
205 120 mulx %o1, CPU_NODE_SIZE, %o2 ! %o2 = byte offset into cpunodes
206 121 add %o2, TICK_NSEC_SCALE, %o2
207 122 ld [%o4 + %o2], %o2 ! %o2 = cpunodes[cpuid].tick_nsec_scale
208 123 NATIVE_TIME_TO_NSEC_SCALE(%o0, %o2, %o3, TICK_NSEC_SHIFT)
209 124 retl
210 125 nop
211 126 SET_SIZE(tick2ns)
212 127
213 -#endif /* lint */
214 -
215 -#if defined(lint)
216 -
217 -/* ARGSUSED */
218 -void
219 -set_cmp_error_steering(void)
220 -{}
221 -
222 -#else /* lint */
223 -
224 128 ENTRY(set_cmp_error_steering)
225 129 membar #Sync
226 130 set ASI_CORE_ID, %o0 ! %o0 = ASI_CORE_ID
227 131 ldxa [%o0]ASI_CMP_PER_CORE, %o0 ! get ASI_CORE_ID
228 132 and %o0, COREID_MASK, %o0
229 133 set ASI_CMP_ERROR_STEERING, %o1 ! %o1 = ERROR_STEERING_REG
230 134 stxa %o0, [%o1]ASI_CMP_SHARED ! this core now hadles
231 135 membar #Sync ! non-core specific errors
232 136 retl
233 137 nop
234 138 SET_SIZE(set_cmp_error_steering)
235 139
236 -#endif /* lint */
237 -
238 -#if defined(lint)
239 -
240 -/* ARGSUSED */
241 -uint64_t
242 -ultra_getver(void)
243 -{
244 - return (0);
245 -}
246 -
247 -#else /* lint */
248 -
249 140 ENTRY(ultra_getver)
250 141 retl
251 142 rdpr %ver, %o0
252 143 SET_SIZE(ultra_getver)
253 144
254 -#endif /* lint */
255 -
256 -#if defined(lint)
257 -
258 -int
259 -fpras_chkfn_type1(void)
260 -{ return 0; }
261 -
262 -#else /* lint */
263 -
264 145 /*
265 146 * Check instructions using just the AX pipelines, designed by
266 147 * C.B. Liaw of PNP.
267 148 *
268 149 * This function must match a struct fpras_chkfn and must be
269 150 * block aligned. A zero return means all was well. These
270 151 * instructions are chosen to be sensitive to bit corruptions
271 152 * on the fpras rewrite, so if a bit corruption still produces
272 153 * a valid instruction we should still get an incorrect result
273 154 * here. This function is never called directly - it is copied
274 155 * into per-cpu and per-operation buffers; it must therefore
275 156 * be absolutely position independent. If an illegal instruction
276 157 * is encountered then the trap handler trampolines to the final
277 158 * three instructions of this function.
278 159 *
279 160 * We want two instructions that are complements of one another,
280 161 * and which can perform a calculation with a known result.
281 162 *
282 163 * SETHI:
283 164 *
284 165 * | 0 0 | rd | 1 0 0 | imm22 |
285 166 * 31 30 29 25 24 22 21 0
286 167 *
287 168 * ADDCCC with two source registers:
288 169 *
289 170 * | 1 0 | rd | 0 1 1 0 0 0 | rs1 | 0 | - | rs2 |
290 171 * 31 30 29 25 24 19 18 14 13 12 5 4 0
291 172 *
292 173 * We can choose rd and imm2 of the SETHI and rd, rs1 and rs2 of
293 174 * the ADDCCC to obtain instructions that are complements in all but
294 175 * bit 30.
295 176 *
296 177 * Registers are numbered as follows:
297 178 *
298 179 * r[31] %i7
299 180 * r[30] %i6
300 181 * r[29] %i5
301 182 * r[28] %i4
302 183 * r[27] %i3
303 184 * r[26] %i2
304 185 * r[25] %i1
305 186 * r[24] %i0
306 187 * r[23] %l7
307 188 * r[22] %l6
308 189 * r[21] %l5
309 190 * r[20] %l4
310 191 * r[19] %l3
311 192 * r[18] %l2
312 193 * r[17] %l1
313 194 * r[16] %l0
314 195 * r[15] %o7
315 196 * r[14] %o6
316 197 * r[13] %o5
317 198 * r[12] %o4
318 199 * r[11] %o3
319 200 * r[10] %o2
320 201 * r[9] %o1
321 202 * r[8] %o0
322 203 * r[7] %g7
323 204 * r[6] %g6
324 205 * r[5] %g5
325 206 * r[4] %g4
326 207 * r[3] %g3
327 208 * r[2] %g2
328 209 * r[1] %g1
329 210 * r[0] %g0
330 211 *
331 212 * For register r[n], register r[31-n] is the complement. We must
332 213 * avoid use of %i6/%i7 and %o6/%o7 as well as %g7. Clearly we need
333 214 * to use a local or input register as one half of the pair, which
334 215 * requires us to obtain our own register window or take steps
335 216 * to preserve any local or input we choose to use. We choose
336 217 * %o1 as rd for the SETHI, so rd of the ADDCCC must be %l6.
337 218 * We'll use %o1 as rs1 and %l6 as rs2 of the ADDCCC, which then
338 219 * requires that imm22 be 0b111 10110 1 11111111 01001 or 0x3dbfe9,
339 220 * or %hi(0xf6ffa400). This determines the value of the constant
340 221 * CBV2 below.
341 222 *
342 223 * The constant CBV1 is chosen such that an initial subcc %g0, CBV1
343 224 * will set the carry bit and every addccc thereafter will continue
344 225 * to generate a carry. Other values are possible for CBV1 - this
345 226 * is just one that works this way.
346 227 *
347 228 * Finally CBV3 is the expected answer when we perform our repeated
348 229 * calculations on CBV1 and CBV2 - it is not otherwise specially
349 230 * derived. If this result is not obtained then a corruption has
350 231 * occured during the FPRAS_REWRITE of one of the two blocks of
351 232 * 16 instructions. A corruption could also result in an illegal
352 233 * instruction or other unexpected trap - we catch illegal
353 234 * instruction traps in the PC range and trampoline to the
354 235 * last instructions of the function to return a failure indication.
355 236 *
356 237 */
357 238
358 239 #define CBV1 0xc11
359 240 #define CBV2 0xf6ffa400
360 241 #define CBV3 0x66f9d800
361 242 #define CBR1 %o1
362 243 #define CBR2 %l6
363 244 #define CBO2 %o2
364 245 #define SETHI_CBV2_CBR1 sethi %hi(CBV2), CBR1
365 246 #define ADDCCC_CBR1_CBR2_CBR2 addccc CBR1, CBR2, CBR2
366 247
367 248 .align 64
368 249 ENTRY_NP(fpras_chkfn_type1)
369 250 mov CBR2, CBO2 ! 1, preserve CBR2 of (callers) window
370 251 mov FPRAS_OK, %o0 ! 2, default return value
371 252 ba,pt %icc, 1f ! 3
372 253 subcc %g0, CBV1, CBR2 ! 4
373 254 ! 5 - 16
374 255 .align 64
375 256 1: SETHI_CBV2_CBR1 ! 1
376 257 ADDCCC_CBR1_CBR2_CBR2 ! 2
377 258 SETHI_CBV2_CBR1 ! 3
378 259 ADDCCC_CBR1_CBR2_CBR2 ! 4
379 260 SETHI_CBV2_CBR1 ! 5
380 261 ADDCCC_CBR1_CBR2_CBR2 ! 6
381 262 SETHI_CBV2_CBR1 ! 7
382 263 ADDCCC_CBR1_CBR2_CBR2 ! 8
383 264 SETHI_CBV2_CBR1 ! 9
384 265 ADDCCC_CBR1_CBR2_CBR2 ! 10
385 266 SETHI_CBV2_CBR1 ! 11
386 267 ADDCCC_CBR1_CBR2_CBR2 ! 12
387 268 SETHI_CBV2_CBR1 ! 13
388 269 ADDCCC_CBR1_CBR2_CBR2 ! 14
389 270 SETHI_CBV2_CBR1 ! 15
390 271 ADDCCC_CBR1_CBR2_CBR2 ! 16
391 272
392 273 ADDCCC_CBR1_CBR2_CBR2 ! 1
393 274 SETHI_CBV2_CBR1 ! 2
394 275 ADDCCC_CBR1_CBR2_CBR2 ! 3
395 276 SETHI_CBV2_CBR1 ! 4
396 277 ADDCCC_CBR1_CBR2_CBR2 ! 5
397 278 SETHI_CBV2_CBR1 ! 6
398 279 ADDCCC_CBR1_CBR2_CBR2 ! 7
399 280 SETHI_CBV2_CBR1 ! 8
400 281 ADDCCC_CBR1_CBR2_CBR2 ! 9
401 282 SETHI_CBV2_CBR1 ! 10
402 283 ADDCCC_CBR1_CBR2_CBR2 ! 11
403 284 SETHI_CBV2_CBR1 ! 12
404 285 ADDCCC_CBR1_CBR2_CBR2 ! 13
405 286 SETHI_CBV2_CBR1 ! 14
406 287 ADDCCC_CBR1_CBR2_CBR2 ! 15
407 288 SETHI_CBV2_CBR1 ! 16
408 289
409 290 addc CBR1, CBR2, CBR2 ! 1
410 291 sethi %hi(CBV3), CBR1 ! 2
411 292 cmp CBR1, CBR2 ! 3
412 293 movnz %icc, FPRAS_BADCALC, %o0! 4, how detected
413 294 retl ! 5
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414 295 mov CBO2, CBR2 ! 6, restore borrowed register
415 296 .skip 4*(13-7+1) ! 7 - 13
416 297 !
417 298 ! illegal instr'n trap comes here
418 299 !
419 300 mov CBO2, CBR2 ! 14, restore borrowed register
420 301 retl ! 15
421 302 mov FPRAS_BADTRAP, %o0 ! 16, how detected
422 303 SET_SIZE(fpras_chkfn_type1)
423 304
424 -#endif /* lint */
425 -
426 305 /*
427 306 * fp_zero() - clear all fp data registers and the fsr
428 307 */
429 308
430 -#if defined(lint) || defined(__lint)
431 -
432 -void
433 -fp_zero(void)
434 -{}
435 -
436 -#else /* lint */
437 -
438 309 ENTRY_NP(fp_zero)
439 310 std %g0, [%sp + ARGPUSH + STACK_BIAS]
440 311 fzero %f0
441 312 fzero %f2
442 313 ldd [%sp + ARGPUSH + STACK_BIAS], %fsr
443 314 faddd %f0, %f2, %f4
444 315 fmuld %f0, %f2, %f6
445 316 faddd %f0, %f2, %f8
446 317 fmuld %f0, %f2, %f10
447 318 faddd %f0, %f2, %f12
448 319 fmuld %f0, %f2, %f14
449 320 faddd %f0, %f2, %f16
450 321 fmuld %f0, %f2, %f18
451 322 faddd %f0, %f2, %f20
452 323 fmuld %f0, %f2, %f22
453 324 faddd %f0, %f2, %f24
454 325 fmuld %f0, %f2, %f26
455 326 faddd %f0, %f2, %f28
456 327 fmuld %f0, %f2, %f30
457 328 faddd %f0, %f2, %f32
458 329 fmuld %f0, %f2, %f34
459 330 faddd %f0, %f2, %f36
460 331 fmuld %f0, %f2, %f38
461 332 faddd %f0, %f2, %f40
462 333 fmuld %f0, %f2, %f42
463 334 faddd %f0, %f2, %f44
464 335 fmuld %f0, %f2, %f46
465 336 faddd %f0, %f2, %f48
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466 337 fmuld %f0, %f2, %f50
467 338 faddd %f0, %f2, %f52
468 339 fmuld %f0, %f2, %f54
469 340 faddd %f0, %f2, %f56
470 341 fmuld %f0, %f2, %f58
471 342 faddd %f0, %f2, %f60
472 343 retl
473 344 fmuld %f0, %f2, %f62
474 345 SET_SIZE(fp_zero)
475 346
476 -#endif /* lint */
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