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--- old/usr/src/uts/sun4u/ml/mach_interrupt.s
+++ new/usr/src/uts/sun4u/ml/mach_interrupt.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
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16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 -#if defined(lint)
27 -#include <sys/types.h>
28 -#include <sys/thread.h>
29 -#else /* lint */
30 26 #include "assym.h"
31 -#endif /* lint */
32 27
33 28 #include <sys/asm_linkage.h>
34 29 #include <sys/machthread.h>
35 30 #include <sys/machcpuvar.h>
36 31 #include <sys/mmu.h>
37 32 #include <sys/intreg.h>
38 33 #include <sys/dmv.h>
39 34
40 35 #ifdef TRAPTRACE
41 36 #include <sys/traptrace.h>
42 37 #endif /* TRAPTRACE */
43 38
44 39
45 -#if defined(lint)
46 -
47 -void
48 -vec_interrupt(void)
49 -{}
50 -
51 -#else /* lint */
52 -
53 40 vec_uiii_irdr_tab:
54 41 .byte UIII_IRDR_0, UIII_IRDR_1, UIII_IRDR_2, UIII_IRDR_3
55 42 .byte UIII_IRDR_4, UIII_IRDR_5, UIII_IRDR_6, UIII_IRDR_7
56 43
57 44 /*
58 45 * (TT 0x60, TL>0) Interrupt Vector Handler
59 46 * Globals are the Interrupt Globals.
60 47 */
61 48 ENTRY_NP(vec_interrupt)
62 49 !
63 50 ! Load the interrupt receive data register 0.
64 51 ! It could be a fast trap handler address (pc > KERNELBASE) at TL>0
65 52 ! or an interrupt number.
66 53 !
67 54 mov IRDR_0, %g2
68 55 ldxa [%g2]ASI_INTR_RECEIVE, %g5 ! %g5 = PC or Interrupt Number
69 56
70 57 ! If the high bit of IRDR_0 is set, then this is a
71 58 ! data bearing mondo vector.
72 59 brlz,pt %g5, dmv_vector
73 60 .empty
74 61
75 62
76 63 vec_interrupt_resume:
77 64 set KERNELBASE, %g4
78 65 cmp %g5, %g4
79 66 bl,a,pt %xcc, 0f ! an interrupt number found
80 67 nop
81 68 !
82 69 ! intercept OBP xcalls and set PCONTEXT=0
83 70 !
84 71 set _end, %g4 ! _end is highest kernel address
85 72 cmp %g5, %g4
86 73 bl,a,pt %xcc, 7f
87 74 nop
88 75
89 76 #ifndef _OPL
90 77 mov MMU_PCONTEXT, %g1
91 78 ldxa [%g1]ASI_DMMU, %g1
92 79 srlx %g1, CTXREG_NEXT_SHIFT, %g3
93 80 brz,pt %g3, 7f ! nucleus pgsz is 0, no problem
94 81 sllx %g3, CTXREG_NEXT_SHIFT, %g3
95 82 set CTXREG_CTX_MASK, %g4 ! check Pcontext
96 83 btst %g4, %g1
97 84 bz,a,pt %xcc, 6f
98 85 clr %g3 ! kernel: PCONTEXT=0
99 86 xor %g3, %g1, %g3 ! user: clr N_pgsz0/1 bits
100 87 6:
101 88 set DEMAP_ALL_TYPE, %g1
102 89 stxa %g0, [%g1]ASI_DTLB_DEMAP
103 90 stxa %g0, [%g1]ASI_ITLB_DEMAP
104 91 mov MMU_PCONTEXT, %g1
105 92 stxa %g3, [%g1]ASI_DMMU
106 93 membar #Sync
107 94 sethi %hi(FLUSH_ADDR), %g1
108 95 flush %g1 ! flush required by immu
109 96 #endif /* _OPL */
110 97
111 98 7:
112 99 !
113 100 ! Cross-trap request case
114 101 !
115 102 ! Load interrupt receive data registers 1 and 2 to fetch
116 103 ! the arguments for the fast trap handler.
117 104 !
118 105 ! Register usage:
119 106 ! g5: TL>0 handler
120 107 ! g1: arg1
121 108 ! g2: arg2
122 109 ! g3: arg3
123 110 ! g4: arg4
124 111 !
125 112 mov IRDR_1, %g2
126 113 ldxa [%g2]ASI_INTR_RECEIVE, %g1
127 114 mov IRDR_2, %g2
128 115 ldxa [%g2]ASI_INTR_RECEIVE, %g2
129 116 #ifdef TRAPTRACE
130 117 TRACE_PTR(%g4, %g6)
131 118 GET_TRACE_TICK(%g6, %g3)
132 119 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
133 120 rdpr %tl, %g6
134 121 stha %g6, [%g4 + TRAP_ENT_TL]%asi
135 122 rdpr %tt, %g6
136 123 stha %g6, [%g4 + TRAP_ENT_TT]%asi
137 124 rdpr %tpc, %g6
138 125 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
139 126 rdpr %tstate, %g6
140 127 stxa %g6, [%g4 + TRAP_ENT_TSTATE]%asi
141 128 stna %sp, [%g4 + TRAP_ENT_SP]%asi
142 129 stna %g5, [%g4 + TRAP_ENT_TR]%asi ! pc of the TL>0 handler
143 130 stxa %g1, [%g4 + TRAP_ENT_F1]%asi
144 131 stxa %g2, [%g4 + TRAP_ENT_F3]%asi
145 132 stxa %g0, [%g4 + TRAP_ENT_F2]%asi
146 133 stxa %g0, [%g4 + TRAP_ENT_F4]%asi
147 134 TRACE_NEXT(%g4, %g6, %g3)
148 135 #endif /* TRAPTRACE */
149 136 stxa %g0, [%g0]ASI_INTR_RECEIVE_STATUS ! clear the BUSY bit
150 137 membar #Sync
151 138 #ifdef SF_ERRATA_51
152 139 ba,pt %icc, 1f
153 140 nop
154 141 .align 32
155 142 1: jmp %g5 ! call the fast trap handler
156 143 nop
157 144 #else
158 145 jmp %g5
159 146 nop
160 147 #endif /* SF_ERRATA_51 */
161 148 /* Never Reached */
162 149
163 150 0:
164 151 ! We have an interrupt number.
165 152 !
166 153 ! Register usage:
167 154 ! %g5 - inum
168 155 ! %g1 - temp
169 156 !
170 157 ! We don't bother to verify that the received inum is valid (it should
171 158 ! be < MAXIVNUM) since setvecint_tl1 will do that for us.
172 159 !
173 160 ! clear BUSY bit
174 161 !
175 162 stxa %g0, [%g0]ASI_INTR_RECEIVE_STATUS
176 163 membar #Sync
177 164
178 165 ! setvecint_tl1 will do all the work, and finish with a retry
179 166 !
180 167 ba,pt %xcc, setvecint_tl1
181 168 mov %g5, %g1 ! setvecint_tl1 expects inum in %g1
182 169
183 170 /* Never Reached */
184 171 SET_SIZE(vec_interrupt)
185 172
186 173
187 174 !
188 175 ! See usr/src/uts/sun4u/sys/dmv.h for the Databearing Mondo Vector
189 176 ! interrupt format
190 177 !
191 178 ! Inputs:
192 179 ! g1: value of ASI_INTR_RECEIVE_STATUS
193 180 ! g5: word 0 of the interrupt data
194 181 ! Register use:
195 182 ! g2: dmv inum
196 183 ! g3: scratch
197 184 ! g4: pointer to dmv_dispatch_table
198 185 ! g6: handler pointer from dispatch table
199 186
200 187
201 188 DGDEF(dmv_spurious_cnt)
202 189 .word 0
203 190
204 191 ENTRY_NP(dmv_vector)
205 192 srlx %g5, DMV_INUM_SHIFT, %g2
206 193 set DMV_INUM_MASK, %g3
207 194 and %g2, %g3, %g2 ! %g2 = inum
208 195
209 196 set dmv_totalints, %g3
210 197 ld [%g3], %g3
211 198 cmp %g2, %g3
212 199 bge,pn %xcc, 2f ! inum >= dmv_totalints
213 200 nop
214 201
215 202 set dmv_dispatch_table, %g3
216 203 ldn [%g3], %g4
217 204 brz,pn %g4, 2f
218 205 sll %g2, DMV_DISP_SHIFT, %g3 ! %g3 = inum*sizeof(struct dmv_disp)
219 206
220 207 add %g4, %g3, %g4 ! %g4 = &dmv_dispatch_table[inum]
221 208 #if (DMV_FUNC != 0) || (DMV_ARG != 8)
222 209 #error "DMV_FUNC or DMV_SIZE has changed"
223 210 #endif
224 211 ldda [%g4]ASI_NQUAD_LD, %g2 ! %g2=handler %g3=argument
225 212 mov %g3, %g1
226 213 brz,pn %g2, 2f
227 214 nop
228 215
229 216 ! we have a handler, so call it
230 217 ! On entry to the handler, the %g registers are set as follows:
231 218 !
232 219 ! %g1 The argument (arg) passed to dmv_add_intr().
233 220 ! %g2 Word 0 of the incoming mondo vector.
234 221 !
235 222 jmp %g2
236 223 mov %g5, %g2
237 224
238 225 ! No handler was listed in the table, so just record it
239 226 ! as an error condition and continue. There is a race
240 227 ! window here updating the counter, but that's ok since
241 228 ! just knowing that spurious interrupts happened is enough,
242 229 ! we probably won't need to know exactly how many.
243 230 2:
244 231 set dmv_spurious_cnt, %g1
245 232 ld [%g1], %g2
246 233 inc %g2
247 234 ba,pt %xcc,3f
248 235 st %g2, [%g1]
249 236
250 237 ! When the handler's processing (which should be as quick as
251 238 ! possible) is complete, the handler must exit by jumping to
252 239 ! the label dmv_finish_intr. The contents of %g1 at this time
253 240 ! determine whether a software interrupt will be issued, as
254 241 ! follows:
255 242 !
256 243 ! If %g1 is less than zero, no interrupt will be queued.
257 244 ! Otherwise, %g1 will be used as the interrupt number
258 245 ! to simulate; this means that the behavior of the
259 246 ! interrupt system will be exactly that which would have
260 247 ! occurred if the first word of the incoming interrupt
261 248 ! vector had contained the contents of %g1.
262 249
263 250 ENTRY_NP(dmv_finish_intr)
264 251 brlz,pn %g1,3f
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265 252 nop
266 253 ! generate an interrupt based on the contents of %g1
267 254 ba,pt %xcc,vec_interrupt_resume
268 255 mov %g1, %g5
269 256 ! We are done
270 257 3:
271 258 stxa %g0, [%g0]ASI_INTR_RECEIVE_STATUS ! clear the busy bit
272 259 retry
273 260 SET_SIZE(dmv_vector)
274 261
275 -#endif /* lint */
276 -
277 -#if defined(lint)
278 -
279 -void
280 -vec_intr_spurious(void)
281 -{}
282 -
283 -#else /* lint */
284 -
285 262 DGDEF(vec_spurious_cnt)
286 263 .word 0
287 264
288 265 ENTRY_NP(vec_intr_spurious)
289 266 sethi %hi(vec_spurious_cnt), %g2
290 267 ld [%g2 + %lo(vec_spurious_cnt)], %g2
291 268 #ifdef TRAPTRACE
292 269 TRACE_PTR(%g4, %g6)
293 270 GET_TRACE_TICK(%g6, %g3)
294 271 stxa %g6, [%g4 + TRAP_ENT_TICK]%asi
295 272 rdpr %tl, %g6
296 273 stha %g6, [%g4 + TRAP_ENT_TL]%asi
297 274 rdpr %tt, %g6
298 275 or %g6, TT_SPURIOUS_INT, %g6
299 276 stha %g6, [%g4 + TRAP_ENT_TT]%asi
300 277 rdpr %tpc, %g6
301 278 stna %g6, [%g4 + TRAP_ENT_TPC]%asi
302 279 rdpr %tstate, %g6
303 280 stxa %g6, [%g4 + TRAP_ENT_TSTATE]%asi
304 281 stna %sp, [%g4 + TRAP_ENT_SP]%asi
305 282 stna %g1, [%g4 + TRAP_ENT_TR]%asi ! irsr
306 283 stna %g2, [%g4 + TRAP_ENT_F1]%asi
307 284 ldxa [%g0]ASI_INTR_RECEIVE_STATUS, %g5
308 285 stxa %g5, [%g4 + TRAP_ENT_F2]%asi
309 286 stxa %g0, [%g4 + TRAP_ENT_F4]%asi
310 287 TRACE_NEXT(%g4, %g6, %g3)
311 288 #endif /* TRAPTRACE */
312 289 cmp %g2, 16
313 290 bl,a,pt %xcc, 1f
314 291 inc %g2
315 292 !
316 293 ! prepare for sys_trap()
317 294 ! %g1 - sys_tl1_panic
318 295 ! %g2 - panic message
319 296 ! %g4 - current pil
320 297 !
321 298 #ifdef CLEAR_INTR_BUSYBIT_ON_SPURIOUS
322 299 /*
323 300 * Certain processors (OPL) need to explicitly
324 301 * clear the intr busy bit even though it is
325 302 * not visibly set (spurious intrs)
326 303 */
327 304 stxa %g0, [%g0]ASI_INTR_RECEIVE_STATUS ! clear the BUSY bit
328 305 membar #Sync
329 306 #endif /* CLEAR_INTR_BUSYBIT_ON_SPURIOUS */
330 307 sub %g0, 1, %g4
331 308 set _not_ready, %g2
332 309 sethi %hi(sys_tl1_panic), %g1
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333 310 ba,pt %xcc, sys_trap
334 311 or %g1, %lo(sys_tl1_panic), %g1
335 312 !
336 313 1: sethi %hi(vec_spurious_cnt), %g1
337 314 st %g2, [%g1 + %lo(vec_spurious_cnt)]
338 315 retry
339 316 SET_SIZE(vec_intr_spurious)
340 317
341 318 _not_ready: .asciz "Interrupt Vector Receive Register not READY"
342 319
343 -#endif /* lint */
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