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de-linting of .s files


   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25 
  26 #if defined(lint)
  27 #include <sys/types.h>
  28 #include <sys/thread.h>
  29 #else   /* lint */
  30 #include "assym.h"
  31 #endif  /* lint */
  32 
  33 #include <sys/asm_linkage.h>
  34 #include <sys/machthread.h>
  35 #include <sys/machcpuvar.h>
  36 #include <sys/mmu.h>
  37 #include <sys/intreg.h>
  38 #include <sys/dmv.h>
  39 
  40 #ifdef TRAPTRACE
  41 #include <sys/traptrace.h>
  42 #endif /* TRAPTRACE */
  43 
  44 
  45 #if defined(lint)
  46 
  47 void
  48 vec_interrupt(void)
  49 {}
  50 
  51 #else   /* lint */
  52 
  53 vec_uiii_irdr_tab:
  54         .byte   UIII_IRDR_0, UIII_IRDR_1, UIII_IRDR_2, UIII_IRDR_3
  55         .byte   UIII_IRDR_4, UIII_IRDR_5, UIII_IRDR_6, UIII_IRDR_7
  56 
  57 /*
  58  * (TT 0x60, TL>0) Interrupt Vector Handler
  59  *      Globals are the Interrupt Globals.
  60  */
  61         ENTRY_NP(vec_interrupt)
  62         !
  63         ! Load the interrupt receive data register 0.
  64         ! It could be a fast trap handler address (pc > KERNELBASE) at TL>0
  65         ! or an interrupt number.
  66         !
  67         mov     IRDR_0, %g2
  68         ldxa    [%g2]ASI_INTR_RECEIVE, %g5      ! %g5 = PC or Interrupt Number
  69 
  70         ! If the high bit of IRDR_0 is set, then this is a
  71         ! data bearing mondo vector.
  72         brlz,pt %g5, dmv_vector


 255         !
 256         !               If %g1 is less than zero, no interrupt will be queued.
 257         !               Otherwise, %g1 will be used as the interrupt number
 258         !               to simulate; this means that the behavior of the
 259         !               interrupt system will be exactly that which would have
 260         !               occurred if the first word of the incoming interrupt
 261         !               vector had contained the contents of %g1.
 262 
 263         ENTRY_NP(dmv_finish_intr)
 264         brlz,pn %g1,3f
 265         nop
 266         !       generate an interrupt based on the contents of %g1
 267         ba,pt   %xcc,vec_interrupt_resume
 268         mov     %g1, %g5
 269         !       We are done
 270 3:      
 271         stxa    %g0, [%g0]ASI_INTR_RECEIVE_STATUS ! clear the busy bit
 272         retry
 273         SET_SIZE(dmv_vector)
 274 
 275 #endif  /* lint */
 276 
 277 #if defined(lint)
 278 
 279 void
 280 vec_intr_spurious(void)
 281 {}
 282 
 283 #else   /* lint */
 284 
 285         DGDEF(vec_spurious_cnt)
 286         .word   0
 287 
 288         ENTRY_NP(vec_intr_spurious)
 289         sethi   %hi(vec_spurious_cnt), %g2
 290         ld      [%g2 + %lo(vec_spurious_cnt)], %g2
 291 #ifdef TRAPTRACE
 292         TRACE_PTR(%g4, %g6)
 293         GET_TRACE_TICK(%g6, %g3)
 294         stxa    %g6, [%g4 + TRAP_ENT_TICK]%asi
 295         rdpr    %tl, %g6
 296         stha    %g6, [%g4 + TRAP_ENT_TL]%asi
 297         rdpr    %tt, %g6
 298         or      %g6, TT_SPURIOUS_INT, %g6
 299         stha    %g6, [%g4 + TRAP_ENT_TT]%asi
 300         rdpr    %tpc, %g6
 301         stna    %g6, [%g4 + TRAP_ENT_TPC]%asi
 302         rdpr    %tstate, %g6
 303         stxa    %g6, [%g4 + TRAP_ENT_TSTATE]%asi
 304         stna    %sp, [%g4 + TRAP_ENT_SP]%asi


 323          * Certain processors (OPL) need to explicitly
 324          * clear the intr busy bit even though it is
 325          * not visibly set (spurious intrs)
 326          */
 327         stxa    %g0, [%g0]ASI_INTR_RECEIVE_STATUS       ! clear the BUSY bit
 328         membar  #Sync
 329 #endif /* CLEAR_INTR_BUSYBIT_ON_SPURIOUS */
 330         sub     %g0, 1, %g4
 331         set     _not_ready, %g2
 332         sethi   %hi(sys_tl1_panic), %g1
 333         ba,pt   %xcc, sys_trap
 334         or      %g1, %lo(sys_tl1_panic), %g1
 335         !
 336 1:      sethi   %hi(vec_spurious_cnt), %g1
 337         st      %g2, [%g1 + %lo(vec_spurious_cnt)]
 338         retry
 339         SET_SIZE(vec_intr_spurious)
 340 
 341 _not_ready:     .asciz  "Interrupt Vector Receive Register not READY"
 342 
 343 #endif  /* lint */


   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25 




  26 #include "assym.h"

  27 
  28 #include <sys/asm_linkage.h>
  29 #include <sys/machthread.h>
  30 #include <sys/machcpuvar.h>
  31 #include <sys/mmu.h>
  32 #include <sys/intreg.h>
  33 #include <sys/dmv.h>
  34 
  35 #ifdef TRAPTRACE
  36 #include <sys/traptrace.h>
  37 #endif /* TRAPTRACE */
  38 
  39 








  40 vec_uiii_irdr_tab:
  41         .byte   UIII_IRDR_0, UIII_IRDR_1, UIII_IRDR_2, UIII_IRDR_3
  42         .byte   UIII_IRDR_4, UIII_IRDR_5, UIII_IRDR_6, UIII_IRDR_7
  43 
  44 /*
  45  * (TT 0x60, TL>0) Interrupt Vector Handler
  46  *      Globals are the Interrupt Globals.
  47  */
  48         ENTRY_NP(vec_interrupt)
  49         !
  50         ! Load the interrupt receive data register 0.
  51         ! It could be a fast trap handler address (pc > KERNELBASE) at TL>0
  52         ! or an interrupt number.
  53         !
  54         mov     IRDR_0, %g2
  55         ldxa    [%g2]ASI_INTR_RECEIVE, %g5      ! %g5 = PC or Interrupt Number
  56 
  57         ! If the high bit of IRDR_0 is set, then this is a
  58         ! data bearing mondo vector.
  59         brlz,pt %g5, dmv_vector


 242         !
 243         !               If %g1 is less than zero, no interrupt will be queued.
 244         !               Otherwise, %g1 will be used as the interrupt number
 245         !               to simulate; this means that the behavior of the
 246         !               interrupt system will be exactly that which would have
 247         !               occurred if the first word of the incoming interrupt
 248         !               vector had contained the contents of %g1.
 249 
 250         ENTRY_NP(dmv_finish_intr)
 251         brlz,pn %g1,3f
 252         nop
 253         !       generate an interrupt based on the contents of %g1
 254         ba,pt   %xcc,vec_interrupt_resume
 255         mov     %g1, %g5
 256         !       We are done
 257 3:      
 258         stxa    %g0, [%g0]ASI_INTR_RECEIVE_STATUS ! clear the busy bit
 259         retry
 260         SET_SIZE(dmv_vector)
 261 










 262         DGDEF(vec_spurious_cnt)
 263         .word   0
 264 
 265         ENTRY_NP(vec_intr_spurious)
 266         sethi   %hi(vec_spurious_cnt), %g2
 267         ld      [%g2 + %lo(vec_spurious_cnt)], %g2
 268 #ifdef TRAPTRACE
 269         TRACE_PTR(%g4, %g6)
 270         GET_TRACE_TICK(%g6, %g3)
 271         stxa    %g6, [%g4 + TRAP_ENT_TICK]%asi
 272         rdpr    %tl, %g6
 273         stha    %g6, [%g4 + TRAP_ENT_TL]%asi
 274         rdpr    %tt, %g6
 275         or      %g6, TT_SPURIOUS_INT, %g6
 276         stha    %g6, [%g4 + TRAP_ENT_TT]%asi
 277         rdpr    %tpc, %g6
 278         stna    %g6, [%g4 + TRAP_ENT_TPC]%asi
 279         rdpr    %tstate, %g6
 280         stxa    %g6, [%g4 + TRAP_ENT_TSTATE]%asi
 281         stna    %sp, [%g4 + TRAP_ENT_SP]%asi


 300          * Certain processors (OPL) need to explicitly
 301          * clear the intr busy bit even though it is
 302          * not visibly set (spurious intrs)
 303          */
 304         stxa    %g0, [%g0]ASI_INTR_RECEIVE_STATUS       ! clear the BUSY bit
 305         membar  #Sync
 306 #endif /* CLEAR_INTR_BUSYBIT_ON_SPURIOUS */
 307         sub     %g0, 1, %g4
 308         set     _not_ready, %g2
 309         sethi   %hi(sys_tl1_panic), %g1
 310         ba,pt   %xcc, sys_trap
 311         or      %g1, %lo(sys_tl1_panic), %g1
 312         !
 313 1:      sethi   %hi(vec_spurious_cnt), %g1
 314         st      %g2, [%g1 + %lo(vec_spurious_cnt)]
 315         retry
 316         SET_SIZE(vec_intr_spurious)
 317 
 318 _not_ready:     .asciz  "Interrupt Vector Receive Register not READY"
 319