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--- old/usr/src/uts/sun4u/cpu/us3_jalapeno_asm.s
+++ new/usr/src/uts/sun4u/cpu/us3_jalapeno_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License, Version 1.0 only
6 6 * (the "License"). You may not use this file except in compliance
7 7 * with the License.
8 8 *
9 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 10 * or http://www.opensolaris.org/os/licensing.
11 11 * See the License for the specific language governing permissions
12 12 * and limitations under the License.
13 13 *
14 14 * When distributing Covered Code, include this CDDL HEADER in each
15 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 16 * If applicable, add the following below this CDDL HEADER, with the
17 17 * fields enclosed by brackets "[]" replaced with your own identifying
18 18 * information: Portions Copyright [yyyy] [name of copyright owner]
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19 19 *
20 20 * CDDL HEADER END
21 21 */
22 22 /*
23 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 *
26 26 * Assembly code support for the jalapeno module
27 27 */
28 28
29 -#pragma ident "%Z%%M% %I% %E% SMI"
30 -
31 -#if !defined(lint)
32 29 #include "assym.h"
33 -#endif /* lint */
34 30
35 31 #include <sys/asm_linkage.h>
36 32 #include <sys/mmu.h>
37 33 #include <vm/hat_sfmmu.h>
38 34 #include <sys/machparam.h>
39 35 #include <sys/machcpuvar.h>
40 36 #include <sys/machthread.h>
41 37 #include <sys/machtrap.h>
42 38 #include <sys/privregs.h>
43 39 #include <sys/asm_linkage.h>
44 40 #include <sys/trap.h>
45 41 #include <sys/cheetahregs.h>
46 42 #include <sys/us3_module.h>
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47 43 #include <sys/xc_impl.h>
48 44 #include <sys/intreg.h>
49 45 #include <sys/async.h>
50 46 #include <sys/clock.h>
51 47 #include <sys/cheetahasm.h>
52 48
53 49 #ifdef TRAPTRACE
54 50 #include <sys/traptrace.h>
55 51 #endif /* TRAPTRACE */
56 52
57 -#if !defined(lint)
58 -
59 53 /* BEGIN CSTYLED */
60 54
61 55 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
62 56
63 57 #define CHK_JP_ERRATA85_ENABLED(scr, label) \
64 58 ASM_LD(scr, jp_errata_85_active); \
65 59 cmp scr, 1; \
66 60 bne %icc, label; \
67 61 nop
68 62
69 63 #define SET_64BIT_PA(dest, scr, hi32, lo32) \
70 64 set hi32, scr; \
71 65 sllx scr, 32, scr; \
72 66 sethi %hi(lo32), dest; \
73 67 or dest, %lo(lo32), dest; \
74 68 or scr, dest, dest
75 69
76 70 /*
77 71 * Macro to trigger Jalapeno/Tomatillo speed change
78 72 * j_chng_pa - scratch register
79 73 * scr - scratch register
80 74 */
81 75 #define JP_ESTAR_TRIGGER(j_chng_pa, scr) \
82 76 SET_64BIT_PA(j_chng_pa, scr, TOM_HIGH_PA, M_T_J_CHNG_INIT_PA); \
83 77 ldxa [j_chng_pa]ASI_IO, scr; \
84 78 5: \
85 79 and scr, TOM_TRIGGER_MASK, scr; \
86 80 cmp scr, TOM_TRIGGER; \
87 81 be,pt %icc, 5b; /* wait while 10 */ \
88 82 ldxa [j_chng_pa]ASI_IO, scr; \
89 83 andn scr, TOM_TRIGGER_MASK, scr; \
90 84 stxa scr, [j_chng_pa]ASI_IO; /* clear j_chng[1:0] */ \
91 85 or scr, TOM_TRIGGER, scr; \
92 86 stxa scr, [j_chng_pa]ASI_IO; /* trigger j_chng */ \
93 87 ldxa [j_chng_pa]ASI_IO, scr; \
94 88 6: \
95 89 and scr, TOM_TRIGGER_MASK, scr; \
96 90 cmp scr, TOM_TRIGGER; \
97 91 be,pt %icc, 6b; /* wait while 10 */ \
98 92 ldxa [j_chng_pa]ASI_IO, scr; \
99 93 andn scr, TOM_TRIGGER_MASK, scr; \
100 94 stxa scr, [j_chng_pa]ASI_IO; /* deassert j_chng */
101 95
102 96 /*
103 97 * Macro to set Jalapeno CPU speed
104 98 * speed - new speed constant
105 99 * scr1 - scratch register
106 100 * scr2 - scratch register
107 101 */
108 102 #define SET_JP_SPEED(speed, scr1, scr2) \
109 103 ldxa [%g0]ASI_JBUS_CONFIG, scr1; \
110 104 set JBUS_CONFIG_ECLK_MASK, scr2; \
111 105 andn scr1, scr2, scr1; \
112 106 set speed, scr2; \
113 107 or scr1, scr2, scr1; \
114 108 stxa scr1, [%g0]ASI_JBUS_CONFIG;
115 109
116 110 /*
117 111 * macro to set Master Tomatillo speed
118 112 * speed - tomatillo speed constant
119 113 * tpa - tomatillo estar control register PA
120 114 * scr - scratch register
121 115 */
122 116 #define SET_TOM_SPEED(speed, tpa, scr) \
123 117 ldxa [tpa]ASI_IO, scr; \
124 118 andn scr, TOM_ESTAR_ELCK_MASK, scr; \
125 119 or scr, speed, scr; \
126 120 stxa scr, [tpa]ASI_IO;
127 121
128 122 /*
129 123 * macro to check and set Slave Tomatillo speed
130 124 * speed - tomatillo speed constant
131 125 * scr1 - scratch register
132 126 * scr2 - scratch register
133 127 */
134 128
135 129 #define SET_SLAVE_T_SPEED(speed, scr1, scr2) \
136 130 ldxa [%g0]ASI_JBUS_CONFIG, scr2; \
137 131 srlx scr2, JBUS_SLAVE_T_PORT_BIT, scr2; \
138 132 btst 1, scr2; \
139 133 bz,pt %icc, 4f; \
140 134 nop; \
141 135 SET_64BIT_PA(scr1, scr2, TOM_HIGH_PA, S_T_ESTAR_CTRL_PA); \
142 136 SET_TOM_SPEED(speed, scr1, scr2); \
143 137 4:
144 138
145 139
146 140 /*
147 141 * macro to adjust ASI_MCU_CTL_REG1[26:25] fsm bits according to
148 142 * new cpu speed: fsm[1:0]=11b for full speed, fsm[1:0]=0 for estar speed
149 143 * value - fsm bit value constant
150 144 * scr1 - scratch register
151 145 * scr2 - scratch register
152 146 */
153 147 #define JP_ADJUST_FSM(value, scr1, scr2) \
154 148 ldxa [%g0]ASI_MCU_CTRL, scr1; \
155 149 set JP_MCU_FSM_MASK, scr2; \
156 150 andn scr1, scr2, scr1; \
157 151 set value, scr2; \
158 152 or scr1, scr2, scr1; \
159 153 stxa scr1, [%g0]ASI_MCU_CTRL; \
160 154 membar #Sync;
161 155
162 156 /*
163 157 * JP_FORCE_FULL_SPEED and its fellow macros are for Jalapeno
164 158 * workstation to work around Errata 85. The front portion of
165 159 * it packs JP speed(14..13) and Tomatillo speed(5..0) into one
166 160 * register.
167 161 *
168 162 * Current code assumes that these two fields are non-overlapping.
169 163 * If that assumption changes, then this code won't work. If so, we
170 164 * force a compile time error by not defining the JP_FORCE_FULL_SPEED
171 165 * and JP_RESTORE_SPEED macros below.
172 166 */
173 167
174 168 #if !(JBUS_CONFIG_ECLK_MASK & TOM_SPEED_MASK)
175 169
176 170 /*
177 171 * Macro to force Jalapeno/Tomatillo to full speed
178 172 * old_lvl - register used to save original cpu, tomatillo speed
179 173 * scr2 - scratch register
180 174 * scr3 - scratch register
181 175 * scr4 - scratch register
182 176 */
183 177 #define JP_FORCE_FULL_SPEED(old_lvl, scr2, scr3, scr4) \
184 178 ldxa [%g0]ASI_JBUS_CONFIG, old_lvl; \
185 179 set JBUS_CONFIG_ECLK_MASK, scr4; \
186 180 and old_lvl, scr4, old_lvl; \
187 181 SET_64BIT_PA(scr2, scr3, TOM_HIGH_PA, M_T_ESTAR_CTRL_PA); \
188 182 ldxa [scr2]ASI_IO, scr3; \
189 183 set TOM_ESTAR_ELCK_MASK, scr4; \
190 184 and scr3, scr4, scr3; \
191 185 or old_lvl, scr3, old_lvl; \
192 186 /* original jp and tomatillo speed saved in old_lvl */ \
193 187 \
194 188 /* either intended or currently at full speed */ \
195 189 set JBUS_CONFIG_ECLK_MASK, scr4; \
196 190 andcc old_lvl, scr4, %g0; \
197 191 bz,pt %icc, 8f; \
198 192 nop; \
199 193 /* go through 1/2 speed. */ \
200 194 SET_JP_SPEED(JBUS_CONFIG_ECLK_2, scr3, scr4); \
201 195 SET_TOM_SPEED(TOM_HALF_SPEED, scr2, scr3); \
202 196 SET_SLAVE_T_SPEED(TOM_HALF_SPEED, scr3, scr4); \
203 197 JP_ADJUST_FSM(0, scr3, scr4); \
204 198 set jp_estar_tl0_data, scr3; \
205 199 ldx [scr3], %g0; \
206 200 membar #Sync; /* or busy wait 1us */ \
207 201 JP_ESTAR_TRIGGER(scr3, scr4); \
208 202 8: \
209 203 /* bring to 1:1 speed */ \
210 204 SET_JP_SPEED(JBUS_CONFIG_ECLK_1, scr3, scr4); \
211 205 SET_TOM_SPEED(TOM_FULL_SPEED, scr2, scr3); \
212 206 SET_SLAVE_T_SPEED(TOM_FULL_SPEED, scr3, scr4); \
213 207 JP_ADJUST_FSM(JP_MCU_FSM_MASK, scr3, scr4); \
214 208 JP_ESTAR_TRIGGER(scr3, scr4)
215 209
216 210
217 211 /*
218 212 * Macro to restore Jalapeno/Tomatillo to original speed
219 213 * old_lvl - register contains saved original cpu, tomatillo speed
220 214 * scr2 - scratch register
221 215 * scr3 - scratch register
222 216 * scr4 - scratch register
223 217 *
224 218 * If trap had occured in the middle of ppm cpu speed transtion, then
225 219 * old_lvl[31:10] contains the intended new speed written into jbus_config.
226 220 * if old_lvl[9:0] is inconsistent with old_lvl[31:10], then the trap surely
227 221 * interrupted the ppm cpu speed transition, otherwise nothing for sure.
228 222 * We'll restore the intended/then-current speed, that should cause no
229 223 * trouble to subsequent ppm cpu speed change code.
230 224 */
231 225 #define JP_RESTORE_SPEED(old_lvl, scr2, scr3, scr4) \
232 226 srlx old_lvl, JBUS_CONFIG_ECLK_SHIFT, scr2; \
233 227 and scr2, 3, scr2; \
234 228 add scr2, 1, scr2; \
235 229 cmp scr2, 3; \
236 230 bne,pt %icc, 7f; \
237 231 nop; \
238 232 set TOM_SLOW_SPEED, scr2; \
239 233 /* scr2 contains tom speed according to intended jp speed */ \
240 234 7: \
241 235 andn old_lvl, TOM_ESTAR_ELCK_MASK, old_lvl; \
242 236 or scr2, old_lvl, old_lvl; \
243 237 /* updated old_lvl to contain intended jp and tom speed */ \
244 238 andcc old_lvl, TOM_FULL_SPEED, %g0; \
245 239 bnz,pt %icc, 9f; /* intended full, already at full */ \
246 240 nop; \
247 241 \
248 242 /* go to half speed */ \
249 243 SET_JP_SPEED(JBUS_CONFIG_ECLK_2, scr3, scr4); \
250 244 SET_64BIT_PA(scr2, scr3, TOM_HIGH_PA, M_T_ESTAR_CTRL_PA); \
251 245 SET_TOM_SPEED(TOM_HALF_SPEED, scr2, scr3); \
252 246 SET_SLAVE_T_SPEED(TOM_HALF_SPEED, scr3, scr4); \
253 247 JP_ADJUST_FSM(0, scr3, scr4); \
254 248 set jp_estar_tl0_data, scr3; \
255 249 ldx [scr3], %g0; \
256 250 membar #Sync; \
257 251 JP_ESTAR_TRIGGER(scr3, scr4); \
258 252 andcc old_lvl, TOM_SLOW_SPEED, %g0; \
259 253 bz,pt %icc, 9f; /* intended 1:2, already at 1:2 */ \
260 254 nop; \
261 255 \
262 256 /* go to 1:32 speed */ \
263 257 SET_JP_SPEED(JBUS_CONFIG_ECLK_32, scr3, scr4); \
264 258 SET_TOM_SPEED(TOM_SLOW_SPEED, scr2, scr3); \
265 259 SET_SLAVE_T_SPEED(TOM_SLOW_SPEED, scr3, scr4); \
266 260 JP_ESTAR_TRIGGER(scr3, scr4); \
267 261 9:
268 262
269 263 #endif /* !(JBUS_CONFIG_ECLK_MASK & TOM_SPEED_MASK) */
270 264 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
271 265
272 266 /*
273 267 * Jalapeno version to reflush an Ecache line by index.
274 268 * Will flush all 4 ways (with only one scratch register).
275 269 * Note that the code will be faster if we use 2 scratch registers.
276 270 */
277 271 #define ECACHE_REFLUSH_LINE(ec_set_size, index, scr1) \
278 272 JP_EC_DIAG_ACCESS_MEMBAR; \
279 273 ldxa [index]ASI_EC_DIAG, %g0; \
280 274 JP_EC_DIAG_ACCESS_MEMBAR; \
281 275 mov 1, scr1; \
282 276 sllx scr1, JP_ECFLUSH_EC_WAY_SHIFT, scr1; \
283 277 add scr1, index, scr1; \
284 278 JP_EC_DIAG_ACCESS_MEMBAR; \
285 279 ldxa [scr1]ASI_EC_DIAG, %g0; \
286 280 JP_EC_DIAG_ACCESS_MEMBAR; \
287 281 mov 2, scr1; \
288 282 sllx scr1, JP_ECFLUSH_EC_WAY_SHIFT, scr1; \
289 283 add scr1, index, scr1; \
290 284 JP_EC_DIAG_ACCESS_MEMBAR; \
291 285 ldxa [scr1]ASI_EC_DIAG, %g0; \
292 286 JP_EC_DIAG_ACCESS_MEMBAR; \
293 287 mov 3, scr1; \
294 288 sllx scr1, JP_ECFLUSH_EC_WAY_SHIFT, scr1; \
295 289 add scr1, index, scr1; \
296 290 JP_EC_DIAG_ACCESS_MEMBAR; \
297 291 ldxa [scr1]ASI_EC_DIAG, %g0; \
298 292 JP_EC_DIAG_ACCESS_MEMBAR
299 293
300 294 /*
301 295 * Jalapeno version of ecache_flush_line. Uses Jalapeno Ecache Displacement
302 296 * Flush feature to flush all 4 sets/ways.
303 297 */
304 298 #define ECACHE_FLUSH_LINE(physaddr, ec_set_size, scr1, scr2) \
305 299 CPU_INDEX(scr1, scr2); \
306 300 sllx scr1, JP_ECFLUSH_PORTID_SHIFT, scr1; \
307 301 set JP_ECACHE_IDX_DISP_FLUSH, scr2; \
308 302 or scr2, scr1, scr2; \
309 303 sub ec_set_size, 1, scr1; \
310 304 and physaddr, scr1, scr1; \
311 305 or scr2, scr1, scr1; \
312 306 ECACHE_REFLUSH_LINE(ec_set_size, scr1, scr2)
313 307
314 308 /*
315 309 * Macro for getting ecache size from cpunodes structure
316 310 * scr1: Scratch, ecache size returned in this
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317 311 * scr2: Scratch
318 312 */
319 313 #define GET_ECACHE_SIZE(scr1, scr2) \
320 314 CPU_INDEX(scr1, scr2); \
321 315 mulx scr1, CPU_NODE_SIZE, scr1; \
322 316 set cpunodes + ECACHE_SIZE, scr2; \
323 317 ld [scr1 + scr2], scr1
324 318
325 319 /* END CSTYLED */
326 320
327 -#endif /* !lint */
328 -
329 -#if defined(lint)
330 -
331 -/* ARGSUSED */
332 -void
333 -shipit(int upaid, int bn)
334 -{ return; }
335 -
336 -#else /* lint */
337 -
338 321 /*
339 322 * Ship mondo to aid using implicit busy/nack pair (bn ignored)
340 323 */
341 324 ENTRY_NP(shipit)
342 325 sll %o0, IDCR_PID_SHIFT, %g1 ! IDCR<18:14> = agent id
343 326 or %g1, IDCR_OFFSET, %g1 ! IDCR<13:0> = 0x70
344 327 stxa %g0, [%g1]ASI_INTR_DISPATCH ! interrupt vector dispatch
345 328 membar #Sync
346 329 retl
347 330 nop
348 331 SET_SIZE(shipit)
349 332
350 -#endif /* lint */
351 333
352 -
353 334 /*
354 335 * flush_ecache:
355 336 * %o0 - 64 bit physical address
356 337 * %o1 - ecache size
357 338 * %o2 - ecache linesize
358 339 */
359 -#if defined(lint)
360 340
361 -/*ARGSUSED*/
362 -void
363 -flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize)
364 -{}
365 -
366 -#else /* !lint */
367 -
368 341 ENTRY(flush_ecache)
369 342 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
370 343 CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_1);
371 344 JP_FORCE_FULL_SPEED(%o3, %g1, %g2, %g3); /* %o3: saved speed */
372 345 flush_ecache_1:
373 346 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
374 347
375 348 /*
376 349 * Flush the entire Ecache using displacement flush.
377 350 */
378 351 ECACHE_FLUSHALL(%o1, %o2, %o0, %o4)
379 352
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380 353 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
381 354 CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_2);
382 355 JP_RESTORE_SPEED(%o3, %g1, %g2, %g3); /* %o3: saved speed */
383 356 flush_ecache_2:
384 357 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
385 358
386 359 retl
387 360 nop
388 361 SET_SIZE(flush_ecache)
389 362
390 -#endif /* lint */
391 363
392 -
393 -#if defined(lint)
394 -
395 -void
396 -fast_ecc_err(void)
397 -{}
398 -
399 -#else /* lint */
400 -
401 364 .section ".text"
402 365 .align 64
403 366 ENTRY_NP(fast_ecc_err)
404 367
405 368 /*
406 369 * Turn off CEEN and NCEEN.
407 370 */
408 371 ldxa [%g0]ASI_ESTATE_ERR, %g3
409 372 andn %g3, EN_REG_NCEEN + EN_REG_CEEN, %g4
410 373 stxa %g4, [%g0]ASI_ESTATE_ERR
411 374 membar #Sync ! membar sync required
412 375
413 376 /*
414 377 * Do the CPU log out capture.
415 378 * %g3 = "failed?" return value.
416 379 * %g2 = Input = AFAR. Output the clo_flags info which is passed
417 380 * into this macro via %g4. Output only valid if cpu_private
418 381 * struct has not been initialized.
419 382 * CHPR_FECCTL0_LOGOUT = cpu logout structure offset input
420 383 * %g4 = Trap information stored in the cpu logout flags field
421 384 * %g5 = scr1
422 385 * %g6 = scr2
423 386 * %g3 = scr3
424 387 * %g4 = scr4
425 388 */
426 389 and %g3, EN_REG_CEEN, %g4 ! store the CEEN value, TL=0
427 390 set CHPR_FECCTL0_LOGOUT, %g6
428 391 DO_CPU_LOGOUT(%g3, %g2, %g6, %g4, %g5, %g6, %g3, %g4)
429 392
430 393 /*
431 394 * Flush the Ecache to get the error out of the Ecache. If the UCC
432 395 * or UCU is on a dirty line, then the following flush will turn
433 396 * that into a WDC or WDU, respectively.
434 397 */
435 398 CPU_INDEX(%g4, %g5)
436 399 mulx %g4, CPU_NODE_SIZE, %g4
437 400 set cpunodes, %g5
438 401 add %g4, %g5, %g4
439 402 ld [%g4 + ECACHE_LINESIZE], %g5
440 403 ld [%g4 + ECACHE_SIZE], %g4
441 404 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
442 405 CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_err_1);
443 406 set jp_estar_tl0_data, %g6
444 407 stx %g2, [%g6 + 0]
445 408 stx %g3, [%g6 + 8]
446 409 JP_FORCE_FULL_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */
447 410 fast_ecc_err_1:
448 411 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
449 412 ECACHE_FLUSHALL(%g4, %g5, %g6, %g7)
450 413 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
451 414 CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_err_2);
452 415 JP_RESTORE_SPEED(%g2, %g3, %g6, %g7) /* %g2: saved speed */
453 416 set jp_estar_tl0_data, %g6
454 417 ldx [%g6 + 0], %g2
455 418 ldx [%g6 + 8], %g3
456 419 fast_ecc_err_2:
457 420 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
458 421
459 422 /*
460 423 * Flush the Dcache. Since bad data could have been installed in
461 424 * the Dcache we must flush it before re-enabling it.
462 425 */
463 426 ASM_LD(%g5, dcache_size)
464 427 ASM_LD(%g6, dcache_linesize)
465 428 CH_DCACHE_FLUSHALL(%g5, %g6, %g7)
466 429
467 430 /*
468 431 * Flush the Icache. Since we turned off the Icache to capture the
469 432 * Icache line it is now stale or corrupted and we must flush it
470 433 * before re-enabling it.
471 434 */
472 435 GET_CPU_PRIVATE_PTR(%g0, %g5, %g7, fast_ecc_err_4);
473 436 ld [%g5 + CHPR_ICACHE_LINESIZE], %g6
474 437 ba,pt %icc, 5f
475 438 ld [%g5 + CHPR_ICACHE_SIZE], %g5
476 439 fast_ecc_err_4:
477 440 ASM_LD(%g5, icache_size)
478 441 ASM_LD(%g6, icache_linesize)
479 442 5:
480 443 CH_ICACHE_FLUSHALL(%g5, %g6, %g7, %g4)
481 444
482 445 /*
483 446 * Restore the Dcache and Icache to the previous state.
484 447 */
485 448 stxa %g1, [%g0]ASI_DCU
486 449 flush %g0 /* flush required after changing the IC bit */
487 450
488 451 /*
489 452 * Make sure our CPU logout operation was successful.
490 453 */
491 454 cmp %g3, %g0
492 455 be 8f
493 456 nop
494 457
495 458 /*
496 459 * If the logout structure had been busy, how many times have
497 460 * we tried to use it and failed (nesting count)? If we have
498 461 * already recursed a substantial number of times, then we can
499 462 * assume things are not going to get better by themselves and
500 463 * so it would be best to panic.
501 464 */
502 465 cmp %g3, CLO_NESTING_MAX
503 466 blt 7f
504 467 nop
505 468
506 469 call ptl1_panic
507 470 mov PTL1_BAD_ECC, %g1
508 471
509 472 7:
510 473 /*
511 474 * Otherwise, if the logout structure was busy but we have not
512 475 * nested more times than our maximum value, then we simply
513 476 * issue a retry. Our TL=0 trap handler code will check and
514 477 * clear the AFSR after it is done logging what is currently
515 478 * in the logout struct and handle this event at that time.
516 479 */
517 480 retry
518 481 8:
519 482 /*
520 483 * Call cpu_fast_ecc_error via systrap at PIL 14 unless we're
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521 484 * already at PIL 15.
522 485 */
523 486 set cpu_fast_ecc_error, %g1
524 487 rdpr %pil, %g4
525 488 cmp %g4, PIL_14
526 489 ba sys_trap
527 490 movl %icc, PIL_14, %g4
528 491
529 492 SET_SIZE(fast_ecc_err)
530 493
531 -#endif /* lint */
532 494
533 -
534 495 /*
535 496 * Fast ECC error at TL>0 handler
536 497 * We get here via trap 70 at TL>0->Software trap 0 at TL>0. We enter
537 498 * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
538 499 * For a complete description of the Fast ECC at TL>0 handling see the
539 500 * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
540 501 * us3_common_asm.s
541 502 */
542 -#if defined(lint)
543 503
544 -void
545 -fast_ecc_tl1_err(void)
546 -{}
547 -
548 -#else /* lint */
549 -
550 504 .section ".text"
551 505 .align 64
552 506 ENTRY_NP(fast_ecc_tl1_err)
553 507
554 508 /*
555 509 * This macro turns off the D$/I$ if they are on and saves their
556 510 * original state in ch_err_tl1_tmp, saves all the %g registers in the
557 511 * ch_err_tl1_data structure, updates the ch_err_tl1_flags and saves
558 512 * the %tpc in ch_err_tl1_tpc. At the end of this macro, %g1 will
559 513 * point to the ch_err_tl1_data structure and the original D$/I$ state
560 514 * will be saved in ch_err_tl1_tmp. All %g registers except for %g1
561 515 * will be available.
562 516 */
563 517 CH_ERR_TL1_FECC_ENTER;
564 518
565 519 /*
566 520 * Get the diagnostic logout data. %g4 must be initialized to
567 521 * current CEEN state, %g5 must point to logout structure in
568 522 * ch_err_tl1_data_t. %g3 will contain the nesting count upon
569 523 * return.
570 524 */
571 525 ldxa [%g0]ASI_ESTATE_ERR, %g4
572 526 and %g4, EN_REG_CEEN, %g4
573 527 add %g1, CH_ERR_TL1_LOGOUT, %g5
574 528 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
575 529
576 530 /*
577 531 * If the logout nesting count is exceeded, we're probably
578 532 * not making any progress, try to panic instead.
579 533 */
580 534 cmp %g3, CLO_NESTING_MAX
581 535 bge fecc_tl1_err
582 536 nop
583 537
584 538 /*
585 539 * Save the current CEEN and NCEEN state in %g7 and turn them off
586 540 * before flushing the Ecache.
587 541 */
588 542 ldxa [%g0]ASI_ESTATE_ERR, %g7
589 543 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
590 544 stxa %g5, [%g0]ASI_ESTATE_ERR
591 545 membar #Sync
592 546
593 547 /*
594 548 * Flush the Ecache, using the largest possible cache size with the
595 549 * smallest possible line size since we can't get the actual sizes
596 550 * from the cpu_node due to DTLB misses.
597 551 */
598 552 set JP_ECACHE_MAX_SIZE, %g4
599 553 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
600 554 CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_tl1_err_1);
601 555 set jp_estar_tl1_data, %g6
602 556 stx %g2, [%g6 + 0]
603 557 stx %g3, [%g6 + 8]
604 558 JP_FORCE_FULL_SPEED(%g2, %g3, %g5, %g6)
605 559 fast_ecc_tl1_err_1:
606 560 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
607 561 ECACHE_FLUSHALL(%g4, JP_ECACHE_MAX_LSIZE, %g5, %g6)
608 562 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
609 563 CHK_JP_ERRATA85_ENABLED(%g6, fast_ecc_tl1_err_2);
610 564 JP_RESTORE_SPEED(%g2, %g3, %g5, %g6)
611 565 set jp_estar_tl1_data, %g6
612 566 ldx [%g6 + 0], %g2
613 567 ldx [%g6 + 8], %g3
614 568 fast_ecc_tl1_err_2:
615 569 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
616 570
617 571 /*
618 572 * Restore CEEN and NCEEN to the previous state.
619 573 */
620 574 stxa %g7, [%g0]ASI_ESTATE_ERR
621 575 membar #Sync
622 576
623 577 /*
624 578 * If we turned off the D$, then flush it and turn it back on.
625 579 */
626 580 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
627 581 andcc %g3, CH_ERR_TSTATE_DC_ON, %g0
628 582 bz %xcc, 3f
629 583 nop
630 584
631 585 /*
632 586 * Flush the D$.
633 587 */
634 588 ASM_LD(%g4, dcache_size)
635 589 ASM_LD(%g5, dcache_linesize)
636 590 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
637 591
638 592 /*
639 593 * Turn the D$ back on.
640 594 */
641 595 ldxa [%g0]ASI_DCU, %g3
642 596 or %g3, DCU_DC, %g3
643 597 stxa %g3, [%g0]ASI_DCU
644 598 membar #Sync
645 599 3:
646 600 /*
647 601 * If we turned off the I$, then flush it and turn it back on.
648 602 */
649 603 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
650 604 andcc %g3, CH_ERR_TSTATE_IC_ON, %g0
651 605 bz %xcc, 4f
652 606 nop
653 607
654 608 /*
655 609 * Flush the I$.
656 610 */
657 611 ASM_LD(%g4, icache_size)
658 612 ASM_LD(%g5, icache_linesize)
659 613 CH_ICACHE_FLUSHALL(%g4, %g5, %g6, %g3)
660 614
661 615 /*
662 616 * Turn the I$ back on. Changing DCU_IC requires flush.
663 617 */
664 618 ldxa [%g0]ASI_DCU, %g3
665 619 or %g3, DCU_IC, %g3
666 620 stxa %g3, [%g0]ASI_DCU
667 621 flush %g0
668 622 4:
669 623
670 624 #ifdef TRAPTRACE
671 625 /*
672 626 * Get current trap trace entry physical pointer.
673 627 */
674 628 CPU_INDEX(%g6, %g5)
675 629 sll %g6, TRAPTR_SIZE_SHIFT, %g6
676 630 set trap_trace_ctl, %g5
677 631 add %g6, %g5, %g6
678 632 ld [%g6 + TRAPTR_LIMIT], %g5
679 633 tst %g5
680 634 be %icc, skip_traptrace
681 635 nop
682 636 ldx [%g6 + TRAPTR_PBASE], %g5
683 637 ld [%g6 + TRAPTR_OFFSET], %g4
684 638 add %g5, %g4, %g5
685 639
686 640 /*
687 641 * Create trap trace entry.
688 642 */
689 643 rd %asi, %g7
690 644 wr %g0, TRAPTR_ASI, %asi
691 645 rd STICK, %g4
692 646 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
693 647 rdpr %tl, %g4
694 648 stha %g4, [%g5 + TRAP_ENT_TL]%asi
695 649 rdpr %tt, %g4
696 650 stha %g4, [%g5 + TRAP_ENT_TT]%asi
697 651 rdpr %tpc, %g4
698 652 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
699 653 rdpr %tstate, %g4
700 654 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
701 655 stna %sp, [%g5 + TRAP_ENT_SP]%asi
702 656 stna %g0, [%g5 + TRAP_ENT_TR]%asi
703 657 wr %g0, %g7, %asi
704 658 ldxa [%g1 + CH_ERR_TL1_SDW_AFAR]%asi, %g3
705 659 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR]%asi, %g4
706 660 wr %g0, TRAPTR_ASI, %asi
707 661 stna %g3, [%g5 + TRAP_ENT_F1]%asi
708 662 stna %g4, [%g5 + TRAP_ENT_F2]%asi
709 663 wr %g0, %g7, %asi
710 664 ldxa [%g1 + CH_ERR_TL1_AFAR]%asi, %g3
711 665 ldxa [%g1 + CH_ERR_TL1_AFSR]%asi, %g4
712 666 wr %g0, TRAPTR_ASI, %asi
713 667 stna %g3, [%g5 + TRAP_ENT_F3]%asi
714 668 stna %g4, [%g5 + TRAP_ENT_F4]%asi
715 669 wr %g0, %g7, %asi
716 670
717 671 /*
718 672 * Advance trap trace pointer.
719 673 */
720 674 ld [%g6 + TRAPTR_OFFSET], %g5
721 675 ld [%g6 + TRAPTR_LIMIT], %g4
722 676 st %g5, [%g6 + TRAPTR_LAST_OFFSET]
723 677 add %g5, TRAP_ENT_SIZE, %g5
724 678 sub %g4, TRAP_ENT_SIZE, %g4
725 679 cmp %g5, %g4
726 680 movge %icc, 0, %g5
727 681 st %g5, [%g6 + TRAPTR_OFFSET]
728 682 skip_traptrace:
729 683 #endif /* TRAPTRACE */
730 684
731 685 /*
732 686 * If nesting count is not zero, skip all the AFSR/AFAR
733 687 * handling and just do the necessary cache-flushing.
734 688 */
735 689 ldxa [%g1 + CH_ERR_TL1_NEST_CNT]%asi, %g2
736 690 brnz %g2, 6f
737 691 nop
738 692
739 693 /*
740 694 * If a UCU followed by a WDU has occurred go ahead and panic
741 695 * since a UE will occur (on the retry) before the UCU and WDU
742 696 * messages are enqueued.
743 697 */
744 698 ldxa [%g1 + CH_ERR_TL1_AFSR]%asi, %g3
745 699 set 1, %g4
746 700 sllx %g4, C_AFSR_UCU_SHIFT, %g4
747 701 btst %g4, %g3 ! UCU in original AFSR?
748 702 bz %xcc, 6f
749 703 nop
750 704 ldxa [%g0]ASI_AFSR, %g4 ! current AFSR
751 705 or %g3, %g4, %g3 ! %g3 = original + current AFSR
752 706 set 1, %g4
753 707 sllx %g4, C_AFSR_WDU_SHIFT, %g4
754 708 btst %g4, %g3 ! WDU in original or current AFSR?
755 709 bnz %xcc, fecc_tl1_err
756 710 nop
757 711
758 712 6:
759 713 /*
760 714 * We fall into this macro if we've successfully logged the error in
761 715 * the ch_err_tl1_data structure and want the PIL15 softint to pick
762 716 * it up and log it. %g1 must point to the ch_err_tl1_data structure.
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763 717 * Restores the %g registers and issues retry.
764 718 */
765 719 CH_ERR_TL1_EXIT;
766 720 /*
767 721 * Establish panic exit label.
768 722 */
769 723 CH_ERR_TL1_PANIC_EXIT(fecc_tl1_err);
770 724
771 725 SET_SIZE(fast_ecc_tl1_err)
772 726
773 -#endif /* lint */
774 727
775 -
776 -#if defined(lint)
777 -
778 -uint64_t
779 -get_jbus_config(void)
780 -{ return (0); }
781 -
782 -/* ARGSUSED */
783 -void
784 -set_jbus_config(uint64_t jbus_config)
785 -{}
786 -
787 -/* ARGSUSED */
788 -void
789 -set_mcu_ctl_reg1(uint64_t mcu_ctl)
790 -{}
791 -
792 -uint64_t
793 -get_mcu_ctl_reg1(void)
794 -{ return (0); }
795 -
796 -#else /* lint */
797 -
798 728 ENTRY(get_jbus_config)
799 729 ldxa [%g0]ASI_JBUS_CONFIG, %o0
800 730 retl
801 731 nop
802 732 SET_SIZE(get_jbus_config)
803 733
804 734 ENTRY(set_jbus_config)
805 735 stxa %o0, [%g0]ASI_JBUS_CONFIG
806 736 membar #Sync
807 737 retl
808 738 nop
809 739 SET_SIZE(set_jbus_config)
810 740
811 741
812 742 ENTRY(get_mcu_ctl_reg1)
813 743 ldxa [%g0]ASI_MCU_CTRL, %o0 ! MCU control reg1 is at offset 0
814 744 retl
815 745 nop
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816 746 SET_SIZE(get_mcu_ctl_reg1)
817 747
818 748
819 749 ENTRY(set_mcu_ctl_reg1)
820 750 stxa %o0, [%g0]ASI_MCU_CTRL ! MCU control reg1 is at offset 0
821 751 membar #Sync
822 752 retl
823 753 nop
824 754 SET_SIZE(set_mcu_ctl_reg1)
825 755
826 -#endif /* lint */
827 756
828 -
829 -#if defined(lint)
830 757 /*
831 758 * scrubphys - Pass in the aligned physical memory address
832 759 * that you want to scrub, along with the ecache set size.
833 760 *
834 761 * 1) Displacement flush the E$ line corresponding to %addr.
835 762 * The first ldxa guarantees that the %addr is no longer in
836 763 * M, O, or E (goes to I or S (if instruction fetch also happens).
837 764 * 2) "Write" the data using a CAS %addr,%g0,%g0.
838 765 * The casxa guarantees a transition from I to M or S to M.
839 766 * 3) Displacement flush the E$ line corresponding to %addr.
840 767 * The second ldxa pushes the M line out of the ecache, into the
841 768 * writeback buffers, on the way to memory.
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842 769 * 4) The "membar #Sync" pushes the cache line out of the writeback
843 770 * buffers onto the bus, on the way to dram finally.
844 771 *
845 772 * This is a modified version of the algorithm suggested by Gary Lauterbach.
846 773 * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
847 774 * as modified, but then we found out that for spitfire, if it misses in the
848 775 * E$ it will probably install as an M, but if it hits in the E$, then it
849 776 * will stay E, if the store doesn't happen. So the first displacement flush
850 777 * should ensure that the CAS will miss in the E$. Arrgh.
851 778 */
852 -/* ARGSUSED */
853 -void
854 -scrubphys(uint64_t paddr, int ecache_set_size)
855 -{}
856 -
857 -#else /* lint */
858 779 ENTRY(scrubphys)
859 780 rdpr %pstate, %o4
860 781 andn %o4, PSTATE_IE | PSTATE_AM, %o5
861 782 wrpr %o5, %g0, %pstate ! clear IE, AM bits
862 783
863 784 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
864 785 CHK_JP_ERRATA85_ENABLED(%g1, scrubphys_1);
865 786 JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
866 787 scrubphys_1:
867 788 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
868 789
869 790 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
870 791 casxa [%o0]ASI_MEM, %g0, %g0
871 792 ECACHE_REFLUSH_LINE(%o1, %o2, %o3)
872 793
873 794 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
874 795 CHK_JP_ERRATA85_ENABLED(%g1, scrubphys_2);
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875 796 JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
876 797 scrubphys_2:
877 798 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
878 799
879 800 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
880 801
881 802 retl
882 803 membar #Sync ! move the data out of the load buffer
883 804 SET_SIZE(scrubphys)
884 805
885 -#endif /* lint */
886 -
887 -
888 -#if defined(lint)
889 806 /*
890 807 * clearphys - Pass in the physical memory address of the checkblock
891 808 * that you want to push out, cleared with a recognizable pattern,
892 809 * from the ecache.
893 810 *
894 811 * To ensure that the ecc gets recalculated after the bad data is cleared,
895 812 * we must write out enough data to fill the w$ line (64 bytes). So we read
896 813 * in an entire ecache subblock's worth of data, and write it back out.
897 814 * Then we overwrite the 16 bytes of bad data with the pattern.
898 815 */
899 -/* ARGSUSED */
900 -void
901 -clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
902 -{
903 -}
904 -
905 -#else /* lint */
906 816 ENTRY(clearphys)
907 817 /* turn off IE, AM bits */
908 818 rdpr %pstate, %o4
909 819 andn %o4, PSTATE_IE | PSTATE_AM, %o5
910 820 wrpr %o5, %g0, %pstate
911 821
912 822 /* turn off NCEEN */
913 823 ldxa [%g0]ASI_ESTATE_ERR, %o5
914 824 andn %o5, EN_REG_NCEEN, %o3
915 825 stxa %o3, [%g0]ASI_ESTATE_ERR
916 826 membar #Sync
917 827
918 828 /* align address passed with 64 bytes subblock size */
919 829 mov CH_ECACHE_SUBBLK_SIZE, %o2
920 830 andn %o0, (CH_ECACHE_SUBBLK_SIZE - 1), %g1
921 831
922 832 /* move the good data into the W$ */
923 833 1:
924 834 subcc %o2, 8, %o2
925 835 ldxa [%g1 + %o2]ASI_MEM, %g2
926 836 bge 1b
927 837 stxa %g2, [%g1 + %o2]ASI_MEM
928 838
929 839 /* now overwrite the bad data */
930 840 setx 0xbadecc00badecc01, %g1, %g2
931 841 stxa %g2, [%o0]ASI_MEM
932 842 mov 8, %g1
933 843 stxa %g2, [%o0 + %g1]ASI_MEM
934 844
935 845 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
936 846 CHK_JP_ERRATA85_ENABLED(%g1, clearphys_1);
937 847 JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
938 848 clearphys_1:
939 849 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
940 850
941 851 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
942 852 casxa [%o0]ASI_MEM, %g0, %g0
943 853 ECACHE_REFLUSH_LINE(%o1, %o2, %o3)
944 854
945 855 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
946 856 CHK_JP_ERRATA85_ENABLED(%g1, clearphys_2);
947 857 JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
948 858 clearphys_2:
949 859 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
950 860
951 861 /* clear the AFSR */
952 862 ldxa [%g0]ASI_AFSR, %o1
953 863 stxa %o1, [%g0]ASI_AFSR
954 864 membar #Sync
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955 865
956 866 /* turn NCEEN back on */
957 867 stxa %o5, [%g0]ASI_ESTATE_ERR
958 868 membar #Sync
959 869
960 870 /* return and re-enable IE and AM */
961 871 retl
962 872 wrpr %g0, %o4, %pstate
963 873 SET_SIZE(clearphys)
964 874
965 -#endif /* lint */
966 -
967 875
968 -#if defined(lint)
969 876 /*
970 877 * Jalapeno Ecache displacement flush the specified line from the E$
971 878 *
972 879 * Register usage:
973 880 * %o0 - 64 bit physical address for flushing
974 881 * %o1 - Ecache set size
975 882 */
976 -/*ARGSUSED*/
977 -void
978 -ecache_flush_line(uint64_t flushaddr, int ec_set_size)
979 -{
980 -}
981 -#else /* lint */
982 883 ENTRY(ecache_flush_line)
983 884
984 885 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
985 886 CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_1);
986 887 JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
987 888 ecache_flush_line_1:
988 889 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
989 890
990 891 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
991 892
992 893 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
993 894 CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_2);
994 895 JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
995 896 ecache_flush_line_2:
996 897 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
997 898
998 899 retl
999 900 nop
1000 901 SET_SIZE(ecache_flush_line)
1001 -#endif /* lint */
1002 902
1003 903
1004 904 /*
1005 905 * Perform necessary cpu workaround to ensure jbus ordering.
1006 906 * Called only from Fire systems.
1007 907 * CPU's internal "invalidate FIFOs" are flushed.
1008 908 */
1009 909
1010 -#if defined(lint)
1011 -void
1012 -jbus_stst_order()
1013 -{}
1014 -#else /* lint */
1015 -
1016 910 #define VIS_BLOCKSIZE 64
1017 911
1018 912 .seg ".data"
1019 913 .align VIS_BLOCKSIZE
1020 914 .type sync_buf, #object
1021 915 sync_buf:
1022 916 .skip VIS_BLOCKSIZE
1023 917 .size sync_buf, VIS_BLOCKSIZE
1024 918
1025 919 ENTRY(jbus_stst_order)
1026 920 set sync_buf, %o1
1027 921
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1028 922 rd %fprs, %o2 ! %o2 = saved fprs
1029 923 or %o2, FPRS_FEF, %o3
1030 924 wr %g0, %o3, %fprs ! make sure fp is enabled
1031 925 stda %d0, [%o1]ASI_BLK_COMMIT_P
1032 926 wr %o2, 0, %fprs ! restore fprs
1033 927
1034 928 retl
1035 929 membar #Sync
1036 930 SET_SIZE(jbus_stst_order)
1037 931
1038 -#endif /* lint */
1039 -
1040 -#if defined(lint)
1041 932 /*
1042 933 * This routine will not be called in Jalapeno systems.
1043 934 */
1044 -void
1045 -flush_ipb(void)
1046 -{ return; }
1047 -
1048 -#else /* lint */
1049 -
1050 935 ENTRY(flush_ipb)
1051 936 retl
1052 937 nop
1053 938 SET_SIZE(flush_ipb)
1054 939
1055 -#endif /* lint */
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