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          --- old/usr/src/uts/sun4u/cpu/us3_jalapeno_asm.s
          +++ new/usr/src/uts/sun4u/cpu/us3_jalapeno_asm.s
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  19   19   *
  20   20   * CDDL HEADER END
  21   21   */
  22   22  /*
  23   23   * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  24   24   * Use is subject to license terms.
  25   25   *
  26   26   * Assembly code support for the jalapeno module
  27   27   */
  28   28  
  29      -#pragma ident   "%Z%%M% %I%     %E% SMI"
  30      -
  31      -#if !defined(lint)
  32   29  #include "assym.h"
  33      -#endif  /* lint */
  34   30  
  35   31  #include <sys/asm_linkage.h>
  36   32  #include <sys/mmu.h>
  37   33  #include <vm/hat_sfmmu.h>
  38   34  #include <sys/machparam.h>
  39   35  #include <sys/machcpuvar.h>
  40   36  #include <sys/machthread.h>
  41   37  #include <sys/machtrap.h>
  42   38  #include <sys/privregs.h>
  43   39  #include <sys/asm_linkage.h>
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  47   43  #include <sys/xc_impl.h>
  48   44  #include <sys/intreg.h>
  49   45  #include <sys/async.h>
  50   46  #include <sys/clock.h>
  51   47  #include <sys/cheetahasm.h>
  52   48  
  53   49  #ifdef TRAPTRACE
  54   50  #include <sys/traptrace.h>
  55   51  #endif /* TRAPTRACE */
  56   52  
  57      -#if !defined(lint)
  58      -
  59   53  /* BEGIN CSTYLED */
  60   54  
  61   55  #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
  62   56  
  63   57  #define CHK_JP_ERRATA85_ENABLED(scr, label)                             \
  64   58          ASM_LD(scr, jp_errata_85_active);                               \
  65   59          cmp     scr, 1;                                                 \
  66   60          bne     %icc, label;                                            \
  67   61          nop
  68   62  
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 317  311   *  scr2:    Scratch
 318  312   */
 319  313  #define GET_ECACHE_SIZE(scr1, scr2)                                     \
 320  314          CPU_INDEX(scr1, scr2);                                          \
 321  315          mulx    scr1, CPU_NODE_SIZE, scr1;                              \
 322  316          set     cpunodes + ECACHE_SIZE, scr2;                           \
 323  317          ld      [scr1 + scr2], scr1
 324  318  
 325  319  /* END CSTYLED */
 326  320  
 327      -#endif  /* !lint */
 328      -
 329      -#if defined(lint)
 330      -
 331      -/* ARGSUSED */
 332      -void
 333      -shipit(int upaid, int bn)
 334      -{ return; }
 335      -
 336      -#else   /* lint */
 337      -
 338  321  /*
 339  322   * Ship mondo to aid using implicit busy/nack pair (bn ignored)
 340  323   */
 341  324          ENTRY_NP(shipit)
 342  325          sll     %o0, IDCR_PID_SHIFT, %g1        ! IDCR<18:14> = agent id
 343  326          or      %g1, IDCR_OFFSET, %g1           ! IDCR<13:0> = 0x70
 344  327          stxa    %g0, [%g1]ASI_INTR_DISPATCH     ! interrupt vector dispatch
 345  328          membar  #Sync
 346  329          retl
 347  330          nop
 348  331          SET_SIZE(shipit)
 349  332  
 350      -#endif  /* lint */
 351  333  
 352      -
 353  334  /*
 354  335   * flush_ecache:
 355  336   *      %o0 - 64 bit physical address
 356  337   *      %o1 - ecache size
 357  338   *      %o2 - ecache linesize
 358  339   */
 359      -#if defined(lint)
 360  340  
 361      -/*ARGSUSED*/
 362      -void
 363      -flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize)
 364      -{}
 365      -
 366      -#else /* !lint */
 367      -
 368  341          ENTRY(flush_ecache)
 369  342  #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
 370  343          CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_1);
 371  344          JP_FORCE_FULL_SPEED(%o3, %g1, %g2, %g3);        /* %o3: saved speed */
 372  345  flush_ecache_1:
 373  346  #endif  /* JALAPENO && JALAPENO_ERRATA_85 */
 374  347  
 375  348          /*
 376  349           * Flush the entire Ecache using displacement flush.
 377  350           */
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 380  353  #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
 381  354          CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_2);
 382  355          JP_RESTORE_SPEED(%o3, %g1, %g2, %g3);           /* %o3: saved speed */
 383  356  flush_ecache_2:
 384  357  #endif  /* JALAPENO && JALAPENO_ERRATA_85 */
 385  358  
 386  359          retl
 387  360          nop
 388  361          SET_SIZE(flush_ecache)
 389  362  
 390      -#endif /* lint */
 391  363  
 392      -
 393      -#if defined(lint)
 394      -
 395      -void
 396      -fast_ecc_err(void)
 397      -{}
 398      -
 399      -#else   /* lint */
 400      -
 401  364          .section ".text"
 402  365          .align  64
 403  366          ENTRY_NP(fast_ecc_err)
 404  367          
 405  368          /*
 406  369           * Turn off CEEN and NCEEN.
 407  370           */
 408  371          ldxa    [%g0]ASI_ESTATE_ERR, %g3
 409  372          andn    %g3, EN_REG_NCEEN + EN_REG_CEEN, %g4
 410  373          stxa    %g4, [%g0]ASI_ESTATE_ERR
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 521  484           * already at PIL 15.
 522  485           */
 523  486          set     cpu_fast_ecc_error, %g1
 524  487          rdpr    %pil, %g4
 525  488          cmp     %g4, PIL_14
 526  489          ba      sys_trap
 527  490            movl  %icc, PIL_14, %g4
 528  491  
 529  492          SET_SIZE(fast_ecc_err)
 530  493  
 531      -#endif  /* lint */
 532  494  
 533      -
 534  495  /*
 535  496   * Fast ECC error at TL>0 handler
 536  497   * We get here via trap 70 at TL>0->Software trap 0 at TL>0.  We enter
 537  498   * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
 538  499   * For a complete description of the Fast ECC at TL>0 handling see the
 539  500   * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
 540  501   * us3_common_asm.s
 541  502   */
 542      -#if defined(lint)
 543  503  
 544      -void
 545      -fast_ecc_tl1_err(void)
 546      -{}
 547      -
 548      -#else   /* lint */
 549      -
 550  504          .section ".text"
 551  505          .align  64
 552  506          ENTRY_NP(fast_ecc_tl1_err)
 553  507  
 554  508          /*
 555  509           * This macro turns off the D$/I$ if they are on and saves their
 556  510           * original state in ch_err_tl1_tmp, saves all the %g registers in the
 557  511           * ch_err_tl1_data structure, updates the ch_err_tl1_flags and saves
 558  512           * the %tpc in ch_err_tl1_tpc.  At the end of this macro, %g1 will
 559  513           * point to the ch_err_tl1_data structure and the original D$/I$ state
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 763  717           * Restores the %g registers and issues retry.
 764  718           */
 765  719          CH_ERR_TL1_EXIT;
 766  720          /*
 767  721           * Establish panic exit label.
 768  722           */
 769  723          CH_ERR_TL1_PANIC_EXIT(fecc_tl1_err);
 770  724  
 771  725          SET_SIZE(fast_ecc_tl1_err)
 772  726  
 773      -#endif  /* lint */
 774  727  
 775      -
 776      -#if defined(lint)
 777      -
 778      -uint64_t
 779      -get_jbus_config(void)
 780      -{ return (0); }
 781      -
 782      -/* ARGSUSED */
 783      -void
 784      -set_jbus_config(uint64_t jbus_config)
 785      -{}
 786      -
 787      -/* ARGSUSED */
 788      -void
 789      -set_mcu_ctl_reg1(uint64_t mcu_ctl)
 790      -{}
 791      -
 792      -uint64_t
 793      -get_mcu_ctl_reg1(void)
 794      -{ return (0); }
 795      -
 796      -#else   /* lint */
 797      -
 798  728          ENTRY(get_jbus_config)
 799  729          ldxa    [%g0]ASI_JBUS_CONFIG, %o0
 800  730          retl
 801  731          nop
 802  732          SET_SIZE(get_jbus_config)
 803  733  
 804  734          ENTRY(set_jbus_config)
 805  735          stxa    %o0, [%g0]ASI_JBUS_CONFIG
 806  736          membar  #Sync
 807  737          retl
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 816  746          SET_SIZE(get_mcu_ctl_reg1)
 817  747  
 818  748  
 819  749          ENTRY(set_mcu_ctl_reg1)
 820  750          stxa    %o0, [%g0]ASI_MCU_CTRL  ! MCU control reg1 is at offset 0
 821  751          membar  #Sync
 822  752          retl
 823  753          nop
 824  754          SET_SIZE(set_mcu_ctl_reg1)
 825  755  
 826      -#endif  /* lint */
 827  756  
 828      -
 829      -#if defined(lint)
 830  757  /*
 831  758   * scrubphys - Pass in the aligned physical memory address
 832  759   * that you want to scrub, along with the ecache set size.
 833  760   *
 834  761   *      1) Displacement flush the E$ line corresponding to %addr.
 835  762   *         The first ldxa guarantees that the %addr is no longer in
 836  763   *         M, O, or E (goes to I or S (if instruction fetch also happens).
 837  764   *      2) "Write" the data using a CAS %addr,%g0,%g0.
 838  765   *         The casxa guarantees a transition from I to M or S to M.
 839  766   *      3) Displacement flush the E$ line corresponding to %addr.
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 842  769   *      4) The "membar #Sync" pushes the cache line out of the writeback
 843  770   *         buffers onto the bus, on the way to dram finally.
 844  771   *
 845  772   * This is a modified version of the algorithm suggested by Gary Lauterbach.
 846  773   * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
 847  774   * as modified, but then we found out that for spitfire, if it misses in the
 848  775   * E$ it will probably install as an M, but if it hits in the E$, then it
 849  776   * will stay E, if the store doesn't happen. So the first displacement flush
 850  777   * should ensure that the CAS will miss in the E$.  Arrgh.
 851  778   */
 852      -/* ARGSUSED */
 853      -void
 854      -scrubphys(uint64_t paddr, int ecache_set_size)
 855      -{}
 856      -
 857      -#else   /* lint */
 858  779          ENTRY(scrubphys)
 859  780          rdpr    %pstate, %o4
 860  781          andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 861  782          wrpr    %o5, %g0, %pstate       ! clear IE, AM bits
 862  783  
 863  784  #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
 864  785          CHK_JP_ERRATA85_ENABLED(%g1, scrubphys_1);
 865  786          JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3)         /* %o5: saved speed */
 866  787  scrubphys_1:
 867  788  #endif  /* JALAPENO && JALAPENO_ERRATA_85 */
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 875  796          JP_RESTORE_SPEED(%o5, %g1, %g2, %g3)            /* %o5: saved speed */
 876  797  scrubphys_2:
 877  798  #endif  /* JALAPENO && JALAPENO_ERRATA_85 */
 878  799  
 879  800          wrpr    %g0, %o4, %pstate       ! restore earlier pstate register value
 880  801  
 881  802          retl
 882  803          membar  #Sync                   ! move the data out of the load buffer
 883  804          SET_SIZE(scrubphys)
 884  805  
 885      -#endif  /* lint */
 886      -
 887      -
 888      -#if defined(lint)
 889  806  /*
 890  807   * clearphys - Pass in the physical memory address of the checkblock
 891  808   * that you want to push out, cleared with a recognizable pattern,
 892  809   * from the ecache.
 893  810   *
 894  811   * To ensure that the ecc gets recalculated after the bad data is cleared,
 895  812   * we must write out enough data to fill the w$ line (64 bytes). So we read
 896  813   * in an entire ecache subblock's worth of data, and write it back out.
 897  814   * Then we overwrite the 16 bytes of bad data with the pattern.
 898  815   */
 899      -/* ARGSUSED */
 900      -void
 901      -clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
 902      -{
 903      -}
 904      -
 905      -#else   /* lint */
 906  816          ENTRY(clearphys)
 907  817          /* turn off IE, AM bits */
 908  818          rdpr    %pstate, %o4
 909  819          andn    %o4, PSTATE_IE | PSTATE_AM, %o5
 910  820          wrpr    %o5, %g0, %pstate
 911  821  
 912  822          /* turn off NCEEN */
 913  823          ldxa    [%g0]ASI_ESTATE_ERR, %o5
 914  824          andn    %o5, EN_REG_NCEEN, %o3
 915  825          stxa    %o3, [%g0]ASI_ESTATE_ERR
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 955  865  
 956  866          /* turn NCEEN back on */
 957  867          stxa    %o5, [%g0]ASI_ESTATE_ERR
 958  868          membar  #Sync
 959  869  
 960  870          /* return and re-enable IE and AM */
 961  871          retl
 962  872            wrpr  %g0, %o4, %pstate
 963  873          SET_SIZE(clearphys)
 964  874  
 965      -#endif  /* lint */
 966      -        
 967  875  
 968      -#if defined(lint)
 969  876  /*
 970  877   * Jalapeno Ecache displacement flush the specified line from the E$
 971  878   *
 972  879   * Register usage:
 973  880   *      %o0 - 64 bit physical address for flushing
 974  881   *      %o1 - Ecache set size
 975  882   */
 976      -/*ARGSUSED*/
 977      -void
 978      -ecache_flush_line(uint64_t flushaddr, int ec_set_size)
 979      -{
 980      -}
 981      -#else   /* lint */
 982  883          ENTRY(ecache_flush_line)
 983  884  
 984  885  #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
 985  886          CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_1);
 986  887          JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3)         /* %o5: saved speed */
 987  888  ecache_flush_line_1:
 988  889  #endif  /* JALAPENO && JALAPENO_ERRATA_85 */
 989  890  
 990  891          ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
 991  892  
 992  893  #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
 993  894          CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_2);
 994  895          JP_RESTORE_SPEED(%o5, %g1, %g2, %g3)            /* %o5: saved speed */
 995  896  ecache_flush_line_2:
 996  897  #endif  /* JALAPENO && JALAPENO_ERRATA_85 */
 997  898  
 998  899          retl
 999  900            nop
1000  901          SET_SIZE(ecache_flush_line)
1001      -#endif  /* lint */
1002  902  
1003  903  
1004  904  /*
1005  905   * Perform necessary cpu workaround to ensure jbus ordering.
1006  906   * Called only from Fire systems.
1007  907   * CPU's internal "invalidate FIFOs" are flushed.
1008  908   */
1009  909  
1010      -#if defined(lint)
1011      -void
1012      -jbus_stst_order()
1013      -{}
1014      -#else   /* lint */
1015      -
1016  910  #define VIS_BLOCKSIZE   64
1017  911  
1018  912          .seg    ".data"
1019  913          .align  VIS_BLOCKSIZE
1020  914          .type   sync_buf, #object
1021  915  sync_buf:
1022  916          .skip   VIS_BLOCKSIZE
1023  917          .size   sync_buf, VIS_BLOCKSIZE
1024  918  
1025  919          ENTRY(jbus_stst_order)
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1028  922          rd      %fprs, %o2                      ! %o2 = saved fprs
1029  923          or      %o2, FPRS_FEF, %o3
1030  924          wr      %g0, %o3, %fprs                 ! make sure fp is enabled
1031  925          stda    %d0, [%o1]ASI_BLK_COMMIT_P
1032  926          wr      %o2, 0, %fprs                   ! restore fprs
1033  927  
1034  928          retl
1035  929          membar  #Sync
1036  930          SET_SIZE(jbus_stst_order)
1037  931  
1038      -#endif  /* lint */
1039      -
1040      -#if defined(lint)
1041  932  /*
1042  933   * This routine will not be called in Jalapeno systems.
1043  934   */
1044      -void
1045      -flush_ipb(void)
1046      -{ return; }
1047      -
1048      -#else   /* lint */
1049      -
1050  935          ENTRY(flush_ipb)
1051  936          retl
1052  937          nop
1053  938          SET_SIZE(flush_ipb)
1054  939  
1055      -#endif  /* lint */
    
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