9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 *
26 * Assembly code support for the jalapeno module
27 */
28
29 #pragma ident "%Z%%M% %I% %E% SMI"
30
31 #if !defined(lint)
32 #include "assym.h"
33 #endif /* lint */
34
35 #include <sys/asm_linkage.h>
36 #include <sys/mmu.h>
37 #include <vm/hat_sfmmu.h>
38 #include <sys/machparam.h>
39 #include <sys/machcpuvar.h>
40 #include <sys/machthread.h>
41 #include <sys/machtrap.h>
42 #include <sys/privregs.h>
43 #include <sys/asm_linkage.h>
44 #include <sys/trap.h>
45 #include <sys/cheetahregs.h>
46 #include <sys/us3_module.h>
47 #include <sys/xc_impl.h>
48 #include <sys/intreg.h>
49 #include <sys/async.h>
50 #include <sys/clock.h>
51 #include <sys/cheetahasm.h>
52
53 #ifdef TRAPTRACE
54 #include <sys/traptrace.h>
55 #endif /* TRAPTRACE */
56
57 #if !defined(lint)
58
59 /* BEGIN CSTYLED */
60
61 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
62
63 #define CHK_JP_ERRATA85_ENABLED(scr, label) \
64 ASM_LD(scr, jp_errata_85_active); \
65 cmp scr, 1; \
66 bne %icc, label; \
67 nop
68
69 #define SET_64BIT_PA(dest, scr, hi32, lo32) \
70 set hi32, scr; \
71 sllx scr, 32, scr; \
72 sethi %hi(lo32), dest; \
73 or dest, %lo(lo32), dest; \
74 or scr, dest, dest
75
76 /*
77 * Macro to trigger Jalapeno/Tomatillo speed change
78 * j_chng_pa - scratch register
307 set JP_ECACHE_IDX_DISP_FLUSH, scr2; \
308 or scr2, scr1, scr2; \
309 sub ec_set_size, 1, scr1; \
310 and physaddr, scr1, scr1; \
311 or scr2, scr1, scr1; \
312 ECACHE_REFLUSH_LINE(ec_set_size, scr1, scr2)
313
314 /*
315 * Macro for getting ecache size from cpunodes structure
316 * scr1: Scratch, ecache size returned in this
317 * scr2: Scratch
318 */
319 #define GET_ECACHE_SIZE(scr1, scr2) \
320 CPU_INDEX(scr1, scr2); \
321 mulx scr1, CPU_NODE_SIZE, scr1; \
322 set cpunodes + ECACHE_SIZE, scr2; \
323 ld [scr1 + scr2], scr1
324
325 /* END CSTYLED */
326
327 #endif /* !lint */
328
329 #if defined(lint)
330
331 /* ARGSUSED */
332 void
333 shipit(int upaid, int bn)
334 { return; }
335
336 #else /* lint */
337
338 /*
339 * Ship mondo to aid using implicit busy/nack pair (bn ignored)
340 */
341 ENTRY_NP(shipit)
342 sll %o0, IDCR_PID_SHIFT, %g1 ! IDCR<18:14> = agent id
343 or %g1, IDCR_OFFSET, %g1 ! IDCR<13:0> = 0x70
344 stxa %g0, [%g1]ASI_INTR_DISPATCH ! interrupt vector dispatch
345 membar #Sync
346 retl
347 nop
348 SET_SIZE(shipit)
349
350 #endif /* lint */
351
352
353 /*
354 * flush_ecache:
355 * %o0 - 64 bit physical address
356 * %o1 - ecache size
357 * %o2 - ecache linesize
358 */
359 #if defined(lint)
360
361 /*ARGSUSED*/
362 void
363 flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize)
364 {}
365
366 #else /* !lint */
367
368 ENTRY(flush_ecache)
369 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
370 CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_1);
371 JP_FORCE_FULL_SPEED(%o3, %g1, %g2, %g3); /* %o3: saved speed */
372 flush_ecache_1:
373 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
374
375 /*
376 * Flush the entire Ecache using displacement flush.
377 */
378 ECACHE_FLUSHALL(%o1, %o2, %o0, %o4)
379
380 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
381 CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_2);
382 JP_RESTORE_SPEED(%o3, %g1, %g2, %g3); /* %o3: saved speed */
383 flush_ecache_2:
384 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
385
386 retl
387 nop
388 SET_SIZE(flush_ecache)
389
390 #endif /* lint */
391
392
393 #if defined(lint)
394
395 void
396 fast_ecc_err(void)
397 {}
398
399 #else /* lint */
400
401 .section ".text"
402 .align 64
403 ENTRY_NP(fast_ecc_err)
404
405 /*
406 * Turn off CEEN and NCEEN.
407 */
408 ldxa [%g0]ASI_ESTATE_ERR, %g3
409 andn %g3, EN_REG_NCEEN + EN_REG_CEEN, %g4
410 stxa %g4, [%g0]ASI_ESTATE_ERR
411 membar #Sync ! membar sync required
412
413 /*
414 * Do the CPU log out capture.
415 * %g3 = "failed?" return value.
416 * %g2 = Input = AFAR. Output the clo_flags info which is passed
417 * into this macro via %g4. Output only valid if cpu_private
418 * struct has not been initialized.
419 * CHPR_FECCTL0_LOGOUT = cpu logout structure offset input
420 * %g4 = Trap information stored in the cpu logout flags field
511 * Otherwise, if the logout structure was busy but we have not
512 * nested more times than our maximum value, then we simply
513 * issue a retry. Our TL=0 trap handler code will check and
514 * clear the AFSR after it is done logging what is currently
515 * in the logout struct and handle this event at that time.
516 */
517 retry
518 8:
519 /*
520 * Call cpu_fast_ecc_error via systrap at PIL 14 unless we're
521 * already at PIL 15.
522 */
523 set cpu_fast_ecc_error, %g1
524 rdpr %pil, %g4
525 cmp %g4, PIL_14
526 ba sys_trap
527 movl %icc, PIL_14, %g4
528
529 SET_SIZE(fast_ecc_err)
530
531 #endif /* lint */
532
533
534 /*
535 * Fast ECC error at TL>0 handler
536 * We get here via trap 70 at TL>0->Software trap 0 at TL>0. We enter
537 * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
538 * For a complete description of the Fast ECC at TL>0 handling see the
539 * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
540 * us3_common_asm.s
541 */
542 #if defined(lint)
543
544 void
545 fast_ecc_tl1_err(void)
546 {}
547
548 #else /* lint */
549
550 .section ".text"
551 .align 64
552 ENTRY_NP(fast_ecc_tl1_err)
553
554 /*
555 * This macro turns off the D$/I$ if they are on and saves their
556 * original state in ch_err_tl1_tmp, saves all the %g registers in the
557 * ch_err_tl1_data structure, updates the ch_err_tl1_flags and saves
558 * the %tpc in ch_err_tl1_tpc. At the end of this macro, %g1 will
559 * point to the ch_err_tl1_data structure and the original D$/I$ state
560 * will be saved in ch_err_tl1_tmp. All %g registers except for %g1
561 * will be available.
562 */
563 CH_ERR_TL1_FECC_ENTER;
564
565 /*
566 * Get the diagnostic logout data. %g4 must be initialized to
567 * current CEEN state, %g5 must point to logout structure in
568 * ch_err_tl1_data_t. %g3 will contain the nesting count upon
569 * return.
753 sllx %g4, C_AFSR_WDU_SHIFT, %g4
754 btst %g4, %g3 ! WDU in original or current AFSR?
755 bnz %xcc, fecc_tl1_err
756 nop
757
758 6:
759 /*
760 * We fall into this macro if we've successfully logged the error in
761 * the ch_err_tl1_data structure and want the PIL15 softint to pick
762 * it up and log it. %g1 must point to the ch_err_tl1_data structure.
763 * Restores the %g registers and issues retry.
764 */
765 CH_ERR_TL1_EXIT;
766 /*
767 * Establish panic exit label.
768 */
769 CH_ERR_TL1_PANIC_EXIT(fecc_tl1_err);
770
771 SET_SIZE(fast_ecc_tl1_err)
772
773 #endif /* lint */
774
775
776 #if defined(lint)
777
778 uint64_t
779 get_jbus_config(void)
780 { return (0); }
781
782 /* ARGSUSED */
783 void
784 set_jbus_config(uint64_t jbus_config)
785 {}
786
787 /* ARGSUSED */
788 void
789 set_mcu_ctl_reg1(uint64_t mcu_ctl)
790 {}
791
792 uint64_t
793 get_mcu_ctl_reg1(void)
794 { return (0); }
795
796 #else /* lint */
797
798 ENTRY(get_jbus_config)
799 ldxa [%g0]ASI_JBUS_CONFIG, %o0
800 retl
801 nop
802 SET_SIZE(get_jbus_config)
803
804 ENTRY(set_jbus_config)
805 stxa %o0, [%g0]ASI_JBUS_CONFIG
806 membar #Sync
807 retl
808 nop
809 SET_SIZE(set_jbus_config)
810
811
812 ENTRY(get_mcu_ctl_reg1)
813 ldxa [%g0]ASI_MCU_CTRL, %o0 ! MCU control reg1 is at offset 0
814 retl
815 nop
816 SET_SIZE(get_mcu_ctl_reg1)
817
818
819 ENTRY(set_mcu_ctl_reg1)
820 stxa %o0, [%g0]ASI_MCU_CTRL ! MCU control reg1 is at offset 0
821 membar #Sync
822 retl
823 nop
824 SET_SIZE(set_mcu_ctl_reg1)
825
826 #endif /* lint */
827
828
829 #if defined(lint)
830 /*
831 * scrubphys - Pass in the aligned physical memory address
832 * that you want to scrub, along with the ecache set size.
833 *
834 * 1) Displacement flush the E$ line corresponding to %addr.
835 * The first ldxa guarantees that the %addr is no longer in
836 * M, O, or E (goes to I or S (if instruction fetch also happens).
837 * 2) "Write" the data using a CAS %addr,%g0,%g0.
838 * The casxa guarantees a transition from I to M or S to M.
839 * 3) Displacement flush the E$ line corresponding to %addr.
840 * The second ldxa pushes the M line out of the ecache, into the
841 * writeback buffers, on the way to memory.
842 * 4) The "membar #Sync" pushes the cache line out of the writeback
843 * buffers onto the bus, on the way to dram finally.
844 *
845 * This is a modified version of the algorithm suggested by Gary Lauterbach.
846 * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
847 * as modified, but then we found out that for spitfire, if it misses in the
848 * E$ it will probably install as an M, but if it hits in the E$, then it
849 * will stay E, if the store doesn't happen. So the first displacement flush
850 * should ensure that the CAS will miss in the E$. Arrgh.
851 */
852 /* ARGSUSED */
853 void
854 scrubphys(uint64_t paddr, int ecache_set_size)
855 {}
856
857 #else /* lint */
858 ENTRY(scrubphys)
859 rdpr %pstate, %o4
860 andn %o4, PSTATE_IE | PSTATE_AM, %o5
861 wrpr %o5, %g0, %pstate ! clear IE, AM bits
862
863 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
864 CHK_JP_ERRATA85_ENABLED(%g1, scrubphys_1);
865 JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
866 scrubphys_1:
867 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
868
869 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
870 casxa [%o0]ASI_MEM, %g0, %g0
871 ECACHE_REFLUSH_LINE(%o1, %o2, %o3)
872
873 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
874 CHK_JP_ERRATA85_ENABLED(%g1, scrubphys_2);
875 JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
876 scrubphys_2:
877 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
878
879 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
880
881 retl
882 membar #Sync ! move the data out of the load buffer
883 SET_SIZE(scrubphys)
884
885 #endif /* lint */
886
887
888 #if defined(lint)
889 /*
890 * clearphys - Pass in the physical memory address of the checkblock
891 * that you want to push out, cleared with a recognizable pattern,
892 * from the ecache.
893 *
894 * To ensure that the ecc gets recalculated after the bad data is cleared,
895 * we must write out enough data to fill the w$ line (64 bytes). So we read
896 * in an entire ecache subblock's worth of data, and write it back out.
897 * Then we overwrite the 16 bytes of bad data with the pattern.
898 */
899 /* ARGSUSED */
900 void
901 clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
902 {
903 }
904
905 #else /* lint */
906 ENTRY(clearphys)
907 /* turn off IE, AM bits */
908 rdpr %pstate, %o4
909 andn %o4, PSTATE_IE | PSTATE_AM, %o5
910 wrpr %o5, %g0, %pstate
911
912 /* turn off NCEEN */
913 ldxa [%g0]ASI_ESTATE_ERR, %o5
914 andn %o5, EN_REG_NCEEN, %o3
915 stxa %o3, [%g0]ASI_ESTATE_ERR
916 membar #Sync
917
918 /* align address passed with 64 bytes subblock size */
919 mov CH_ECACHE_SUBBLK_SIZE, %o2
920 andn %o0, (CH_ECACHE_SUBBLK_SIZE - 1), %g1
921
922 /* move the good data into the W$ */
923 1:
924 subcc %o2, 8, %o2
925 ldxa [%g1 + %o2]ASI_MEM, %g2
945 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
946 CHK_JP_ERRATA85_ENABLED(%g1, clearphys_2);
947 JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
948 clearphys_2:
949 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
950
951 /* clear the AFSR */
952 ldxa [%g0]ASI_AFSR, %o1
953 stxa %o1, [%g0]ASI_AFSR
954 membar #Sync
955
956 /* turn NCEEN back on */
957 stxa %o5, [%g0]ASI_ESTATE_ERR
958 membar #Sync
959
960 /* return and re-enable IE and AM */
961 retl
962 wrpr %g0, %o4, %pstate
963 SET_SIZE(clearphys)
964
965 #endif /* lint */
966
967
968 #if defined(lint)
969 /*
970 * Jalapeno Ecache displacement flush the specified line from the E$
971 *
972 * Register usage:
973 * %o0 - 64 bit physical address for flushing
974 * %o1 - Ecache set size
975 */
976 /*ARGSUSED*/
977 void
978 ecache_flush_line(uint64_t flushaddr, int ec_set_size)
979 {
980 }
981 #else /* lint */
982 ENTRY(ecache_flush_line)
983
984 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
985 CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_1);
986 JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
987 ecache_flush_line_1:
988 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
989
990 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
991
992 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
993 CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_2);
994 JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
995 ecache_flush_line_2:
996 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
997
998 retl
999 nop
1000 SET_SIZE(ecache_flush_line)
1001 #endif /* lint */
1002
1003
1004 /*
1005 * Perform necessary cpu workaround to ensure jbus ordering.
1006 * Called only from Fire systems.
1007 * CPU's internal "invalidate FIFOs" are flushed.
1008 */
1009
1010 #if defined(lint)
1011 void
1012 jbus_stst_order()
1013 {}
1014 #else /* lint */
1015
1016 #define VIS_BLOCKSIZE 64
1017
1018 .seg ".data"
1019 .align VIS_BLOCKSIZE
1020 .type sync_buf, #object
1021 sync_buf:
1022 .skip VIS_BLOCKSIZE
1023 .size sync_buf, VIS_BLOCKSIZE
1024
1025 ENTRY(jbus_stst_order)
1026 set sync_buf, %o1
1027
1028 rd %fprs, %o2 ! %o2 = saved fprs
1029 or %o2, FPRS_FEF, %o3
1030 wr %g0, %o3, %fprs ! make sure fp is enabled
1031 stda %d0, [%o1]ASI_BLK_COMMIT_P
1032 wr %o2, 0, %fprs ! restore fprs
1033
1034 retl
1035 membar #Sync
1036 SET_SIZE(jbus_stst_order)
1037
1038 #endif /* lint */
1039
1040 #if defined(lint)
1041 /*
1042 * This routine will not be called in Jalapeno systems.
1043 */
1044 void
1045 flush_ipb(void)
1046 { return; }
1047
1048 #else /* lint */
1049
1050 ENTRY(flush_ipb)
1051 retl
1052 nop
1053 SET_SIZE(flush_ipb)
1054
1055 #endif /* lint */
|
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 *
26 * Assembly code support for the jalapeno module
27 */
28
29 #include "assym.h"
30
31 #include <sys/asm_linkage.h>
32 #include <sys/mmu.h>
33 #include <vm/hat_sfmmu.h>
34 #include <sys/machparam.h>
35 #include <sys/machcpuvar.h>
36 #include <sys/machthread.h>
37 #include <sys/machtrap.h>
38 #include <sys/privregs.h>
39 #include <sys/asm_linkage.h>
40 #include <sys/trap.h>
41 #include <sys/cheetahregs.h>
42 #include <sys/us3_module.h>
43 #include <sys/xc_impl.h>
44 #include <sys/intreg.h>
45 #include <sys/async.h>
46 #include <sys/clock.h>
47 #include <sys/cheetahasm.h>
48
49 #ifdef TRAPTRACE
50 #include <sys/traptrace.h>
51 #endif /* TRAPTRACE */
52
53 /* BEGIN CSTYLED */
54
55 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
56
57 #define CHK_JP_ERRATA85_ENABLED(scr, label) \
58 ASM_LD(scr, jp_errata_85_active); \
59 cmp scr, 1; \
60 bne %icc, label; \
61 nop
62
63 #define SET_64BIT_PA(dest, scr, hi32, lo32) \
64 set hi32, scr; \
65 sllx scr, 32, scr; \
66 sethi %hi(lo32), dest; \
67 or dest, %lo(lo32), dest; \
68 or scr, dest, dest
69
70 /*
71 * Macro to trigger Jalapeno/Tomatillo speed change
72 * j_chng_pa - scratch register
301 set JP_ECACHE_IDX_DISP_FLUSH, scr2; \
302 or scr2, scr1, scr2; \
303 sub ec_set_size, 1, scr1; \
304 and physaddr, scr1, scr1; \
305 or scr2, scr1, scr1; \
306 ECACHE_REFLUSH_LINE(ec_set_size, scr1, scr2)
307
308 /*
309 * Macro for getting ecache size from cpunodes structure
310 * scr1: Scratch, ecache size returned in this
311 * scr2: Scratch
312 */
313 #define GET_ECACHE_SIZE(scr1, scr2) \
314 CPU_INDEX(scr1, scr2); \
315 mulx scr1, CPU_NODE_SIZE, scr1; \
316 set cpunodes + ECACHE_SIZE, scr2; \
317 ld [scr1 + scr2], scr1
318
319 /* END CSTYLED */
320
321 /*
322 * Ship mondo to aid using implicit busy/nack pair (bn ignored)
323 */
324 ENTRY_NP(shipit)
325 sll %o0, IDCR_PID_SHIFT, %g1 ! IDCR<18:14> = agent id
326 or %g1, IDCR_OFFSET, %g1 ! IDCR<13:0> = 0x70
327 stxa %g0, [%g1]ASI_INTR_DISPATCH ! interrupt vector dispatch
328 membar #Sync
329 retl
330 nop
331 SET_SIZE(shipit)
332
333
334 /*
335 * flush_ecache:
336 * %o0 - 64 bit physical address
337 * %o1 - ecache size
338 * %o2 - ecache linesize
339 */
340
341 ENTRY(flush_ecache)
342 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
343 CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_1);
344 JP_FORCE_FULL_SPEED(%o3, %g1, %g2, %g3); /* %o3: saved speed */
345 flush_ecache_1:
346 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
347
348 /*
349 * Flush the entire Ecache using displacement flush.
350 */
351 ECACHE_FLUSHALL(%o1, %o2, %o0, %o4)
352
353 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
354 CHK_JP_ERRATA85_ENABLED(%g1, flush_ecache_2);
355 JP_RESTORE_SPEED(%o3, %g1, %g2, %g3); /* %o3: saved speed */
356 flush_ecache_2:
357 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
358
359 retl
360 nop
361 SET_SIZE(flush_ecache)
362
363
364 .section ".text"
365 .align 64
366 ENTRY_NP(fast_ecc_err)
367
368 /*
369 * Turn off CEEN and NCEEN.
370 */
371 ldxa [%g0]ASI_ESTATE_ERR, %g3
372 andn %g3, EN_REG_NCEEN + EN_REG_CEEN, %g4
373 stxa %g4, [%g0]ASI_ESTATE_ERR
374 membar #Sync ! membar sync required
375
376 /*
377 * Do the CPU log out capture.
378 * %g3 = "failed?" return value.
379 * %g2 = Input = AFAR. Output the clo_flags info which is passed
380 * into this macro via %g4. Output only valid if cpu_private
381 * struct has not been initialized.
382 * CHPR_FECCTL0_LOGOUT = cpu logout structure offset input
383 * %g4 = Trap information stored in the cpu logout flags field
474 * Otherwise, if the logout structure was busy but we have not
475 * nested more times than our maximum value, then we simply
476 * issue a retry. Our TL=0 trap handler code will check and
477 * clear the AFSR after it is done logging what is currently
478 * in the logout struct and handle this event at that time.
479 */
480 retry
481 8:
482 /*
483 * Call cpu_fast_ecc_error via systrap at PIL 14 unless we're
484 * already at PIL 15.
485 */
486 set cpu_fast_ecc_error, %g1
487 rdpr %pil, %g4
488 cmp %g4, PIL_14
489 ba sys_trap
490 movl %icc, PIL_14, %g4
491
492 SET_SIZE(fast_ecc_err)
493
494
495 /*
496 * Fast ECC error at TL>0 handler
497 * We get here via trap 70 at TL>0->Software trap 0 at TL>0. We enter
498 * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
499 * For a complete description of the Fast ECC at TL>0 handling see the
500 * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
501 * us3_common_asm.s
502 */
503
504 .section ".text"
505 .align 64
506 ENTRY_NP(fast_ecc_tl1_err)
507
508 /*
509 * This macro turns off the D$/I$ if they are on and saves their
510 * original state in ch_err_tl1_tmp, saves all the %g registers in the
511 * ch_err_tl1_data structure, updates the ch_err_tl1_flags and saves
512 * the %tpc in ch_err_tl1_tpc. At the end of this macro, %g1 will
513 * point to the ch_err_tl1_data structure and the original D$/I$ state
514 * will be saved in ch_err_tl1_tmp. All %g registers except for %g1
515 * will be available.
516 */
517 CH_ERR_TL1_FECC_ENTER;
518
519 /*
520 * Get the diagnostic logout data. %g4 must be initialized to
521 * current CEEN state, %g5 must point to logout structure in
522 * ch_err_tl1_data_t. %g3 will contain the nesting count upon
523 * return.
707 sllx %g4, C_AFSR_WDU_SHIFT, %g4
708 btst %g4, %g3 ! WDU in original or current AFSR?
709 bnz %xcc, fecc_tl1_err
710 nop
711
712 6:
713 /*
714 * We fall into this macro if we've successfully logged the error in
715 * the ch_err_tl1_data structure and want the PIL15 softint to pick
716 * it up and log it. %g1 must point to the ch_err_tl1_data structure.
717 * Restores the %g registers and issues retry.
718 */
719 CH_ERR_TL1_EXIT;
720 /*
721 * Establish panic exit label.
722 */
723 CH_ERR_TL1_PANIC_EXIT(fecc_tl1_err);
724
725 SET_SIZE(fast_ecc_tl1_err)
726
727
728 ENTRY(get_jbus_config)
729 ldxa [%g0]ASI_JBUS_CONFIG, %o0
730 retl
731 nop
732 SET_SIZE(get_jbus_config)
733
734 ENTRY(set_jbus_config)
735 stxa %o0, [%g0]ASI_JBUS_CONFIG
736 membar #Sync
737 retl
738 nop
739 SET_SIZE(set_jbus_config)
740
741
742 ENTRY(get_mcu_ctl_reg1)
743 ldxa [%g0]ASI_MCU_CTRL, %o0 ! MCU control reg1 is at offset 0
744 retl
745 nop
746 SET_SIZE(get_mcu_ctl_reg1)
747
748
749 ENTRY(set_mcu_ctl_reg1)
750 stxa %o0, [%g0]ASI_MCU_CTRL ! MCU control reg1 is at offset 0
751 membar #Sync
752 retl
753 nop
754 SET_SIZE(set_mcu_ctl_reg1)
755
756
757 /*
758 * scrubphys - Pass in the aligned physical memory address
759 * that you want to scrub, along with the ecache set size.
760 *
761 * 1) Displacement flush the E$ line corresponding to %addr.
762 * The first ldxa guarantees that the %addr is no longer in
763 * M, O, or E (goes to I or S (if instruction fetch also happens).
764 * 2) "Write" the data using a CAS %addr,%g0,%g0.
765 * The casxa guarantees a transition from I to M or S to M.
766 * 3) Displacement flush the E$ line corresponding to %addr.
767 * The second ldxa pushes the M line out of the ecache, into the
768 * writeback buffers, on the way to memory.
769 * 4) The "membar #Sync" pushes the cache line out of the writeback
770 * buffers onto the bus, on the way to dram finally.
771 *
772 * This is a modified version of the algorithm suggested by Gary Lauterbach.
773 * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
774 * as modified, but then we found out that for spitfire, if it misses in the
775 * E$ it will probably install as an M, but if it hits in the E$, then it
776 * will stay E, if the store doesn't happen. So the first displacement flush
777 * should ensure that the CAS will miss in the E$. Arrgh.
778 */
779 ENTRY(scrubphys)
780 rdpr %pstate, %o4
781 andn %o4, PSTATE_IE | PSTATE_AM, %o5
782 wrpr %o5, %g0, %pstate ! clear IE, AM bits
783
784 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
785 CHK_JP_ERRATA85_ENABLED(%g1, scrubphys_1);
786 JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
787 scrubphys_1:
788 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
789
790 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
791 casxa [%o0]ASI_MEM, %g0, %g0
792 ECACHE_REFLUSH_LINE(%o1, %o2, %o3)
793
794 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
795 CHK_JP_ERRATA85_ENABLED(%g1, scrubphys_2);
796 JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
797 scrubphys_2:
798 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
799
800 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
801
802 retl
803 membar #Sync ! move the data out of the load buffer
804 SET_SIZE(scrubphys)
805
806 /*
807 * clearphys - Pass in the physical memory address of the checkblock
808 * that you want to push out, cleared with a recognizable pattern,
809 * from the ecache.
810 *
811 * To ensure that the ecc gets recalculated after the bad data is cleared,
812 * we must write out enough data to fill the w$ line (64 bytes). So we read
813 * in an entire ecache subblock's worth of data, and write it back out.
814 * Then we overwrite the 16 bytes of bad data with the pattern.
815 */
816 ENTRY(clearphys)
817 /* turn off IE, AM bits */
818 rdpr %pstate, %o4
819 andn %o4, PSTATE_IE | PSTATE_AM, %o5
820 wrpr %o5, %g0, %pstate
821
822 /* turn off NCEEN */
823 ldxa [%g0]ASI_ESTATE_ERR, %o5
824 andn %o5, EN_REG_NCEEN, %o3
825 stxa %o3, [%g0]ASI_ESTATE_ERR
826 membar #Sync
827
828 /* align address passed with 64 bytes subblock size */
829 mov CH_ECACHE_SUBBLK_SIZE, %o2
830 andn %o0, (CH_ECACHE_SUBBLK_SIZE - 1), %g1
831
832 /* move the good data into the W$ */
833 1:
834 subcc %o2, 8, %o2
835 ldxa [%g1 + %o2]ASI_MEM, %g2
855 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
856 CHK_JP_ERRATA85_ENABLED(%g1, clearphys_2);
857 JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
858 clearphys_2:
859 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
860
861 /* clear the AFSR */
862 ldxa [%g0]ASI_AFSR, %o1
863 stxa %o1, [%g0]ASI_AFSR
864 membar #Sync
865
866 /* turn NCEEN back on */
867 stxa %o5, [%g0]ASI_ESTATE_ERR
868 membar #Sync
869
870 /* return and re-enable IE and AM */
871 retl
872 wrpr %g0, %o4, %pstate
873 SET_SIZE(clearphys)
874
875
876 /*
877 * Jalapeno Ecache displacement flush the specified line from the E$
878 *
879 * Register usage:
880 * %o0 - 64 bit physical address for flushing
881 * %o1 - Ecache set size
882 */
883 ENTRY(ecache_flush_line)
884
885 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
886 CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_1);
887 JP_FORCE_FULL_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
888 ecache_flush_line_1:
889 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
890
891 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
892
893 #if defined(JALAPENO) && defined(JALAPENO_ERRATA_85)
894 CHK_JP_ERRATA85_ENABLED(%g1, ecache_flush_line_2);
895 JP_RESTORE_SPEED(%o5, %g1, %g2, %g3) /* %o5: saved speed */
896 ecache_flush_line_2:
897 #endif /* JALAPENO && JALAPENO_ERRATA_85 */
898
899 retl
900 nop
901 SET_SIZE(ecache_flush_line)
902
903
904 /*
905 * Perform necessary cpu workaround to ensure jbus ordering.
906 * Called only from Fire systems.
907 * CPU's internal "invalidate FIFOs" are flushed.
908 */
909
910 #define VIS_BLOCKSIZE 64
911
912 .seg ".data"
913 .align VIS_BLOCKSIZE
914 .type sync_buf, #object
915 sync_buf:
916 .skip VIS_BLOCKSIZE
917 .size sync_buf, VIS_BLOCKSIZE
918
919 ENTRY(jbus_stst_order)
920 set sync_buf, %o1
921
922 rd %fprs, %o2 ! %o2 = saved fprs
923 or %o2, FPRS_FEF, %o3
924 wr %g0, %o3, %fprs ! make sure fp is enabled
925 stda %d0, [%o1]ASI_BLK_COMMIT_P
926 wr %o2, 0, %fprs ! restore fprs
927
928 retl
929 membar #Sync
930 SET_SIZE(jbus_stst_order)
931
932 /*
933 * This routine will not be called in Jalapeno systems.
934 */
935 ENTRY(flush_ipb)
936 retl
937 nop
938 SET_SIZE(flush_ipb)
939
|