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--- old/usr/src/uts/sun4u/cpu/us3_cheetah_asm.s
+++ new/usr/src/uts/sun4u/cpu/us3_cheetah_asm.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License, Version 1.0 only
6 6 * (the "License"). You may not use this file except in compliance
7 7 * with the License.
8 8 *
9 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 10 * or http://www.opensolaris.org/os/licensing.
11 11 * See the License for the specific language governing permissions
12 12 * and limitations under the License.
13 13 *
14 14 * When distributing Covered Code, include this CDDL HEADER in each
15 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 16 * If applicable, add the following below this CDDL HEADER, with the
17 17 * fields enclosed by brackets "[]" replaced with your own identifying
18 18 * information: Portions Copyright [yyyy] [name of copyright owner]
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19 19 *
20 20 * CDDL HEADER END
21 21 */
22 22 /*
23 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 *
26 26 * Assembly code support for the Cheetah module
27 27 */
28 28
29 -#pragma ident "%Z%%M% %I% %E% SMI"
30 -
31 -#if !defined(lint)
32 29 #include "assym.h"
33 -#endif /* lint */
34 30
35 31 #include <sys/asm_linkage.h>
36 32 #include <sys/mmu.h>
37 33 #include <vm/hat_sfmmu.h>
38 34 #include <sys/machparam.h>
39 35 #include <sys/machcpuvar.h>
40 36 #include <sys/machthread.h>
41 37 #include <sys/machtrap.h>
42 38 #include <sys/privregs.h>
43 39 #include <sys/asm_linkage.h>
44 40 #include <sys/trap.h>
45 41 #include <sys/cheetahregs.h>
46 42 #include <sys/us3_module.h>
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47 43 #include <sys/xc_impl.h>
48 44 #include <sys/intreg.h>
49 45 #include <sys/async.h>
50 46 #include <sys/clock.h>
51 47 #include <sys/cheetahasm.h>
52 48
53 49 #ifdef TRAPTRACE
54 50 #include <sys/traptrace.h>
55 51 #endif /* TRAPTRACE */
56 52
57 -#if !defined(lint)
58 -
59 53 /* BEGIN CSTYLED */
60 54
61 55 /*
62 56 * Cheetah version to flush an Ecache line by index (aliased address)
63 57 */
64 58 #define ECACHE_REFLUSH_LINE(ecache_size, alias_address, scr2) \
65 59 ldxa [alias_address]ASI_MEM, %g0
66 60
67 61 #define ECACHE_FLUSH_LINE(physaddr, ecache_size, scr1, scr2) \
68 62 xor physaddr, ecache_size, scr1; \
69 63 add ecache_size, ecache_size, scr2; \
70 64 sub scr2, 1, scr2; \
71 65 and scr1, scr2, scr1; \
72 66 ASM_LDX(scr2, ecache_flushaddr); \
73 67 add scr1, scr2, scr1; \
74 68 ECACHE_REFLUSH_LINE(ecache_size, scr1, scr2)
75 69
76 70 /* END CSTYLED */
77 71
78 -#endif /* !lint */
79 72
80 -
81 73 /*
82 74 * Fast ECC error at TL>0 handler
83 75 * We get here via trap 70 at TL>0->Software trap 0 at TL>0. We enter
84 76 * this routine with %g1 and %g2 already saved in %tpc, %tnpc and %tstate.
85 77 * For a complete description of the Fast ECC at TL>0 handling see the
86 78 * comment block "Cheetah/Cheetah+ Fast ECC at TL>0 trap strategy" in
87 79 * us3_common_asm.s
88 80 */
89 -#if defined(lint)
90 81
91 -void
92 -fast_ecc_tl1_err(void)
93 -{}
94 -
95 -#else /* lint */
96 -
97 82 .section ".text"
98 83 .align 64
99 84 ENTRY_NP(fast_ecc_tl1_err)
100 85
101 86 /*
102 87 * This macro turns off the D$/I$ if they are on and saves their
103 88 * original state in ch_err_tl1_tmp, saves all the %g registers in the
104 89 * ch_err_tl1_data structure, updates the ch_err_tl1_flags and saves
105 90 * the %tpc in ch_err_tl1_tpc. At the end of this macro, %g1 will
106 91 * point to the ch_err_tl1_data structure and the original D$/I$ state
107 92 * will be saved in ch_err_tl1_tmp. All %g registers except for %g1
108 93 * will be available.
109 94 */
110 95 CH_ERR_TL1_FECC_ENTER;
111 96
112 97 /*
113 98 * Get the diagnostic logout data. %g4 must be initialized to
114 99 * current CEEN state, %g5 must point to logout structure in
115 100 * ch_err_tl1_data_t. %g3 will contain the nesting count upon
116 101 * return.
117 102 */
118 103 ldxa [%g0]ASI_ESTATE_ERR, %g4
119 104 and %g4, EN_REG_CEEN, %g4
120 105 add %g1, CH_ERR_TL1_LOGOUT, %g5
121 106 DO_TL1_CPU_LOGOUT(%g3, %g2, %g4, %g5, %g6, %g3, %g4)
122 107
123 108 /*
124 109 * If the logout nesting count is exceeded, we're probably
125 110 * not making any progress, try to panic instead.
126 111 */
127 112 cmp %g3, CLO_NESTING_MAX
128 113 bge fecc_tl1_err
129 114 nop
130 115
131 116 /*
132 117 * Save the current CEEN and NCEEN state in %g7 and turn them off
133 118 * before flushing the Ecache.
134 119 */
135 120 ldxa [%g0]ASI_ESTATE_ERR, %g7
136 121 andn %g7, EN_REG_CEEN | EN_REG_NCEEN, %g5
137 122 stxa %g5, [%g0]ASI_ESTATE_ERR
138 123 membar #Sync
139 124
140 125 /*
141 126 * Flush the Ecache, using the largest possible cache size with the
142 127 * smallest possible line size since we can't get the actual sizes
143 128 * from the cpu_node due to DTLB misses.
144 129 */
145 130 set CH_ECACHE_8M_SIZE, %g4
146 131 set CH_ECACHE_MIN_LSIZE, %g5
147 132
148 133 /*
149 134 * Use a different flush address to avoid recursion if the error
150 135 * exists in ecache_flushaddr.
151 136 */
152 137 ASM_LDX(%g6, ecache_tl1_flushaddr)
153 138 cmp %g6, -1 ! check if address is valid
154 139 be %xcc, fecc_tl1_err
155 140 nop
156 141 CH_ECACHE_FLUSHALL(%g4, %g5, %g6)
157 142
158 143 /*
159 144 * Restore CEEN and NCEEN to the previous state.
160 145 */
161 146 stxa %g7, [%g0]ASI_ESTATE_ERR
162 147 membar #Sync
163 148
164 149 /*
165 150 * If we turned off the D$, then flush it and turn it back on.
166 151 */
167 152 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
168 153 andcc %g3, CH_ERR_TSTATE_DC_ON, %g0
169 154 bz %xcc, 3f
170 155 nop
171 156
172 157 /*
173 158 * Flush the D$.
174 159 */
175 160 ASM_LD(%g4, dcache_size)
176 161 ASM_LD(%g5, dcache_linesize)
177 162 CH_DCACHE_FLUSHALL(%g4, %g5, %g6)
178 163
179 164 /*
180 165 * Turn the D$ back on.
181 166 */
182 167 ldxa [%g0]ASI_DCU, %g3
183 168 or %g3, DCU_DC, %g3
184 169 stxa %g3, [%g0]ASI_DCU
185 170 membar #Sync
186 171 3:
187 172 /*
188 173 * If we turned off the I$, then flush it and turn it back on.
189 174 */
190 175 ldxa [%g1 + CH_ERR_TL1_TMP]%asi, %g3
191 176 andcc %g3, CH_ERR_TSTATE_IC_ON, %g0
192 177 bz %xcc, 4f
193 178 nop
194 179
195 180 /*
196 181 * Flush the I$.
197 182 */
198 183 ASM_LD(%g4, icache_size)
199 184 ASM_LD(%g5, icache_linesize)
200 185 CH_ICACHE_FLUSHALL(%g4, %g5, %g6, %g3)
201 186
202 187 /*
203 188 * Turn the I$ back on. Changing DCU_IC requires flush.
204 189 */
205 190 ldxa [%g0]ASI_DCU, %g3
206 191 or %g3, DCU_IC, %g3
207 192 stxa %g3, [%g0]ASI_DCU
208 193 flush %g0
209 194 4:
210 195
211 196 #ifdef TRAPTRACE
212 197 /*
213 198 * Get current trap trace entry physical pointer.
214 199 */
215 200 CPU_INDEX(%g6, %g5)
216 201 sll %g6, TRAPTR_SIZE_SHIFT, %g6
217 202 set trap_trace_ctl, %g5
218 203 add %g6, %g5, %g6
219 204 ld [%g6 + TRAPTR_LIMIT], %g5
220 205 tst %g5
221 206 be %icc, skip_traptrace
222 207 nop
223 208 ldx [%g6 + TRAPTR_PBASE], %g5
224 209 ld [%g6 + TRAPTR_OFFSET], %g4
225 210 add %g5, %g4, %g5
226 211
227 212 /*
228 213 * Create trap trace entry.
229 214 */
230 215 rd %asi, %g7
231 216 wr %g0, TRAPTR_ASI, %asi
232 217 rd STICK, %g4
233 218 stxa %g4, [%g5 + TRAP_ENT_TICK]%asi
234 219 rdpr %tl, %g4
235 220 stha %g4, [%g5 + TRAP_ENT_TL]%asi
236 221 rdpr %tt, %g4
237 222 stha %g4, [%g5 + TRAP_ENT_TT]%asi
238 223 rdpr %tpc, %g4
239 224 stna %g4, [%g5 + TRAP_ENT_TPC]%asi
240 225 rdpr %tstate, %g4
241 226 stxa %g4, [%g5 + TRAP_ENT_TSTATE]%asi
242 227 stna %sp, [%g5 + TRAP_ENT_SP]%asi
243 228 stna %g0, [%g5 + TRAP_ENT_TR]%asi
244 229 wr %g0, %g7, %asi
245 230 ldxa [%g1 + CH_ERR_TL1_SDW_AFAR]%asi, %g3
246 231 ldxa [%g1 + CH_ERR_TL1_SDW_AFSR]%asi, %g4
247 232 wr %g0, TRAPTR_ASI, %asi
248 233 stna %g3, [%g5 + TRAP_ENT_F1]%asi
249 234 stna %g4, [%g5 + TRAP_ENT_F2]%asi
250 235 wr %g0, %g7, %asi
251 236 ldxa [%g1 + CH_ERR_TL1_AFAR]%asi, %g3
252 237 ldxa [%g1 + CH_ERR_TL1_AFSR]%asi, %g4
253 238 wr %g0, TRAPTR_ASI, %asi
254 239 stna %g3, [%g5 + TRAP_ENT_F3]%asi
255 240 stna %g4, [%g5 + TRAP_ENT_F4]%asi
256 241 wr %g0, %g7, %asi
257 242
258 243 /*
259 244 * Advance trap trace pointer.
260 245 */
261 246 ld [%g6 + TRAPTR_OFFSET], %g5
262 247 ld [%g6 + TRAPTR_LIMIT], %g4
263 248 st %g5, [%g6 + TRAPTR_LAST_OFFSET]
264 249 add %g5, TRAP_ENT_SIZE, %g5
265 250 sub %g4, TRAP_ENT_SIZE, %g4
266 251 cmp %g5, %g4
267 252 movge %icc, 0, %g5
268 253 st %g5, [%g6 + TRAPTR_OFFSET]
269 254 skip_traptrace:
270 255 #endif /* TRAPTRACE */
271 256
272 257 /*
273 258 * If nesting count is not zero, skip all the AFSR/AFAR
274 259 * handling and just do the necessary cache-flushing.
275 260 */
276 261 ldxa [%g1 + CH_ERR_TL1_NEST_CNT]%asi, %g2
277 262 brnz %g2, 6f
278 263 nop
279 264
280 265 /*
281 266 * If a UCU followed by a WDU has occurred go ahead and panic
282 267 * since a UE will occur (on the retry) before the UCU and WDU
283 268 * messages are enqueued.
284 269 */
285 270 ldxa [%g1 + CH_ERR_TL1_AFSR]%asi, %g3
286 271 set 1, %g4
287 272 sllx %g4, C_AFSR_UCU_SHIFT, %g4
288 273 btst %g4, %g3 ! UCU in original AFSR?
289 274 bz %xcc, 6f
290 275 nop
291 276 ldxa [%g0]ASI_AFSR, %g4 ! current AFSR
292 277 or %g3, %g4, %g3 ! %g3 = original + current AFSR
293 278 set 1, %g4
294 279 sllx %g4, C_AFSR_WDU_SHIFT, %g4
295 280 btst %g4, %g3 ! WDU in original or current AFSR?
296 281 bnz %xcc, fecc_tl1_err
297 282 nop
298 283
299 284 6:
300 285 /*
301 286 * We fall into this macro if we've successfully logged the error in
302 287 * the ch_err_tl1_data structure and want the PIL15 softint to pick
303 288 * it up and log it. %g1 must point to the ch_err_tl1_data structure.
304 289 * Restores the %g registers and issues retry.
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305 290 */
306 291 CH_ERR_TL1_EXIT;
307 292
308 293 /*
309 294 * Establish panic exit label.
310 295 */
311 296 CH_ERR_TL1_PANIC_EXIT(fecc_tl1_err);
312 297
313 298 SET_SIZE(fast_ecc_tl1_err)
314 299
315 -#endif /* lint */
316 300
317 -
318 -#if defined(lint)
319 301 /*
320 302 * scrubphys - Pass in the aligned physical memory address
321 303 * that you want to scrub, along with the ecache set size.
322 304 *
323 305 * 1) Displacement flush the E$ line corresponding to %addr.
324 306 * The first ldxa guarantees that the %addr is no longer in
325 307 * M, O, or E (goes to I or S (if instruction fetch also happens).
326 308 * 2) "Write" the data using a CAS %addr,%g0,%g0.
327 309 * The casxa guarantees a transition from I to M or S to M.
328 310 * 3) Displacement flush the E$ line corresponding to %addr.
329 311 * The second ldxa pushes the M line out of the ecache, into the
330 312 * writeback buffers, on the way to memory.
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331 313 * 4) The "membar #Sync" pushes the cache line out of the writeback
332 314 * buffers onto the bus, on the way to dram finally.
333 315 *
334 316 * This is a modified version of the algorithm suggested by Gary Lauterbach.
335 317 * In theory the CAS %addr,%g0,%g0 is supposed to mark the addr's cache line
336 318 * as modified, but then we found out that for spitfire, if it misses in the
337 319 * E$ it will probably install as an M, but if it hits in the E$, then it
338 320 * will stay E, if the store doesn't happen. So the first displacement flush
339 321 * should ensure that the CAS will miss in the E$. Arrgh.
340 322 */
341 -/* ARGSUSED */
342 -void
343 -scrubphys(uint64_t paddr, int ecache_set_size)
344 -{}
345 -
346 -#else /* lint */
347 323 ENTRY(scrubphys)
348 324 rdpr %pstate, %o4
349 325 andn %o4, PSTATE_IE | PSTATE_AM, %o5
350 326 wrpr %o5, %g0, %pstate ! clear IE, AM bits
351 327
352 328 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
353 329 casxa [%o0]ASI_MEM, %g0, %g0
354 330 ECACHE_REFLUSH_LINE(%o1, %o2, %o3)
355 331
356 332 wrpr %g0, %o4, %pstate ! restore earlier pstate register value
357 333
358 334 retl
359 335 membar #Sync ! move the data out of the load buffer
360 336 SET_SIZE(scrubphys)
361 337
362 -#endif /* lint */
363 338
364 -
365 -#if defined(lint)
366 - /*
339 +/*
367 340 * clearphys - Pass in the physical memory address of the checkblock
368 341 * that you want to push out, cleared with a recognizable pattern,
369 342 * from the ecache.
370 343 *
371 344 * To ensure that the ecc gets recalculated after the bad data is cleared,
372 345 * we must write out enough data to fill the w$ line (64 bytes). So we read
373 346 * in an entire ecache subblock's worth of data, and write it back out.
374 347 * Then we overwrite the 16 bytes of bad data with the pattern.
375 348 */
376 -/* ARGSUSED */
377 -void
378 -clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize)
379 -{
380 -}
381 -
382 -#else /* lint */
383 349 ENTRY(clearphys)
384 350 /* turn off IE, AM bits */
385 351 rdpr %pstate, %o4
386 352 andn %o4, PSTATE_IE | PSTATE_AM, %o5
387 353 wrpr %o5, %g0, %pstate
388 354
389 355 /* turn off NCEEN */
390 356 ldxa [%g0]ASI_ESTATE_ERR, %o5
391 357 andn %o5, EN_REG_NCEEN, %o3
392 358 stxa %o3, [%g0]ASI_ESTATE_ERR
393 359 membar #Sync
394 360
395 361 /* align address passed with 64 bytes subblock size */
396 362 mov CH_ECACHE_SUBBLK_SIZE, %o2
397 363 andn %o0, (CH_ECACHE_SUBBLK_SIZE - 1), %g1
398 364
399 365 /* move the good data into the W$ */
400 366 1:
401 367 subcc %o2, 8, %o2
402 368 ldxa [%g1 + %o2]ASI_MEM, %g2
403 369 bge 1b
404 370 stxa %g2, [%g1 + %o2]ASI_MEM
405 371
406 372 /* now overwrite the bad data */
407 373 setx 0xbadecc00badecc01, %g1, %g2
408 374 stxa %g2, [%o0]ASI_MEM
409 375 mov 8, %g1
410 376 stxa %g2, [%o0 + %g1]ASI_MEM
411 377
412 378 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
413 379 casxa [%o0]ASI_MEM, %g0, %g0
414 380 ECACHE_REFLUSH_LINE(%o1, %o2, %o3)
415 381
416 382 /* clear the AFSR */
417 383 ldxa [%g0]ASI_AFSR, %o1
418 384 stxa %o1, [%g0]ASI_AFSR
419 385 membar #Sync
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420 386
421 387 /* turn NCEEN back on */
422 388 stxa %o5, [%g0]ASI_ESTATE_ERR
423 389 membar #Sync
424 390
425 391 /* return and re-enable IE and AM */
426 392 retl
427 393 wrpr %g0, %o4, %pstate
428 394 SET_SIZE(clearphys)
429 395
430 -#endif /* lint */
431 396
432 -
433 -#if defined(lint)
434 397 /*
435 398 * Cheetah Ecache displacement flush the specified line from the E$
436 399 *
437 400 * Register usage:
438 401 * %o0 - 64 bit physical address for flushing
439 402 * %o1 - Ecache set size
440 403 */
441 -/*ARGSUSED*/
442 -void
443 -ecache_flush_line(uint64_t flushaddr, int ec_set_size)
444 -{
445 -}
446 -#else /* lint */
447 404 ENTRY(ecache_flush_line)
448 405
449 406 ECACHE_FLUSH_LINE(%o0, %o1, %o2, %o3)
450 407
451 408 retl
452 409 nop
453 410 SET_SIZE(ecache_flush_line)
454 -#endif /* lint */
455 411
456 -
457 -#if defined(lint)
458 412 /*
459 413 * This routine will not be called in Cheetah systems.
460 414 */
461 -void
462 -flush_ipb(void)
463 -{ return; }
464 -
465 -#else /* lint */
466 -
467 415 ENTRY(flush_ipb)
468 416 retl
469 417 nop
470 418 SET_SIZE(flush_ipb)
471 419
472 -#endif /* lint */
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