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restore sparc comments
de-linting of .s files

*** 21,35 **** /* * Copyright 2008 Sun Microsystems, Inc. All rights reserved. * Use is subject to license terms. */ - #pragma ident "%Z%%M% %I% %E% SMI" - - #if !defined(lint) #include "assym.h" - #endif /* lint */ #include <sys/asm_linkage.h> #include <sys/mmu.h> #include <vm/hat_sfmmu.h> #include <sys/machparam.h> --- 21,31 ----
*** 46,57 **** #ifdef TRAPTRACE #include <sys/traptrace.h> #endif /* TRAPTRACE */ - #ifndef lint - /* BEGIN CSTYLED */ #define DCACHE_FLUSHPAGE(arg1, arg2, tmp1, tmp2, tmp3) \ ldxa [%g0]ASI_LSU, tmp1 ;\ btst LSU_DC, tmp1 /* is dcache enabled? */ ;\ bz,pn %icc, 1f ;\ --- 42,51 ----
*** 345,450 **** #define HB_PHYS_FLUSH_CNT 10 /* #loads to flush specific paddr */ #endif /* HUMMINGBIRD */ /* END CSTYLED */ - #endif /* !lint */ - /* * Spitfire MMU and Cache operations. */ - #if defined(lint) - - /*ARGSUSED*/ - void - vtag_flushpage(caddr_t vaddr, uint64_t sfmmup) - {} - - /*ARGSUSED*/ - void - vtag_flushall(void) - {} - - /*ARGSUSED*/ - void - vtag_flushall_uctxs(void) - {} - - /*ARGSUSED*/ - void - vtag_flushpage_tl1(uint64_t vaddr, uint64_t sfmmup) - {} - - /*ARGSUSED*/ - void - vtag_flush_pgcnt_tl1(uint64_t vaddr, uint64_t sfmmup_pgcnt) - {} - - /*ARGSUSED*/ - void - vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2) - {} - - /*ARGSUSED*/ - void - vac_flushpage(pfn_t pfnum, int vcolor) - {} - - /*ARGSUSED*/ - void - vac_flushpage_tl1(uint64_t pfnum, uint64_t vcolor) - {} - - /*ARGSUSED*/ - void - init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2) - {} - - /*ARGSUSED*/ - void - init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2) - {} - - /*ARGSUSED*/ - void - flush_instr_mem(caddr_t vaddr, size_t len) - {} - - /*ARGSUSED*/ - void - flush_ecache(uint64_t physaddr, size_t size, size_t linesize) - {} - - /*ARGSUSED*/ - void - get_ecache_dtag(uint32_t ecache_idx, uint64_t *ecache_data, - uint64_t *ecache_tag, uint64_t *oafsr, uint64_t *acc_afsr) - {} - - /* ARGSUSED */ - uint64_t - get_ecache_tag(uint32_t id, uint64_t *nafsr, uint64_t *acc_afsr) - { - return ((uint64_t)0); - } - - /* ARGSUSED */ - uint64_t - check_ecache_line(uint32_t id, uint64_t *acc_afsr) - { - return ((uint64_t)0); - } - - /*ARGSUSED*/ - void - kdi_flush_idcache(int dcache_size, int dcache_lsize, - int icache_size, int icache_lsize) - {} - - #else /* lint */ - ENTRY_NP(vtag_flushpage) /* * flush page from the tlb * * %o0 = vaddr --- 339,352 ----
*** 954,1021 **** membar #Sync wrpr %g0, %i5, %pstate ret restore SET_SIZE(get_ecache_dtag) - #endif /* lint */ - #if defined(lint) /* * The ce_err function handles trap type 0x63 (corrected_ECC_error) at tl=0. * Steps: 1. GET AFSR 2. Get AFAR <40:4> 3. Get datapath error status * 4. Clear datapath error bit(s) 5. Clear AFSR error bit * 6. package data in %g2 and %g3 7. call cpu_ce_error vis sys_trap * %g2: [ 52:43 UDB lower | 42:33 UDB upper | 32:0 afsr ] - arg #3/arg #1 * %g3: [ 40:4 afar ] - sys_trap->have_win: arg #4/arg #2 */ - void - ce_err(void) - {} - - void - ce_err_tl1(void) - {} - - - /* - * The async_err function handles trap types 0x0A (instruction_access_error) - * and 0x32 (data_access_error) at TL = 0 and TL > 0. When we branch here, - * %g5 will have the trap type (with 0x200 set if we're at TL > 0). - * - * Steps: 1. Get AFSR 2. Get AFAR <40:4> 3. If not UE error skip UDP registers. - * 4. Else get and clear datapath error bit(s) 4. Clear AFSR error bits - * 6. package data in %g2 and %g3 7. disable all cpu errors, because - * trap is likely to be fatal 8. call cpu_async_error vis sys_trap - * - * %g3: [ 63:53 tt | 52:43 UDB_L | 42:33 UDB_U | 32:0 afsr ] - arg #3/arg #1 - * %g2: [ 40:4 afar ] - sys_trap->have_win: arg #4/arg #2 - */ - void - async_err(void) - {} - - /* - * The clr_datapath function clears any error bits set in the UDB regs. - */ - void - clr_datapath(void) - {} - - /* - * The get_udb_errors() function gets the current value of the - * Datapath Error Registers. - */ - /*ARGSUSED*/ - void - get_udb_errors(uint64_t *udbh, uint64_t *udbl) - { - *udbh = 0; - *udbl = 0; - } - - #else /* lint */ - ENTRY_NP(ce_err) ldxa [%g0]ASI_AFSR, %g3 ! save afsr in g3 ! ! Check for a UE... From Kevin.Normoyle: --- 856,874 ----
*** 1106,1120 **** call panic nop SET_SIZE(ce_trap_tl1) #endif ! ! ! ! async_err is the assembly glue code to get us from the actual trap ! ! into the CPU module's C error handler. Note that we also branch ! ! here from ce_err() above. ! ! ENTRY_NP(async_err) stxa %g0, [%g0]ASI_ESTATE_ERR ! disable ecc and other cpu errors membar #Sync ! membar sync required ldxa [%g0]ASI_AFSR, %g3 ! save afsr in g3 --- 959,985 ---- call panic nop SET_SIZE(ce_trap_tl1) #endif ! /* ! * The async_err function handles trap types 0x0A (instruction_access_error) ! * and 0x32 (data_access_error) at TL = 0 and TL > 0. When we branch here, ! * %g5 will have the trap type (with 0x200 set if we're at TL > 0). ! * ! * Steps: 1. Get AFSR 2. Get AFAR <40:4> 3. If not UE error skip UDP registers. ! * 4. Else get and clear datapath error bit(s) 4. Clear AFSR error bits ! * 6. package data in %g2 and %g3 7. disable all cpu errors, because ! * trap is likely to be fatal 8. call cpu_async_error vis sys_trap ! * ! * %g3: [ 63:53 tt | 52:43 UDB_L | 42:33 UDB_U | 32:0 afsr ] - arg #3/arg #1 ! * %g2: [ 40:4 afar ] - sys_trap->have_win: arg #4/arg #2 ! * ! * async_err is the assembly glue code to get us from the actual trap ! * into the CPU module's C error handler. Note that we also branch ! * here from ce_err() above. ! */ ENTRY_NP(async_err) stxa %g0, [%g0]ASI_ESTATE_ERR ! disable ecc and other cpu errors membar #Sync ! membar sync required ldxa [%g0]ASI_AFSR, %g3 ! save afsr in g3
*** 1184,1193 **** --- 1049,1061 ---- sethi %hi(sys_trap), %g5 jmp %g5 + %lo(sys_trap) ! goto sys_trap sub %g0, 1, %g4 SET_SIZE(dis_err_panic1) + /* + * The clr_datapath function clears any error bits set in the UDB regs. + */ ENTRY(clr_datapath) set P_DER_H, %o4 ! put P_DER_H in o4 ldxa [%o4]ASI_SDB_INTR_R, %o5 ! read sdb upper half into o3 or %g0, 0x3, %o2 ! put 0x3 in o2 sllx %o2, 8, %o2 ! shift o2 to <9:8> sdb
*** 1207,1216 **** --- 1075,1088 ---- 2: retl nop SET_SIZE(clr_datapath) + /* + * The get_udb_errors() function gets the current value of the + * Datapath Error Registers. + */ ENTRY(get_udb_errors) set P_DER_H, %o3 ldxa [%o3]ASI_SDB_INTR_R, %o2 stx %o2, [%o0] set P_DER_L, %o3
*** 1217,1247 **** ldxa [%o3]ASI_SDB_INTR_R, %o2 retl stx %o2, [%o1] SET_SIZE(get_udb_errors) - #endif /* lint */ - - #if defined(lint) /* * The itlb_rd_entry and dtlb_rd_entry functions return the tag portion of the * tte, the virtual address, and the ctxnum of the specified tlb entry. They * should only be used in places where you have no choice but to look at the * tlb itself. * * Note: These two routines are required by the Estar "cpr" loadable module. */ - /*ARGSUSED*/ - void - itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) - {} - - /*ARGSUSED*/ - void - dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) - {} - #else /* lint */ /* * NB - In Spitfire cpus, when reading a tte from the hardware, we * need to clear [42-41] because the general definitions in pte.h * define the PA to be [42-13] whereas Spitfire really uses [40-13]. * When cloning these routines for other cpus the "andn" below is not --- 1089,1106 ----
*** 1284,1313 **** set TAGREAD_CTX_MASK, %o4 andn %g2, %o4, %o5 retl stx %o5, [%o2] SET_SIZE(dtlb_rd_entry) - #endif /* lint */ - #if defined(lint) - - /* - * routines to get and set the LSU register - */ - uint64_t - get_lsu(void) - { - return ((uint64_t)0); - } - - /*ARGSUSED*/ - void - set_lsu(uint64_t lsu) - {} - - #else /* lint */ - ENTRY(set_lsu) stxa %o0, [%g0]ASI_LSU ! store to LSU retl membar #Sync SET_SIZE(set_lsu) --- 1143,1153 ----
*** 1315,1327 **** ENTRY(get_lsu) retl ldxa [%g0]ASI_LSU, %o0 ! load LSU SET_SIZE(get_lsu) - #endif /* lint */ - - #ifndef lint /* * Clear the NPT (non-privileged trap) bit in the %tick * registers. In an effort to make the change in the * tick counter as consistent as possible, we disable * all interrupts while we're changing the registers. We also --- 1155,1164 ----
*** 1456,1490 **** stxa %g1, [%g0]ASI_ESTATE_ERR ! Turn error enable back on membar #Sync retl wrpr %g0, %o5, %pstate SET_SIZE(check_ecache_line) - #endif /* lint */ - #if defined(lint) - uint64_t - read_and_clear_afsr() - { - return ((uint64_t)0); - } - #else /* lint */ ENTRY(read_and_clear_afsr) ldxa [%g0]ASI_AFSR, %o0 retl stxa %o0, [%g0]ASI_AFSR ! clear AFSR SET_SIZE(read_and_clear_afsr) - #endif /* lint */ - #if defined(lint) - /* ARGSUSED */ - void - scrubphys(uint64_t paddr, int ecache_size) - { - } - - #else /* lint */ - /* * scrubphys - Pass in the aligned physical memory address that you want * to scrub, along with the ecache size. * * 1) Displacement flush the E$ line corresponding to %addr. --- 1293,1309 ----
*** 1607,1636 **** retl membar #Sync ! move the data out of the load buffer SET_SIZE(scrubphys) - #endif /* lint */ - - #if defined(lint) - /* * clearphys - Pass in the aligned physical memory address that you want * to push out, as a 64 byte block of zeros, from the ecache zero-filled. * Since this routine does not bypass the ecache, it is possible that * it could generate a UE error while trying to clear the a bad line. * This routine clears and restores the error enable flag. * TBD - Hummingbird may need similar protection */ - /* ARGSUSED */ - void - clearphys(uint64_t paddr, int ecache_size, int ecache_linesize) - { - } - - #else /* lint */ - ENTRY(clearphys) or %o2, %g0, %o3 ! ecache linesize or %o1, %g0, %o2 ! ecache size #ifndef HUMMINGBIRD or %o3, %g0, %o4 ! save ecache linesize --- 1426,1443 ----
*** 1757,1776 **** retl wrpr %g0, %o4, %pstate ! restore earlier pstate register value SET_SIZE(clearphys) - #endif /* lint */ - - #if defined(lint) - /* ARGSUSED */ - void - flushecacheline(uint64_t paddr, int ecache_size) - { - } - - #else /* lint */ /* * flushecacheline - This is a simpler version of scrubphys * which simply does a displacement flush of the line in * question. This routine is mainly used in handling async * errors where we want to get rid of a bad line in ecache. --- 1564,1573 ----
*** 1880,1899 **** #endif /* HUMMINGBIRD */ retl wrpr %g0, %o4, %pstate SET_SIZE(flushecacheline) - #endif /* lint */ - - #if defined(lint) - /* ARGSUSED */ - void - ecache_scrubreq_tl1(uint64_t inum, uint64_t dummy) - { - } - - #else /* lint */ /* * ecache_scrubreq_tl1 is the crosstrap handler called at ecache_calls_a_sec Hz * from the clock CPU. It atomically increments the outstanding request * counter and, if there was not already an outstanding request, * branches to setsoftint_tl1 to enqueue an intr_vec for the given inum. --- 1677,1686 ----
*** 1926,1944 **** ! not reached 1: retry SET_SIZE(ecache_scrubreq_tl1) - #endif /* lint */ - - #if defined(lint) - /*ARGSUSED*/ - void - write_ec_tag_parity(uint32_t id) - {} - #else /* lint */ - /* * write_ec_tag_parity(), which zero's the ecache tag, * marks the state as invalid and writes good parity to the tag. * Input %o1= 32 bit E$ index */ --- 1713,1722 ----
*** 1974,1992 **** membar #Sync retl wrpr %g0, %o5, %pstate SET_SIZE(write_ec_tag_parity) - #endif /* lint */ - - #if defined(lint) - /*ARGSUSED*/ - void - write_hb_ec_tag_parity(uint32_t id) - {} - #else /* lint */ - /* * write_hb_ec_tag_parity(), which zero's the ecache tag, * marks the state as invalid and writes good parity to the tag. * Input %o1= 32 bit E$ index */ --- 1752,1761 ----
*** 2027,2049 **** membar #Sync retl wrpr %g0, %o5, %pstate SET_SIZE(write_hb_ec_tag_parity) - #endif /* lint */ - #define VIS_BLOCKSIZE 64 - #if defined(lint) - - /*ARGSUSED*/ - int - dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain) - { return (0); } - - #else - ENTRY(dtrace_blksuword32) save %sp, -SA(MINFRAME + 4), %sp rdpr %pstate, %l1 andn %l1, PSTATE_IE, %l2 ! disable interrupts to --- 1796,1807 ----
*** 2104,2109 **** call dtrace_blksuword32_err restore SET_SIZE(dtrace_blksuword32) - #endif /* lint */ --- 1862,1866 ----