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          --- old/usr/src/uts/sun4u/cpu/opl_olympus_asm.s
          +++ new/usr/src/uts/sun4u/cpu/opl_olympus_asm.s
↓ open down ↓ 17 lines elided ↑ open up ↑
  18   18   *
  19   19   * CDDL HEADER END
  20   20   */
  21   21  /*
  22   22   * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23   23   * Use is subject to license terms.
  24   24   *
  25   25   * Assembly code support for the Olympus-C module
  26   26   */
  27   27  
  28      -#if !defined(lint)
  29   28  #include "assym.h"
  30      -#endif  /* lint */
  31   29  
  32   30  #include <sys/asm_linkage.h>
  33   31  #include <sys/mmu.h>
  34   32  #include <vm/hat_sfmmu.h>
  35   33  #include <sys/machparam.h>
  36   34  #include <sys/machcpuvar.h>
  37   35  #include <sys/machthread.h>
  38   36  #include <sys/machtrap.h>
  39   37  #include <sys/privregs.h>
  40   38  #include <sys/asm_linkage.h>
↓ open down ↓ 19 lines elided ↑ open up ↑
  60   58   */
  61   59  #define ECACHE_FLUSHALL(arg1, arg2, arg3, tmp1)                         \
  62   60          mov     ASI_L2_CTRL_U2_FLUSH, arg1;                             \
  63   61          mov     ASI_L2_CTRL_RW_ADDR, arg2;                              \
  64   62          stxa    arg1, [arg2]ASI_L2_CTRL
  65   63  
  66   64  /*
  67   65   * SPARC64-VI MMU and Cache operations.
  68   66   */
  69   67  
  70      -#if defined(lint)
  71      -
  72      -/* ARGSUSED */
  73      -void
  74      -vtag_flushpage(caddr_t vaddr, uint64_t sfmmup)
  75      -{}
  76      -
  77      -#else   /* lint */
  78      -
  79   68          ENTRY_NP(vtag_flushpage)
  80   69          /*
  81   70           * flush page from the tlb
  82   71           *
  83   72           * %o0 = vaddr
  84   73           * %o1 = sfmmup
  85   74           */
  86   75          rdpr    %pstate, %o5
  87   76  #ifdef DEBUG
  88   77          PANIC_IF_INTR_DISABLED_PSTR(%o5, opl_di_l3, %g1)
↓ open down ↓ 48 lines elided ↑ open up ↑
 137  126          stxa    %g0, [%o0]ASI_DTLB_DEMAP
 138  127          stxa    %g0, [%o0]ASI_ITLB_DEMAP
 139  128          stxa    %o2, [%o4]ASI_DMMU              /* restore old ctxnum */
 140  129          flush   %o3
 141  130          wrpr    %g0, 0, %tl
 142  131  
 143  132          retl
 144  133          wrpr    %g0, %o5, %pstate               /* enable interrupts */
 145  134          SET_SIZE(vtag_flushpage)
 146  135  
 147      -#endif  /* lint */
 148  136  
 149      -
 150      -#if defined(lint)
 151      -
 152      -void
 153      -vtag_flushall(void)
 154      -{}
 155      -
 156      -#else   /* lint */
 157      -
 158  137          ENTRY_NP2(vtag_flushall, demap_all)
 159  138          /*
 160  139           * flush the tlb
 161  140           */
 162  141          sethi   %hi(FLUSH_ADDR), %o3
 163  142          set     DEMAP_ALL_TYPE, %g1
 164  143          stxa    %g0, [%g1]ASI_DTLB_DEMAP
 165  144          stxa    %g0, [%g1]ASI_ITLB_DEMAP
 166  145          flush   %o3
 167  146          retl
 168  147          nop
 169  148          SET_SIZE(demap_all)
 170  149          SET_SIZE(vtag_flushall)
 171  150  
 172      -#endif  /* lint */
 173  151  
 174      -
 175      -#if defined(lint)
 176      -
 177      -/* ARGSUSED */
 178      -void
 179      -vtag_flushpage_tl1(uint64_t vaddr, uint64_t sfmmup)
 180      -{}
 181      -
 182      -#else   /* lint */
 183      -
 184  152          ENTRY_NP(vtag_flushpage_tl1)
 185  153          /*
 186  154           * x-trap to flush page from tlb and tsb
 187  155           *
 188  156           * %g1 = vaddr, zero-extended on 32-bit kernel
 189  157           * %g2 = sfmmup
 190  158           *
 191  159           * assumes TSBE_TAG = 0
 192  160           */
 193  161          srln    %g1, MMU_PAGESHIFT, %g1
↓ open down ↓ 24 lines elided ↑ open up ↑
 218  186          srlx    %g5, CTXREG_NEXT_SHIFT, %g2     ! %g2 = nucleus pgsz 
 219  187          sllx    %g2, CTXREG_NEXT_SHIFT, %g2     ! preserve nucleus pgsz 
 220  188          or      %g6, %g2, %g6                   ! %g6 = nucleus pgsz | primary pgsz | cnum      
 221  189          stxa    %g6, [%g4]ASI_DMMU              ! wr new ctxum
 222  190          stxa    %g0, [%g1]ASI_DTLB_DEMAP
 223  191          stxa    %g0, [%g1]ASI_ITLB_DEMAP
 224  192          stxa    %g5, [%g4]ASI_DMMU              ! restore old ctxnum
 225  193          retry
 226  194          SET_SIZE(vtag_flushpage_tl1)
 227  195  
 228      -#endif  /* lint */
 229  196  
 230      -
 231      -#if defined(lint)
 232      -
 233      -/* ARGSUSED */
 234      -void
 235      -vtag_flush_pgcnt_tl1(uint64_t vaddr, uint64_t sfmmup_pgcnt)
 236      -{}
 237      -
 238      -#else   /* lint */
 239      -
 240  197          ENTRY_NP(vtag_flush_pgcnt_tl1)
 241  198          /*
 242  199           * x-trap to flush pgcnt MMU_PAGESIZE pages from tlb
 243  200           *
 244  201           * %g1 = vaddr, zero-extended on 32-bit kernel
 245  202           * %g2 = <sfmmup58|pgcnt6>
 246  203           *
 247  204           * NOTE: this handler relies on the fact that no
 248  205           *      interrupts or traps can occur during the loop
 249  206           *      issuing the TLB_DEMAP operations. It is assumed
↓ open down ↓ 58 lines elided ↑ open up ↑
 308  265          flush   %g5                             ! flush required by immu
 309  266  
 310  267          deccc   %g3                             /* decr pgcnt */
 311  268          bnz,pt  %icc,3b
 312  269            add   %g1, %g2, %g1                   /* next page */
 313  270  
 314  271          stxa    %g6, [%g4]ASI_DMMU              /* restore old ctxnum */
 315  272          retry
 316  273          SET_SIZE(vtag_flush_pgcnt_tl1)
 317  274  
 318      -#endif  /* lint */
 319  275  
 320      -
 321      -#if defined(lint)
 322      -
 323      -/*ARGSUSED*/
 324      -void
 325      -vtag_flushall_tl1(uint64_t dummy1, uint64_t dummy2)
 326      -{}
 327      -
 328      -#else   /* lint */
 329      -
 330  276          ENTRY_NP(vtag_flushall_tl1)
 331  277          /*
 332  278           * x-trap to flush tlb
 333  279           */
 334  280          set     DEMAP_ALL_TYPE, %g4
 335  281          stxa    %g0, [%g4]ASI_DTLB_DEMAP
 336  282          stxa    %g0, [%g4]ASI_ITLB_DEMAP
 337  283          retry
 338  284          SET_SIZE(vtag_flushall_tl1)
 339  285  
 340      -#endif  /* lint */
 341  286  
 342      -
 343  287  /*
 344  288   * VAC (virtual address conflict) does not apply to OPL.
 345  289   * VAC resolution is managed by the Olympus processor hardware.
 346  290   * As a result, all OPL VAC flushing routines are no-ops.
 347  291   */
 348  292  
 349      -#if defined(lint)
 350      -
 351      -/* ARGSUSED */
 352      -void
 353      -vac_flushpage(pfn_t pfnum, int vcolor)
 354      -{}
 355      -
 356      -#else   /* lint */
 357      -
 358  293          ENTRY(vac_flushpage)
 359  294          retl
 360  295            nop
 361  296          SET_SIZE(vac_flushpage)
 362  297  
 363      -#endif  /* lint */
 364      -
 365      -#if defined(lint)
 366      -
 367      -/* ARGSUSED */
 368      -void
 369      -vac_flushpage_tl1(uint64_t pfnum, uint64_t vcolor)
 370      -{}
 371      -
 372      -#else   /* lint */
 373      -
 374  298          ENTRY_NP(vac_flushpage_tl1)
 375  299          retry
 376  300          SET_SIZE(vac_flushpage_tl1)
 377  301  
 378      -#endif  /* lint */
 379  302  
 380      -
 381      -#if defined(lint)
 382      -
 383      -/* ARGSUSED */
 384      -void
 385      -vac_flushcolor(int vcolor, pfn_t pfnum)
 386      -{}
 387      -
 388      -#else   /* lint */
 389      -
 390  303          ENTRY(vac_flushcolor)
 391  304          retl
 392  305           nop
 393  306          SET_SIZE(vac_flushcolor)
 394  307  
 395      -#endif  /* lint */
 396  308  
 397  309  
 398      -
 399      -#if defined(lint)
 400      -
 401      -/* ARGSUSED */
 402      -void
 403      -vac_flushcolor_tl1(uint64_t vcolor, uint64_t pfnum)
 404      -{}
 405      -
 406      -#else   /* lint */
 407      -
 408  310          ENTRY(vac_flushcolor_tl1)
 409  311          retry
 410  312          SET_SIZE(vac_flushcolor_tl1)
 411  313  
 412      -#endif  /* lint */
 413      -
 414      -#if defined(lint)
 415      -
 416      -int
 417      -idsr_busy(void)
 418      -{
 419      -        return (0);
 420      -}
 421      -
 422      -#else   /* lint */
 423      -
 424  314  /*
 425  315   * Determine whether or not the IDSR is busy.
 426  316   * Entry: no arguments
 427  317   * Returns: 1 if busy, 0 otherwise
 428  318   */
 429  319          ENTRY(idsr_busy)
 430  320          ldxa    [%g0]ASI_INTR_DISPATCH_STATUS, %g1
 431  321          clr     %o0
 432  322          btst    IDSR_BUSY, %g1
 433  323          bz,a,pt %xcc, 1f
 434  324          mov     1, %o0
 435  325  1:
 436  326          retl
 437  327          nop
 438  328          SET_SIZE(idsr_busy)
 439  329  
 440      -#endif  /* lint */
 441      -
 442      -#if defined(lint)
 443      -
 444      -/* ARGSUSED */
 445      -void
 446      -init_mondo(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
 447      -{}
 448      -
 449      -/* ARGSUSED */
 450      -void
 451      -init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2)
 452      -{}
 453      -
 454      -#else   /* lint */
 455      -
 456  330          .global _dispatch_status_busy
 457  331  _dispatch_status_busy:
 458  332          .asciz  "ASI_INTR_DISPATCH_STATUS error: busy"
 459  333          .align  4
 460  334  
 461  335  /*
 462  336   * Setup interrupt dispatch data registers
 463  337   * Entry:
 464  338   *      %o0 - function or inumber to call
 465  339   *      %o1, %o2 - arguments (2 uint64_t's)
↓ open down ↓ 33 lines elided ↑ open up ↑
 499  373          ! interrupt vector dispatch data reg 2
 500  374          !
 501  375          stxa    %o2, [%g3]ASI_INTR_DISPATCH
 502  376  
 503  377          membar  #Sync
 504  378          retl
 505  379          nop
 506  380          SET_SIZE(init_mondo_nocheck)
 507  381          SET_SIZE(init_mondo)
 508  382  
 509      -#endif  /* lint */
 510  383  
 511      -
 512      -#if defined(lint)
 513      -
 514      -/* ARGSUSED */
 515      -void
 516      -shipit(int upaid, int bn)
 517      -{ return; }
 518      -
 519      -#else   /* lint */
 520      -
 521  384  /*
 522  385   * Ship mondo to aid using busy/nack pair bn
 523  386   */
 524  387          ENTRY_NP(shipit)
 525  388          sll     %o0, IDCR_PID_SHIFT, %g1        ! IDCR<23:14> = agent id
 526  389          sll     %o1, IDCR_BN_SHIFT, %g2         ! IDCR<28:24> = b/n pair
 527  390          or      %g1, IDCR_OFFSET, %g1           ! IDCR<13:0> = 0x70
 528  391          or      %g1, %g2, %g1
 529  392          stxa    %g0, [%g1]ASI_INTR_DISPATCH     ! interrupt vector dispatch
 530  393          membar  #Sync
 531  394          retl
 532  395          nop
 533  396          SET_SIZE(shipit)
 534  397  
 535      -#endif  /* lint */
 536  398  
 537      -
 538      -#if defined(lint)
 539      -
 540      -/* ARGSUSED */
 541      -void
 542      -flush_instr_mem(caddr_t vaddr, size_t len)
 543      -{}
 544      -
 545      -#else   /* lint */
 546      -
 547  399  /*
 548  400   * flush_instr_mem:
 549  401   *      Flush 1 page of the I-$ starting at vaddr
 550  402   *      %o0 vaddr
 551  403   *      %o1 bytes to be flushed
 552  404   *
 553  405   * SPARC64-VI maintains consistency of the on-chip Instruction Cache with
 554  406   * the stores from all processors so that a FLUSH instruction is only needed
 555  407   * to ensure pipeline is consistent. This means a single flush is sufficient at
 556  408   * the end of a sequence of stores that updates the instruction stream to
 557  409   * ensure correct operation.
 558  410   */
 559  411  
 560  412          ENTRY(flush_instr_mem)
 561  413          flush   %o0                     ! address irrelevant
 562  414          retl
 563  415          nop
 564  416          SET_SIZE(flush_instr_mem)
 565  417  
 566      -#endif  /* lint */
 567  418  
 568      -
 569  419  /*
 570  420   * flush_ecache:
 571  421   *      %o0 - 64 bit physical address
 572  422   *      %o1 - ecache size
 573  423   *      %o2 - ecache linesize
 574  424   */
 575      -#if defined(lint)
 576  425  
 577      -/*ARGSUSED*/
 578      -void
 579      -flush_ecache(uint64_t physaddr, size_t ecache_size, size_t ecache_linesize)
 580      -{}
 581      -
 582      -#else /* !lint */
 583      -
 584  426          ENTRY(flush_ecache)
 585  427  
 586  428          /*
 587  429           * Flush the entire Ecache.
 588  430           */
 589  431          ECACHE_FLUSHALL(%o1, %o2, %o0, %o4)
 590  432          retl
 591  433          nop
 592  434          SET_SIZE(flush_ecache)
 593  435  
 594      -#endif /* lint */
 595      -
 596      -#if defined(lint)
 597      -
 598      -/*ARGSUSED*/
 599      -void
 600      -kdi_flush_idcache(int dcache_size, int dcache_lsize, int icache_size,
 601      -    int icache_lsize)
 602      -{
 603      -}
 604      -
 605      -#else   /* lint */
 606      -
 607  436          /*
 608  437           * I/D cache flushing is not needed for OPL processors
 609  438           */
 610  439          ENTRY(kdi_flush_idcache)
 611  440          retl
 612  441          nop
 613  442          SET_SIZE(kdi_flush_idcache)
 614  443  
 615      -#endif  /* lint */
 616      -
 617  444  #ifdef  TRAPTRACE
 618  445  /*
 619  446   * Simplified trap trace macro for OPL. Adapted from us3.
 620  447   */
 621  448  #define OPL_TRAPTRACE(ptr, scr1, scr2, label)                   \
 622  449          CPU_INDEX(scr1, ptr);                                   \
 623  450          sll     scr1, TRAPTR_SIZE_SHIFT, scr1;                  \
 624  451          set     trap_trace_ctl, ptr;                            \
 625  452          add     ptr, scr1, scr1;                                \
 626  453          ld      [scr1 + TRAPTR_LIMIT], ptr;                     \
↓ open down ↓ 367 lines elided ↑ open up ↑
 994  821  /*
 995  822   * In case of urgent errors some MMU registers may be
 996  823   * corrupted, so we set here some reasonable values for
 997  824   * them. Note that resetting MMU registers also reset the context
 998  825   * info, we will need to reset the window registers to prevent
 999  826   * spill/fill that depends on context info for correct behaviour.
1000  827   * Note that the TLBs must be flushed before programming the context
1001  828   * registers.
1002  829   */
1003  830  
1004      -#if !defined(lint)
1005  831  #define RESET_MMU_REGS(tmp1, tmp2, tmp3)                        \
1006  832          FLUSH_ALL_TLB(tmp1)                                     ;\
1007  833          set     MMU_PCONTEXT, tmp1                              ;\
1008  834          sethi   %hi(kcontextreg), tmp2                          ;\
1009  835          ldx     [tmp2 + %lo(kcontextreg)], tmp2                 ;\
1010  836          stxa    tmp2, [tmp1]ASI_DMMU                            ;\
1011  837          set     MMU_SCONTEXT, tmp1                              ;\
1012  838          stxa    tmp2, [tmp1]ASI_DMMU                            ;\
1013  839          sethi   %hi(ktsb_base), tmp1                            ;\
1014  840          ldx     [tmp1 + %lo(ktsb_base)], tmp2                   ;\
↓ open down ↓ 1 lines elided ↑ open up ↑
1016  842          stxa    tmp2, [tmp3]ASI_IMMU                            ;\
1017  843          stxa    tmp2, [tmp3]ASI_DMMU                            ;\
1018  844          membar  #Sync                                           ;\
1019  845          RESET_WINREG(tmp1)
1020  846  
1021  847  #define RESET_TSB_TAGPTR(tmp)                                   \
1022  848          set     MMU_TAG_ACCESS, tmp                             ;\
1023  849          stxa    %g0, [tmp]ASI_IMMU                              ;\
1024  850          stxa    %g0, [tmp]ASI_DMMU                              ;\
1025  851          membar  #Sync
1026      -#endif /* lint */
1027  852  
1028  853  /*
1029  854   * In case of errors in the MMU_TSB_PREFETCH registers we have to
1030  855   * reset them. We can use "0" as the reset value, this way we set
1031  856   * the "V" bit of the registers to 0, which will disable the prefetch
1032  857   * so the values of the other fields are irrelevant.
1033  858   */
1034      -#if !defined(lint)
1035  859  #define RESET_TSB_PREFETCH(tmp)                 \
1036  860          set     VA_UTSBPREF_8K, tmp             ;\
1037  861          stxa    %g0, [tmp]ASI_ITSB_PREFETCH     ;\
1038  862          set     VA_UTSBPREF_4M, tmp             ;\
1039  863          stxa    %g0, [tmp]ASI_ITSB_PREFETCH     ;\
1040  864          set     VA_KTSBPREF_8K, tmp             ;\
1041  865          stxa    %g0, [tmp]ASI_ITSB_PREFETCH     ;\
1042  866          set     VA_KTSBPREF_4M, tmp             ;\
1043  867          stxa    %g0, [tmp]ASI_ITSB_PREFETCH     ;\
1044  868          set     VA_UTSBPREF_8K, tmp             ;\
1045  869          stxa    %g0, [tmp]ASI_DTSB_PREFETCH     ;\
1046  870          set     VA_UTSBPREF_4M, tmp             ;\
1047  871          stxa    %g0, [tmp]ASI_DTSB_PREFETCH     ;\
1048  872          set     VA_KTSBPREF_8K, tmp             ;\
1049  873          stxa    %g0, [tmp]ASI_DTSB_PREFETCH     ;\
1050  874          set     VA_KTSBPREF_4M, tmp             ;\
1051  875          stxa    %g0, [tmp]ASI_DTSB_PREFETCH
1052      -#endif /* lint */
1053  876  
1054  877  /*
1055  878   * In case of errors in the MMU_SHARED_CONTEXT register we have to
1056  879   * reset its value. We can use "0" as the reset value, it will put
1057  880   * 0 in the IV field disabling the shared context support, and
1058  881   * making values of all the other fields of the register irrelevant.
1059  882   */
1060      -#if !defined(lint)
1061  883  #define RESET_SHARED_CTXT(tmp)                  \
1062  884          set     MMU_SHARED_CONTEXT, tmp         ;\
1063  885          stxa    %g0, [tmp]ASI_DMMU
1064      -#endif /* lint */
1065  886  
1066  887  /*
1067  888   * RESET_TO_PRIV()
1068  889   *
1069  890   * In many cases, we need to force the thread into privilege mode because
1070  891   * privilege mode is only thing in which the system continue to work
1071  892   * due to undeterminable user mode information that come from register
1072  893   * corruption.
1073  894   *
1074  895   *  - opl_uger_ctxt
↓ open down ↓ 43 lines elided ↑ open up ↑
1118  939          rdpr    %pstate, local                                  ;\
1119  940          wrpr    local, PSTATE_AG, %pstate                       ;\
1120  941          wrpr    %g0, 1, %tl                                     ;\
1121  942          set     TSTATE_KERN, tmp                                ;\
1122  943          rdpr    %cwp, tmp1                                      ;\
1123  944          or      tmp, tmp1, tmp                                  ;\
1124  945          wrpr    tmp, %g0, %tstate                               ;\
1125  946          wrpr    %g0, %tpc
1126  947  
1127  948  
1128      -#if defined(lint)
1129      -
1130      -void
1131      -ce_err(void)
1132      -{}
1133      -
1134      -#else   /* lint */
1135      -
1136  949  /*
1137  950   * We normally don't expect CE traps since we disable the
1138  951   * 0x63 trap reporting at the start of day. There is a
1139  952   * small window before we disable them, so let check for
1140  953   * it. Otherwise, panic.
1141  954   */
1142  955  
1143  956          .align  128
1144  957          ENTRY_NP(ce_err)
1145  958          mov     AFSR_ECR, %g1
↓ open down ↓ 7 lines elided ↑ open up ↑
1153  966           * We did disabled the 0x63 trap reporting.
1154  967           * This shouldn't happen - panic.
1155  968           */
1156  969          set     trap, %g1
1157  970          rdpr    %tt, %g3
1158  971          sethi   %hi(sys_trap), %g5
1159  972          jmp     %g5 + %lo(sys_trap)
1160  973          sub     %g0, 1, %g4
1161  974          SET_SIZE(ce_err)
1162  975  
1163      -#endif  /* lint */
1164  976  
1165      -
1166      -#if defined(lint)
1167      -
1168      -void
1169      -ce_err_tl1(void)
1170      -{}
1171      -
1172      -#else   /* lint */
1173      -
1174  977  /*
1175  978   * We don't use trap for CE detection.
1176  979   */
1177  980          ENTRY_NP(ce_err_tl1)
1178  981          set     trap, %g1
1179  982          rdpr    %tt, %g3
1180  983          sethi   %hi(sys_trap), %g5
1181  984          jmp     %g5 + %lo(sys_trap)
1182  985          sub     %g0, 1, %g4
1183  986          SET_SIZE(ce_err_tl1)
1184  987  
1185      -#endif  /* lint */
1186  988  
1187      -
1188      -#if defined(lint)
1189      -
1190      -void
1191      -async_err(void)
1192      -{}
1193      -
1194      -#else   /* lint */
1195      -
1196  989  /*
1197  990   * async_err is the default handler for IAE/DAE traps.
1198  991   * For OPL, we patch in the right handler at start of day.
1199  992   * But if a IAE/DAE trap get generated before the handler
1200  993   * is patched, panic.
1201  994   */
1202  995          ENTRY_NP(async_err)
1203  996          set     trap, %g1
1204  997          rdpr    %tt, %g3
1205  998          sethi   %hi(sys_trap), %g5
1206  999          jmp     %g5 + %lo(sys_trap)
1207 1000          sub     %g0, 1, %g4
1208 1001          SET_SIZE(async_err)
1209 1002  
1210      -#endif  /* lint */
1211      -
1212      -#if defined(lint)
1213      -void
1214      -opl_sync_trap(void)
1215      -{}
1216      -#else   /* lint */
1217      -
1218 1003          .seg    ".data"
1219 1004          .global opl_clr_freg
1220 1005          .global opl_cpu0_err_log
1221 1006  
1222 1007          .align  16
1223 1008  opl_clr_freg:
1224 1009          .word   0
1225 1010          .align  16
1226 1011  
1227 1012          .align  MMU_PAGESIZE
↓ open down ↓ 166 lines elided ↑ open up ↑
1394 1179          mov     %g6, %g2                ! pass SFAR to the 2nd arg
1395 1180          set     opl_cpu_isync_tl0_error, %g1
1396 1181          set     opl_cpu_dsync_tl0_error, %g6
1397 1182          cmp     %g4, T_INSTR_ERROR
1398 1183          movne   %icc, %g6, %g1
1399 1184  6:
1400 1185          sethi   %hi(sys_trap), %g5
1401 1186          jmp     %g5 + %lo(sys_trap)
1402 1187           mov    PIL_15, %g4
1403 1188          SET_SIZE(opl_sync_trap)
1404      -#endif  /* lint */
1405 1189  
1406      -#if defined(lint)
1407      -void
1408      -opl_uger_trap(void)
1409      -{}
1410      -#else   /* lint */
1411 1190  /*
1412 1191   * Common Urgent error trap handler (tt=0x40)
1413 1192   * All TL=0 and TL>0 0x40 traps vector to this handler.
1414 1193   * The error handling can be best summarized as follows:
1415 1194   * 1. Read the Urgent error status register (UGERSR)
1416 1195   *    Faultaddress is N/A here and it is not collected.
1417 1196   * 2. Check to see if we have a multiple errors case
1418 1197   *    If so, we enable WEAK_ED (weak error detection) bit
1419 1198   *    to prevent any potential error storms and branch directly
1420 1199   *    to generate ereport. (we don't decode/handle individual
↓ open down ↓ 194 lines elided ↑ open up ↑
1615 1394           */
1616 1395  opl_uger_panic_cmn:
1617 1396          RESET_USER_RTT_REGS(%g4, %g5, opl_uger_panic_resetskip)
1618 1397  opl_uger_panic_resetskip:
1619 1398          rdpr    %tl, %g3                        ! arg #2
1620 1399          set     opl_cpu_urgent_error, %g1       ! pc
1621 1400          sethi   %hi(sys_trap), %g5
1622 1401          jmp     %g5 + %lo(sys_trap)
1623 1402           mov    PIL_15, %g4
1624 1403          SET_SIZE(opl_uger_trap)
1625      -#endif  /* lint */
1626 1404  
1627      -#if defined(lint)
1628      -void
1629      -opl_ta3_trap(void)
1630      -{}
1631      -void
1632      -opl_cleanw_subr(void)
1633      -{}
1634      -#else   /* lint */
1635 1405  /*
1636 1406   * OPL ta3 support (note please, that win_reg
1637 1407   * area size for each cpu is 2^7 bytes)
1638 1408   */
1639 1409  
1640 1410  #define RESTORE_WREGS(tmp1, tmp2)               \
1641 1411          CPU_INDEX(tmp1, tmp2)                   ;\
1642 1412          sethi   %hi(opl_ta3_save), tmp2         ;\
1643 1413          ldx     [tmp2 +%lo(opl_ta3_save)], tmp2 ;\
1644 1414          sllx    tmp1, 7, tmp1                   ;\
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1720 1490          flushw
1721 1491          rdpr    %cwp, %g6
1722 1492          wrpr    %g5, %cwp
1723 1493          RESTORE_WREGS(%g2, %g5)
1724 1494          wrpr    %g6, %cwp
1725 1495          restored
1726 1496          restore
1727 1497          jmp     %g7
1728 1498            nop
1729 1499          SET_SIZE(opl_cleanw_subr)
1730      -#endif  /* lint */
1731 1500  
1732      -#if defined(lint)
1733      -
1734      -void
1735      -opl_serr_instr(void)
1736      -{}
1737      -
1738      -#else   /* lint */
1739 1501  /*
1740 1502   * The actual trap handler for tt=0x0a, and tt=0x32
1741 1503   */
1742 1504          ENTRY_NP(opl_serr_instr)
1743 1505          OPL_SAVE_GLOBAL(%g1,%g2,%g3)
1744 1506          sethi   %hi(opl_sync_trap), %g3
1745 1507          jmp     %g3 + %lo(opl_sync_trap)
1746 1508           rdpr    %tt, %g1
1747 1509          .align  32
1748 1510          SET_SIZE(opl_serr_instr)
1749 1511  
1750      -#endif  /* lint */
1751      -
1752      -#if defined(lint)
1753      -
1754      -void
1755      -opl_ugerr_instr(void)
1756      -{}
1757      -
1758      -#else   /* lint */
1759 1512  /*
1760 1513   * The actual trap handler for tt=0x40
1761 1514   */
1762 1515          ENTRY_NP(opl_ugerr_instr)
1763 1516          sethi   %hi(opl_uger_trap), %g3
1764 1517          jmp     %g3 + %lo(opl_uger_trap)
1765 1518           nop
1766 1519          .align  32
1767 1520          SET_SIZE(opl_ugerr_instr)
1768 1521  
1769      -#endif  /* lint */
1770      -
1771      -#if defined(lint)
1772      -
1773      -void
1774      -opl_ta3_instr(void)
1775      -{}
1776      -
1777      -#else   /* lint */
1778 1522  /*
1779 1523   * The actual trap handler for tt=0x103 (flushw)
1780 1524   */
1781 1525          ENTRY_NP(opl_ta3_instr)
1782 1526          sethi   %hi(opl_ta3_trap), %g3
1783 1527          jmp     %g3 + %lo(opl_ta3_trap)
1784 1528           nop
1785 1529          .align  32
1786 1530          SET_SIZE(opl_ta3_instr)
1787 1531  
1788      -#endif  /* lint */
1789      -
1790      -#if defined(lint)
1791      -
1792      -void
1793      -opl_ta4_instr(void)
1794      -{}
1795      -
1796      -#else   /* lint */
1797 1532  /*
1798 1533   * The patch for the .clean_windows code
1799 1534   */
1800 1535          ENTRY_NP(opl_ta4_instr)
1801 1536          sethi   %hi(opl_cleanw_subr), %g3
1802 1537          add     %g3, %lo(opl_cleanw_subr), %g3
1803 1538          jmpl    %g3, %g7
1804 1539            add   %g7, 8, %g7
1805 1540          nop
1806 1541          nop
1807 1542          nop
1808 1543          SET_SIZE(opl_ta4_instr)
1809 1544  
1810      -#endif  /* lint */
1811      -
1812      -#if defined(lint)
1813      -/*
1814      - *  Get timestamp (stick).
1815      - */
1816      -/* ARGSUSED */
1817      -void
1818      -stick_timestamp(int64_t *ts)
1819      -{
1820      -}
1821      -
1822      -#else   /* lint */
1823      -
1824 1545          ENTRY_NP(stick_timestamp)
1825 1546          rd      STICK, %g1      ! read stick reg
1826 1547          sllx    %g1, 1, %g1
1827 1548          srlx    %g1, 1, %g1     ! clear npt bit
1828 1549  
1829 1550          retl
1830 1551          stx     %g1, [%o0]      ! store the timestamp
1831 1552          SET_SIZE(stick_timestamp)
1832 1553  
1833      -#endif  /* lint */
1834 1554  
1835      -
1836      -#if defined(lint)
1837      -/*
1838      - * Set STICK adjusted by skew.
1839      - */
1840      -/* ARGSUSED */
1841      -void
1842      -stick_adj(int64_t skew)
1843      -{
1844      -}
1845      -
1846      -#else   /* lint */
1847      -
1848 1555          ENTRY_NP(stick_adj)
1849 1556          rdpr    %pstate, %g1            ! save processor state
1850 1557          andn    %g1, PSTATE_IE, %g3
1851 1558          ba      1f                      ! cache align stick adj
1852 1559          wrpr    %g0, %g3, %pstate       ! turn off interrupts
1853 1560  
1854 1561          .align  16
1855 1562  1:      nop
1856 1563  
1857 1564          rd      STICK, %g4              ! read stick reg
1858 1565          add     %g4, %o0, %o1           ! adjust stick with skew
1859 1566          wr      %o1, %g0, STICK         ! write stick reg
1860 1567  
1861 1568          retl
1862 1569          wrpr    %g1, %pstate            ! restore processor state
1863 1570          SET_SIZE(stick_adj)
1864 1571  
1865      -#endif  /* lint */
1866      -
1867      -#if defined(lint)
1868      -/*
1869      - * Debugger-specific stick retrieval
1870      - */
1871      -/*ARGSUSED*/
1872      -int
1873      -kdi_get_stick(uint64_t *stickp)
1874      -{
1875      -        return (0);
1876      -}
1877      -
1878      -#else   /* lint */
1879      -
1880 1572          ENTRY_NP(kdi_get_stick)
1881 1573          rd      STICK, %g1
1882 1574          stx     %g1, [%o0]
1883 1575          retl
1884 1576          mov     %g0, %o0
1885 1577          SET_SIZE(kdi_get_stick)
1886 1578  
1887      -#endif  /* lint */
1888      -
1889      -#if defined(lint)
1890      -
1891      -/*ARGSUSED*/
1892      -int
1893      -dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain)
1894      -{ return (0); }
1895      -
1896      -#else
1897      -
1898 1579          ENTRY(dtrace_blksuword32)
1899 1580          save    %sp, -SA(MINFRAME + 4), %sp
1900 1581  
1901 1582          rdpr    %pstate, %l1
1902 1583          andn    %l1, PSTATE_IE, %l2             ! disable interrupts to
1903 1584          wrpr    %g0, %l2, %pstate               ! protect our FPU diddling
1904 1585  
1905 1586          rd      %fprs, %l0
1906 1587          andcc   %l0, FPRS_FEF, %g0
1907 1588          bz,a,pt %xcc, 1f                        ! if the fpu is disabled
↓ open down ↓ 44 lines elided ↑ open up ↑
1952 1633           */
1953 1634          brnz,pt %i2, 1f
1954 1635          nop
1955 1636          ret
1956 1637          restore %g0, -1, %o0
1957 1638  1:
1958 1639          call    dtrace_blksuword32_err
1959 1640          restore
1960 1641  
1961 1642          SET_SIZE(dtrace_blksuword32)
1962      -#endif /* lint */
1963 1643  
1964      -#if defined(lint)
1965      -/*ARGSUSED*/
1966      -void
1967      -ras_cntr_reset(void *arg)
1968      -{
1969      -}
1970      -#else
1971 1644          ENTRY_NP(ras_cntr_reset)
1972 1645          set     OPL_SCRATCHPAD_ERRLOG, %o1
1973 1646          ldxa    [%o1]ASI_SCRATCHPAD, %o0
1974 1647          or      %o0, ERRLOG_REG_NUMERR_MASK, %o0
1975 1648          retl
1976 1649           stxa   %o0, [%o1]ASI_SCRATCHPAD
1977 1650          SET_SIZE(ras_cntr_reset)
1978      -#endif /* lint */
1979 1651  
1980      -#if defined(lint)
1981      -/* ARGSUSED */
1982      -void
1983      -opl_error_setup(uint64_t cpu_err_log_pa)
1984      -{
1985      -}
1986      -
1987      -#else   /* lint */
1988 1652          ENTRY_NP(opl_error_setup)
1989 1653          /*
1990 1654           * Initialize the error log scratchpad register
1991 1655           */
1992 1656          ldxa    [%g0]ASI_EIDR, %o2
1993 1657          sethi   %hi(ERRLOG_REG_EIDR_MASK), %o1
1994 1658          or      %o1, %lo(ERRLOG_REG_EIDR_MASK), %o1
1995 1659          and     %o2, %o1, %o3
1996 1660          sllx    %o3, ERRLOG_REG_EIDR_SHIFT, %o2
1997 1661          or      %o2, %o0, %o3
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2000 1664          stxa    %o0, [%o1]ASI_SCRATCHPAD
2001 1665          /*
2002 1666           * Disable all restrainable error traps
2003 1667           */
2004 1668          mov     AFSR_ECR, %o1
2005 1669          ldxa    [%o1]ASI_AFSR, %o0
2006 1670          andn    %o0, ASI_ECR_RTE_UE|ASI_ECR_RTE_CEDG, %o0
2007 1671          retl
2008 1672            stxa  %o0, [%o1]ASI_AFSR
2009 1673          SET_SIZE(opl_error_setup)
2010      -#endif /* lint */
2011 1674  
2012      -#if defined(lint)
2013      -/* ARGSUSED */
2014      -void
2015      -cpu_early_feature_init(void)
2016      -{
2017      -}
2018      -#else   /* lint */
2019 1675          ENTRY_NP(cpu_early_feature_init)
2020 1676          /*
2021 1677           * Enable MMU translating multiple page sizes for
2022 1678           * sITLB and sDTLB.
2023 1679           */
2024 1680          mov     LSU_MCNTL, %o0
2025 1681          ldxa    [%o0] ASI_MCNTL, %o1
2026 1682          or      %o1, MCNTL_MPG_SITLB | MCNTL_MPG_SDTLB, %o1
2027 1683            stxa  %o1, [%o0] ASI_MCNTL
2028 1684          /*
2029 1685           * Demap all previous entries.
2030 1686           */
2031 1687          sethi   %hi(FLUSH_ADDR), %o1
2032 1688          set     DEMAP_ALL_TYPE, %o0
2033 1689          stxa    %g0, [%o0]ASI_DTLB_DEMAP
2034 1690          stxa    %g0, [%o0]ASI_ITLB_DEMAP
2035 1691          retl
2036 1692            flush %o1
2037 1693          SET_SIZE(cpu_early_feature_init)
2038      -#endif /* lint */
2039 1694  
2040      -#if     defined(lint)
2041 1695  /*
2042 1696   * This function is called for each (enabled) CPU. We use it to
2043 1697   * initialize error handling related registers.
2044 1698   */
2045      -/*ARGSUSED*/
2046      -void
2047      -cpu_feature_init(void)
2048      -{}
2049      -#else   /* lint */
2050 1699          ENTRY(cpu_feature_init)
2051 1700          !
2052 1701          ! get the device_id and store the device_id
2053 1702          ! in the appropriate cpunodes structure
2054 1703          ! given the cpus index
2055 1704          !
2056 1705          CPU_INDEX(%o0, %o1)
2057 1706          mulx %o0, CPU_NODE_SIZE, %o0
2058 1707          set  cpunodes + DEVICE_ID, %o1
2059 1708          ldxa [%g0] ASI_DEVICE_SERIAL_ID, %o2
2060 1709          stx  %o2, [%o0 + %o1]
2061 1710          !
2062 1711          ! initialize CPU registers
2063 1712          !
2064 1713          ba      opl_cpu_reg_init
2065 1714          nop
2066 1715          SET_SIZE(cpu_feature_init)
2067      -#endif  /* lint */
2068 1716  
2069      -#if defined(lint)
2070      -
2071      -void
2072      -cpu_cleartickpnt(void)
2073      -{}
2074      -
2075      -#else   /* lint */
2076 1717          /*
2077 1718           * Clear the NPT (non-privileged trap) bit in the %tick/%stick
2078 1719           * registers. In an effort to make the change in the
2079 1720           * tick/stick counter as consistent as possible, we disable
2080 1721           * all interrupts while we're changing the registers. We also
2081 1722           * ensure that the read and write instructions are in the same
2082 1723           * line in the instruction cache.
2083 1724           */
2084 1725          ENTRY_NP(cpu_clearticknpt)
2085 1726          rdpr    %pstate, %g1            /* save processor state */
↓ open down ↓ 19 lines elided ↑ open up ↑
2105 1746  4:
2106 1747          rd      STICK, %g2              /* get stick register */
2107 1748          wr      %g3, %g2, STICK         /* write stick register, */
2108 1749                                          /*   clearing NPT bit   */
2109 1750  3:
2110 1751          jmp     %g4 + 4
2111 1752          wrpr    %g0, %g1, %pstate       /* restore processor state */
2112 1753  
2113 1754          SET_SIZE(cpu_clearticknpt)
2114 1755  
2115      -#endif  /* lint */
2116      -
2117      -#if defined(lint)
2118      -
2119      -void
2120      -cpu_halt_cpu(void)
2121      -{}
2122      -
2123      -void
2124      -cpu_smt_pause(void)
2125      -{}
2126      -
2127      -#else   /* lint */
2128      -
2129 1756          /*
2130 1757           * Halt the current strand with the suspend instruction.
2131 1758           * The compiler/asm currently does not support this suspend
2132 1759           * instruction mnemonic, use byte code for now.
2133 1760           */
2134 1761          ENTRY_NP(cpu_halt_cpu)
2135 1762          .word   0x81b01040
2136 1763          retl
2137 1764          nop
2138 1765          SET_SIZE(cpu_halt_cpu)
↓ open down ↓ 2 lines elided ↑ open up ↑
2141 1768           * Pause the current strand with the sleep instruction.
2142 1769           * The compiler/asm currently does not support this sleep
2143 1770           * instruction mnemonic, use byte code for now.
2144 1771           */
2145 1772          ENTRY_NP(cpu_smt_pause)
2146 1773          .word   0x81b01060
2147 1774          retl
2148 1775          nop
2149 1776          SET_SIZE(cpu_smt_pause)
2150 1777  
2151      -#endif  /* lint */
    
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