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--- old/usr/src/uts/i86pc/dboot/dboot_grub.s
+++ new/usr/src/uts/i86pc/dboot/dboot_grub.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
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17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 -#if defined(__lint)
28 -
29 -int silence_lint_warnings = 0;
30 -
31 -#else /* __lint */
32 -
33 27 #include <sys/multiboot.h>
34 28 #include <sys/multiboot2.h>
35 29 #include <sys/asm_linkage.h>
36 30 #include <sys/segments.h>
37 31 #include <sys/controlregs.h>
38 32
39 33 #include "dboot_xboot.h"
40 34
41 35 .text
42 36 .globl _start
43 37 _start:
44 38 jmp code_start
45 39
46 40 /*
47 41 * The multiboot header has to be at the start of the file
48 42 *
49 43 * The 32 bit kernel is ELF32, so the MB header is mostly ignored.
50 44 *
51 45 * The 64 bit kernel is ELF64, so we get grub to load the entire
52 46 * ELF file into memory and trick it into jumping into this code.
53 47 * The trick is done by a binary utility run after unix is linked,
54 48 * that rewrites the mb_header.
55 49 */
56 50 .align 4
57 51 .globl mb_header
58 52 mb_header:
59 53 .long MB_HEADER_MAGIC /* magic number */
60 54 #if defined(_BOOT_TARGET_i386)
61 55 .long MB_HEADER_FLAGS_32 /* flags */
62 56 .long MB_HEADER_CHECKSUM_32 /* checksum */
63 57 #elif defined (_BOOT_TARGET_amd64)
64 58 .long MB_HEADER_FLAGS_64 /* flags */
65 59 .long MB_HEADER_CHECKSUM_64 /* checksum */
66 60 #else
67 61 #error No architecture defined
68 62 #endif
69 63 .long 0x11111111 /* header_addr: patched by mbh_patch */
70 64 .long 0x100000 /* load_addr: patched by mbh_patch */
71 65 .long 0 /* load_end_addr - 0 means entire file */
72 66 .long 0 /* bss_end_addr */
73 67 .long 0x2222222 /* entry_addr: patched by mbh_patch */
74 68 .long 0 /* video mode.. */
75 69 .long 0 /* width 0 == don't care */
76 70 .long 0 /* height 0 == don't care */
77 71 .long 0 /* depth 0 == don't care */
78 72
79 73 #if defined(_BOOT_TARGET_i386)
80 74 /*
81 75 * The MB2 header must be 8 byte aligned relative to the beginning of
82 76 * the in-memory ELF object. The 32-bit kernel ELF file has sections
83 77 * which are 4-byte aligned, and as .align family directives only do
84 78 * control the alignment inside the section, we need to construct the
85 79 * image manually, by inserting the padding where needed. The alignment
86 80 * setup here depends on the first PT_LOAD section of the ELF file, if
87 81 * this section offset will change, this code must be reviewed.
88 82 * Similarily, if we add extra tag types into the information request
89 83 * or add tags into the tag list.
90 84 */
91 85 .long 0 /* padding */
92 86 #else
93 87 .balign MULTIBOOT_HEADER_ALIGN
94 88 #endif
95 89 mb2_header:
96 90 .long MULTIBOOT2_HEADER_MAGIC
97 91 .long MULTIBOOT_ARCHITECTURE_I386
98 92 .long mb2_header_end - mb2_header
99 93 .long -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT_ARCHITECTURE_I386 + (mb2_header_end - mb2_header))
100 94
101 95 /*
102 96 * Multiboot 2 tags follow. Note, the first tag immediately follows
103 97 * the header. Subsequent tags must be aligned by MULTIBOOT_TAG_ALIGN.
104 98 *
105 99 * MB information request tag.
106 100 */
107 101 information_request_tag_start:
108 102 .word MULTIBOOT_HEADER_TAG_INFORMATION_REQUEST
109 103 .word 0
110 104 .long information_request_tag_end - information_request_tag_start
111 105 .long MULTIBOOT_TAG_TYPE_CMDLINE
112 106 .long MULTIBOOT_TAG_TYPE_MODULE
113 107 .long MULTIBOOT_TAG_TYPE_BOOTDEV
114 108 .long MULTIBOOT_TAG_TYPE_MMAP
115 109 .long MULTIBOOT_TAG_TYPE_FRAMEBUFFER
116 110 .long MULTIBOOT_TAG_TYPE_BASIC_MEMINFO
117 111 information_request_tag_end:
118 112
119 113 #if defined (_BOOT_TARGET_amd64)
120 114 /*
121 115 * The following values are patched by mbh_patch for the 64-bit kernel,
122 116 * so we only provide this tag for the 64-bit kernel.
123 117 */
124 118 .balign MULTIBOOT_TAG_ALIGN
125 119 address_tag_start:
126 120 .word MULTIBOOT_HEADER_TAG_ADDRESS
127 121 .word 0
128 122 .long address_tag_end - address_tag_start
129 123 .long mb2_header
130 124 .globl mb2_load_addr
131 125 mb2_load_addr:
132 126 .long 0 /* load addr */
133 127 .long 0 /* load_end_addr */
134 128 .long 0 /* bss_end_addr */
135 129 address_tag_end:
136 130 /*
137 131 * entry address tag
138 132 */
139 133 .balign MULTIBOOT_TAG_ALIGN
140 134 entry_address_tag_start:
141 135 .word MULTIBOOT_HEADER_TAG_ENTRY_ADDRESS
142 136 .word 0
143 137 .long entry_address_tag_end - entry_address_tag_start
144 138 .long 0 /* entry addr */
145 139 entry_address_tag_end:
146 140
147 141 .balign MULTIBOOT_TAG_ALIGN /* Alignment for the next tag */
148 142 #endif
149 143 /*
150 144 * MB console flags tag
151 145 */
152 146 console_tag_start:
153 147 .word MULTIBOOT_HEADER_TAG_CONSOLE_FLAGS
154 148 .word 0
155 149 .long console_tag_end - console_tag_start
156 150 .long MULTIBOOT_CONSOLE_FLAGS_EGA_TEXT_SUPPORTED
157 151 console_tag_end:
158 152 .long 0 /* padding */
159 153
160 154 /*
161 155 * MB header framebuffer tag
162 156 */
163 157 framebuffer_tag_start:
164 158 .word MULTIBOOT_HEADER_TAG_FRAMEBUFFER
165 159 .word 0
166 160 .long framebuffer_tag_end - framebuffer_tag_start
167 161 .long 0 /* width - no preference */
168 162 .long 0 /* height - no preference */
169 163 .long 0 /* depth - no preference */
170 164 framebuffer_tag_end:
171 165 .long 0 /* padding */
172 166
173 167 /*
174 168 * Tell the bootloader to load the modules page aligned to
175 169 * the specified alignment.
176 170 */
177 171 .word MULTIBOOT_HEADER_TAG_MODULE_ALIGN
178 172 .word 0
179 173 .long 8
180 174
181 175 /*
182 176 * Termination tag.
183 177 */
184 178 .word MULTIBOOT_HEADER_TAG_END
185 179 .word 0
186 180 .long 8
187 181 mb2_header_end:
188 182
189 183 /*
190 184 * At entry we are in protected mode, 32 bit execution, paging and
191 185 * interrupts are disabled.
192 186 *
193 187 * EAX == MB_BOOTLOADER_MAGIC
194 188 * EBX points to multiboot information
195 189 * segment registers all have segments with base 0, limit == 0xffffffff
196 190 */
197 191 code_start:
198 192 movl %eax, mb_magic
199 193 movl %ebx, mb_addr
200 194
201 195 movl $stack_space, %esp /* load my stack pointer */
202 196 addl $STACK_SIZE, %esp
203 197
204 198 pushl $0x0 /* push a dead-end frame */
205 199 pushl $0x0
206 200 movl %esp, %ebp
207 201
208 202 pushl $0x0 /* clear all processor flags */
209 203 popf
210 204
211 205 /*
212 206 * setup a global descriptor table with known contents
213 207 */
214 208 lgdt gdt_info
215 209 movw $B32DATA_SEL, %ax
216 210 movw %ax, %ds
217 211 movw %ax, %es
218 212 movw %ax, %fs
219 213 movw %ax, %gs
220 214 movw %ax, %ss
221 215 ljmp $B32CODE_SEL, $newgdt
222 216 newgdt:
223 217 nop
224 218
225 219 /*
226 220 * go off and determine memory config, build page tables, etc.
227 221 */
228 222 call startup_kernel
229 223
230 224
231 225 /*
232 226 * On amd64 we'll want the stack pointer to be 16 byte aligned.
233 227 */
234 228 andl $0xfffffff0, %esp
235 229
236 230 /*
237 231 * Enable PGE, PAE and large pages
238 232 */
239 233 movl %cr4, %eax
240 234 testl $1, pge_support
241 235 jz 1f
242 236 orl $CR4_PGE, %eax
243 237 1:
244 238 testl $1, pae_support
245 239 jz 1f
246 240 orl $CR4_PAE, %eax
247 241 1:
248 242 testl $1, largepage_support
249 243 jz 1f
250 244 orl $CR4_PSE, %eax
251 245 1:
252 246 movl %eax, %cr4
253 247
254 248 /*
255 249 * enable NX protection if processor supports it
256 250 */
257 251 testl $1, NX_support
258 252 jz 1f
259 253 movl $MSR_AMD_EFER, %ecx
260 254 rdmsr
261 255 orl $AMD_EFER_NXE, %eax
262 256 wrmsr
263 257 1:
264 258
265 259
266 260 /*
267 261 * load the pagetable base address into cr3
268 262 */
269 263 movl top_page_table, %eax
270 264 movl %eax, %cr3
271 265
272 266 #if defined(_BOOT_TARGET_amd64)
273 267 /*
274 268 * enable long mode
275 269 */
276 270 movl $MSR_AMD_EFER, %ecx
277 271 rdmsr
278 272 orl $AMD_EFER_LME, %eax
279 273 wrmsr
280 274 #endif
281 275
282 276 /*
283 277 * enable paging, write protection, alignment masking, but disable
284 278 * the cache disable and write through only bits.
285 279 */
286 280 movl %cr0, %eax
287 281 orl $_CONST(CR0_PG | CR0_WP | CR0_AM), %eax
288 282 andl $_BITNOT(CR0_NW | CR0_CD), %eax
289 283 movl %eax, %cr0
290 284 jmp paging_on
291 285 paging_on:
292 286
293 287 /*
294 288 * The xboot_info ptr gets passed to the kernel as its argument
295 289 */
296 290 movl bi, %edi
297 291 movl entry_addr_low, %esi
298 292
299 293 #if defined(_BOOT_TARGET_i386)
300 294
301 295 pushl %edi
302 296 call *%esi
303 297
304 298 #elif defined(_BOOT_TARGET_amd64)
305 299
306 300 /*
307 301 * We're still in compatibility mode with 32 bit execution.
308 302 * Switch to 64 bit mode now by switching to a 64 bit code segment.
309 303 * then set up and do a lret to get into 64 bit execution.
310 304 */
311 305 pushl $B64CODE_SEL
312 306 pushl $longmode
313 307 lret
314 308 longmode:
315 309 .code64
316 310 movq $0xffffffff00000000,%rdx
317 311 orq %rdx, %rsi /* set upper bits of entry addr */
318 312 notq %rdx
319 313 andq %rdx, %rdi /* clean %rdi for passing arg */
320 314 call *%rsi
321 315
322 316 #else
323 317 #error "undefined target"
324 318 #endif
325 319
326 320 .code32
327 321
328 322 /*
329 323 * if reset fails halt the system
330 324 */
331 325 ENTRY_NP(dboot_halt)
332 326 hlt
333 327 SET_SIZE(dboot_halt)
334 328
335 329 /*
336 330 * flush the TLB
337 331 */
338 332 ENTRY_NP(reload_cr3)
339 333 movl %cr3, %eax
340 334 movl %eax, %cr3
341 335 ret
342 336 SET_SIZE(reload_cr3)
343 337
344 338 /*
345 339 * Detect if we can do cpuid, see if we can change bit 21 of eflags.
346 340 * Note we don't do the bizarre tests for Cyrix CPUs in ml/locore.s.
347 341 * If you're on such a CPU, you're stuck with non-PAE 32 bit kernels.
348 342 */
349 343 ENTRY_NP(have_cpuid)
350 344 pushf
351 345 pushf
352 346 xorl %eax, %eax
353 347 popl %ecx
354 348 movl %ecx, %edx
355 349 xorl $0x200000, %ecx
356 350 pushl %ecx
357 351 popf
358 352 pushf
359 353 popl %ecx
360 354 cmpl %ecx, %edx
361 355 setne %al
362 356 popf
363 357 ret
364 358 SET_SIZE(have_cpuid)
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365 359
366 360 /*
367 361 * We want the GDT to be on its own page for better performance
368 362 * running under hypervisors.
369 363 */
370 364 .skip 4096
371 365 #include "../boot/boot_gdt.s"
372 366 .skip 4096
373 367 .long 0
374 368
375 -#endif /* __lint */
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