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--- old/usr/src/uts/common/io/nxge/nxge_hcall.s
+++ new/usr/src/uts/common/io/nxge/nxge_hcall.s
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21
22 22 /*
23 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 /*
28 28 * Hypervisor calls called by niu leaf driver.
29 29 */
30 30
31 31 #include <sys/asm_linkage.h>
32 32 #include <sys/hypervisor_api.h>
33 33 #include <sys/nxge/nxge_impl.h>
34 34
35 35 #if defined(sun4v)
36 36
37 37 /*
38 38 * NIU HV API v1.0 definitions
39 39 */
40 40 #define N2NIU_RX_LP_SET 0x142
41 41 #define N2NIU_RX_LP_GET 0x143
42 42 #define N2NIU_TX_LP_SET 0x144
43 43 #define N2NIU_TX_LP_GET 0x145
44 44
45 45 /*
46 46 * NIU HV API v1.1 definitions
47 47 */
48 48 #define N2NIU_VR_ASSIGN 0x146
49 49 #define N2NIU_VR_UNASSIGN 0x147
50 50 #define N2NIU_VR_GETINFO 0x148
51 51
52 52 #define N2NIU_VR_RX_DMA_ASSIGN 0x149
53 53 #define N2NIU_VR_RX_DMA_UNASSIGN 0x14a
54 54 #define N2NIU_VR_TX_DMA_ASSIGN 0x14b
55 55 #define N2NIU_VR_TX_DMA_UNASSIGN 0x14c
56 56
57 57 #define N2NIU_VR_GET_RX_MAP 0x14d
58 58 #define N2NIU_VR_GET_TX_MAP 0x14e
59 59
60 60 #define N2NIU_VRRX_SET_INO 0x150
61 61 #define N2NIU_VRTX_SET_INO 0x151
62 62
63 63 #define N2NIU_VRRX_GET_INFO 0x152
64 64 #define N2NIU_VRTX_GET_INFO 0x153
65 65
66 66 #define N2NIU_VRRX_LP_SET 0x154
67 67 #define N2NIU_VRRX_LP_GET 0x155
68 68 #define N2NIU_VRTX_LP_SET 0x156
69 69 #define N2NIU_VRTX_LP_GET 0x157
70 70
71 71 #define N2NIU_VRRX_PARAM_GET 0x158
72 72 #define N2NIU_VRRX_PARAM_SET 0x159
73 73
74 74 #define N2NIU_VRTX_PARAM_GET 0x15a
75 75 #define N2NIU_VRTX_PARAM_SET 0x15b
76 76
77 77 /*
78 78 * The new set of HV APIs to provide the ability
79 79 * of a domain to manage multiple NIU resources at once to
|
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79 lines elided |
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80 80 * support the KT familty chip having up to 4 NIUs
81 81 * per system. The trap # will be the same as those defined
82 82 * before 2.0
83 83 */
84 84 #define N2NIU_CFGH_RX_LP_SET 0x142
85 85 #define N2NIU_CFGH_TX_LP_SET 0x143
86 86 #define N2NIU_CFGH_RX_LP_GET 0x144
87 87 #define N2NIU_CFGH_TX_LP_GET 0x145
88 88 #define N2NIU_CFGH_VR_ASSIGN 0x146
89 89
90 -#if defined(lint) || defined(__lint)
91 -
92 -/*ARGSUSED*/
93 -uint64_t
94 -hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
95 - uint64_t raddr, uint64_t size)
96 -{ return (0); }
97 -
98 -/*ARGSUSED*/
99 -uint64_t
100 -hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
101 - uint64_t *raddr, uint64_t *size)
102 -{ return (0); }
103 -
104 -/*ARGSUSED*/
105 -uint64_t
106 -hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
107 - uint64_t raddr, uint64_t size)
108 -{ return (0); }
109 -
110 -/*ARGSUSED*/
111 -uint64_t
112 -hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx,
113 - uint64_t *raddr, uint64_t *size)
114 -{ return (0); }
115 -
116 -/*ARGSUSED*/
117 -uint64_t
118 -hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie)
119 -{ return (0); }
120 -
121 -/*
122 - * KT: Interfaces functions which require the configuration handle
123 - */
124 -/*ARGSUSED*/
125 -uint64_t
126 -hv_niu_cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
127 - uint64_t raddr, uint64_t size)
128 -{ return (0); }
129 -
130 -/*ARGSUSED*/
131 -uint64_t
132 -hv_niu_cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
133 - uint64_t *raddr, uint64_t *size)
134 -{ return (0); }
135 -
136 -/*ARGSUSED*/
137 -uint64_t
138 -hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
139 - uint64_t raddr, uint64_t size)
140 -{ return (0); }
141 -
142 -/*ARGSUSED*/
143 -uint64_t
144 -hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
145 - uint64_t *raddr, uint64_t *size)
146 -{ return (0); }
147 -
148 -/*ARGSUSED*/
149 -uint64_t
150 -hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id, uint32_t *cookie)
151 -{ return (0); }
152 -
153 -/*ARGSUSED*/
154 -uint64_t
155 -hv_niu_vr_unassign(uint32_t cookie)
156 -{ return (0); }
157 -
158 -/*ARGSUSED*/
159 -uint64_t
160 -hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, uint64_t *size)
161 -{ return (0); }
162 -
163 -/*ARGSUSED*/
164 -uint64_t
165 -hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
166 -{ return (0); }
167 -
168 -/*ARGSUSED*/
169 -uint64_t
170 -hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
171 -{ return (0); }
172 -
173 -/*ARGSUSED*/
174 -uint64_t
175 -hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx)
176 -{ return (0); }
177 -
178 -/*ARGSUSED*/
179 -uint64_t
180 -hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx)
181 -{ return (0); }
182 -
183 -/*ARGSUSED*/
184 -uint64_t
185 -hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx)
186 -{ return (0); }
187 -
188 -/*ARGSUSED*/
189 -uint64_t
190 -hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx)
191 -{ return (0); }
192 -
193 -/*ARGSUSED*/
194 -uint64_t
195 -hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
196 - uint64_t raddr, uint64_t size)
197 -{ return (0); }
198 -
199 -/*ARGSUSED*/
200 -uint64_t
201 -hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
202 - uint64_t *raddr, uint64_t *size)
203 -{ return (0); }
204 -
205 -/*ARGSUSED*/
206 -uint64_t
207 -hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
208 - uint64_t raddr, uint64_t size)
209 -{ return (0); }
210 -
211 -/*ARGSUSED*/
212 -uint64_t
213 -hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
214 - uint64_t *raddr, uint64_t *size)
215 -{ return (0); }
216 -
217 -/*ARGSUSED*/
218 -uint64_t
219 -hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param,
220 - uint64_t *value)
221 -{ return (0); }
222 -
223 -/*ARGSUSED*/
224 -uint64_t
225 -hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param,
226 - uint64_t value)
227 -{ return (0); }
228 -
229 -/*ARGSUSED*/
230 -uint64_t
231 -hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param,
232 - uint64_t *value)
233 -{ return (0); }
234 -
235 -/*ARGSUSED*/
236 -uint64_t
237 -hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param,
238 - uint64_t value)
239 -{ return (0); }
240 -
241 -/*ARGSUSED*/
242 -uint64_t
243 -hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx,
244 - uint64_t *group, uint64_t *logdev)
245 -{ return (0); }
246 -
247 -/*ARGSUSED*/
248 -uint64_t
249 -hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx,
250 - uint64_t *group, uint64_t *logdev)
251 -{ return (0); }
252 -
253 -/*ARGSUSED*/
254 -uint64_t
255 -hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
256 -{ return (0); }
257 -
258 -/*ARGSUSED*/
259 -uint64_t
260 -hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
261 -{ return (0); }
262 -
263 -#else /* lint || __lint */
264 -
265 90 /*
266 91 * hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
267 92 * uint64_t raddr, uint64_t size)
268 93 */
269 94 ENTRY(hv_niu_rx_logical_page_conf)
270 95 mov N2NIU_RX_LP_CONF, %o5
271 96 ta FAST_TRAP
272 97 retl
273 98 nop
274 99 SET_SIZE(hv_niu_rx_logical_page_conf)
275 100
276 101 /*
277 102 * hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
278 103 * uint64_t *raddr, uint64_t *size)
279 104 */
280 105 ENTRY(hv_niu_rx_logical_page_info)
281 106 mov %o2, %g1
282 107 mov %o3, %g2
283 108 mov N2NIU_RX_LP_INFO, %o5
284 109 ta FAST_TRAP
285 110 stx %o1, [%g1]
286 111 retl
287 112 stx %o2, [%g2]
288 113 SET_SIZE(hv_niu_rx_logical_page_info)
289 114
290 115 /*
291 116 * hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
292 117 * uint64_t raddr, uint64_t size)
293 118 */
294 119 ENTRY(hv_niu_tx_logical_page_conf)
295 120 mov N2NIU_TX_LP_CONF, %o5
296 121 ta FAST_TRAP
297 122 retl
298 123 nop
299 124 SET_SIZE(hv_niu_tx_logical_page_conf)
300 125
301 126 /*
302 127 * hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx,
303 128 * uint64_t *raddr, uint64_t *size)
304 129 */
305 130 ENTRY(hv_niu_tx_logical_page_info)
306 131 mov %o2, %g1
307 132 mov %o3, %g2
308 133 mov N2NIU_TX_LP_INFO, %o5
309 134 ta FAST_TRAP
310 135 stx %o1, [%g1]
311 136 retl
312 137 stx %o2, [%g2]
313 138 SET_SIZE(hv_niu_tx_logical_page_info)
314 139
315 140 /*
316 141 * hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id,
317 142 * uint32_t *cookie)
318 143 */
319 144 ENTRY(hv_niu_vr_assign)
320 145 mov %o2, %g1
321 146 mov N2NIU_VR_ASSIGN, %o5
322 147 ta FAST_TRAP
323 148 retl
324 149 stw %o1, [%g1]
325 150 SET_SIZE(hv_niu_vr_assign)
326 151
327 152 /*
328 153 * hv_niu_vr_unassign(uint32_t cookie)
329 154 */
330 155 ENTRY(hv_niu_vr_unassign)
331 156 mov N2NIU_VR_UNASSIGN, %o5
332 157 ta FAST_TRAP
333 158 retl
334 159 nop
335 160 SET_SIZE(hv_niu_vr_unassign)
336 161
337 162 /*
338 163 * hv_niu_vr_getinfo(uint32_t cookie, uint64_t &real_start,
339 164 * uint64_t &size)
340 165 */
341 166 ENTRY(hv_niu_vr_getinfo)
342 167 mov %o1, %g1
343 168 mov %o2, %g2
344 169 mov N2NIU_VR_GETINFO, %o5
345 170 ta FAST_TRAP
346 171 stx %o1, [%g1]
347 172 retl
348 173 stx %o2, [%g2]
349 174 SET_SIZE(hv_niu_vr_getinfo)
350 175
351 176 /*
352 177 * hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
353 178 */
354 179 ENTRY(hv_niu_vr_get_rxmap)
355 180 mov %o1, %g1
356 181 mov N2NIU_VR_GET_RX_MAP, %o5
357 182 ta FAST_TRAP
358 183 retl
359 184 stx %o1, [%g1]
360 185 SET_SIZE(hv_niu_vr_get_rxmap)
361 186
362 187 /*
363 188 * hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
364 189 */
365 190 ENTRY(hv_niu_vr_get_txmap)
366 191 mov %o1, %g1
367 192 mov N2NIU_VR_GET_TX_MAP, %o5
368 193 ta FAST_TRAP
369 194 retl
370 195 stx %o1, [%g1]
371 196 SET_SIZE(hv_niu_vr_get_txmap)
372 197
373 198 /*
374 199 * hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx,
375 200 * uint64_t *vchidx)
376 201 */
377 202 ENTRY(hv_niu_rx_dma_assign)
378 203 mov %o2, %g1
379 204 mov N2NIU_VR_RX_DMA_ASSIGN, %o5
380 205 ta FAST_TRAP
381 206 retl
382 207 stx %o1, [%g1]
383 208 SET_SIZE(hv_niu_rx_dma_assign)
384 209
385 210 /*
386 211 * hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx)
387 212 */
388 213 ENTRY(hv_niu_rx_dma_unassign)
389 214 mov N2NIU_VR_RX_DMA_UNASSIGN, %o5
390 215 ta FAST_TRAP
391 216 retl
392 217 nop
393 218 SET_SIZE(hv_niu_rx_dma_unassign)
394 219
395 220 /*
396 221 * hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx,
397 222 * uint64_t *vchidx)
398 223 */
399 224 ENTRY(hv_niu_tx_dma_assign)
400 225 mov %o2, %g1
401 226 mov N2NIU_VR_TX_DMA_ASSIGN, %o5
402 227 ta FAST_TRAP
403 228 retl
404 229 stx %o1, [%g1]
405 230 SET_SIZE(hv_niu_tx_dma_assign)
406 231
407 232 /*
408 233 * hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t vchidx)
409 234 */
410 235 ENTRY(hv_niu_tx_dma_unassign)
411 236 mov N2NIU_VR_TX_DMA_UNASSIGN, %o5
412 237 ta FAST_TRAP
413 238 retl
414 239 nop
415 240 SET_SIZE(hv_niu_tx_dma_unassign)
416 241
417 242 /*
418 243 * hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx,
419 244 * uint64_t pgidx, uint64_t raddr, uint64_t size)
420 245 */
421 246 ENTRY(hv_niu_vrrx_logical_page_conf)
422 247 mov N2NIU_VRRX_LP_SET, %o5
423 248 ta FAST_TRAP
424 249 retl
425 250 nop
426 251 SET_SIZE(hv_niu_vrrx_logical_page_conf)
427 252
428 253 /*
429 254 * hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx,
430 255 * uint64_t pgidx, uint64_t *raddr, uint64_t *size)
431 256 */
432 257 ENTRY(hv_niu_vrrx_logical_page_info)
433 258 mov %o3, %g1
434 259 mov %o4, %g2
435 260 mov N2NIU_VRRX_LP_GET, %o5
436 261 ta FAST_TRAP
437 262 stx %o1, [%g1]
438 263 retl
439 264 stx %o2, [%g2]
440 265 SET_SIZE(hv_niu_vrrx_logical_page_info)
441 266
442 267 /*
443 268 * hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx,
444 269 * uint64_t pgidx, uint64_t raddr, uint64_t size)
445 270 */
446 271 ENTRY(hv_niu_vrtx_logical_page_conf)
447 272 mov N2NIU_VRTX_LP_SET, %o5
448 273 ta FAST_TRAP
449 274 retl
450 275 nop
451 276 SET_SIZE(hv_niu_vrtx_logical_page_conf)
452 277
453 278 /*
454 279 * hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx,
455 280 * uint64_t pgidx, uint64_t *raddr, uint64_t *size)
456 281 */
457 282 ENTRY(hv_niu_vrtx_logical_page_info)
458 283 mov %o3, %g1
459 284 mov %o4, %g2
460 285 mov N2NIU_VRTX_LP_GET, %o5
461 286 ta FAST_TRAP
462 287 stx %o1, [%g1]
463 288 retl
464 289 stx %o2, [%g2]
465 290 SET_SIZE(hv_niu_vrtx_logical_page_info)
466 291
467 292 /*
468 293 * hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx,
469 294 * uint64_t *group, uint64_t *logdev)
470 295 */
471 296 ENTRY(hv_niu_vrrx_getinfo)
472 297 mov %o2, %g1
473 298 mov %o3, %g2
474 299 mov N2NIU_VRRX_GET_INFO, %o5
475 300 ta FAST_TRAP
476 301 stx %o2, [%g2]
477 302 retl
478 303 stx %o1, [%g1]
479 304 SET_SIZE(hv_niu_vrrx_getinfo)
480 305
481 306 /*
482 307 * hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx,
483 308 * uint64_t *group, uint64_t *logdev)
484 309 */
485 310 ENTRY(hv_niu_vrtx_getinfo)
486 311 mov %o2, %g1
487 312 mov %o3, %g2
488 313 mov N2NIU_VRTX_GET_INFO, %o5
489 314 ta FAST_TRAP
490 315 stx %o2, [%g2]
491 316 retl
492 317 stx %o1, [%g1]
493 318 SET_SIZE(hv_niu_vrtx_getinfo)
494 319
495 320 /*
496 321 * hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
497 322 */
498 323 ENTRY(hv_niu_vrrx_set_ino)
499 324 mov N2NIU_VRRX_SET_INO, %o5
500 325 ta FAST_TRAP
501 326 retl
502 327 nop
503 328 SET_SIZE(hv_niu_vrrx_set_ino)
504 329
505 330 /*
506 331 * hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
507 332 */
508 333 ENTRY(hv_niu_vrtx_set_ino)
509 334 mov N2NIU_VRTX_SET_INO, %o5
510 335 ta FAST_TRAP
511 336 retl
512 337 nop
513 338 SET_SIZE(hv_niu_vrtx_set_ino)
514 339
515 340 /*
516 341 * hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx,
517 342 * uint64_t param, uint64_t *value)
518 343 *
519 344 */
520 345 ENTRY(hv_niu_vrrx_param_get)
521 346 mov %o3, %g1
522 347 mov N2NIU_VRRX_PARAM_GET, %o5
523 348 ta FAST_TRAP
524 349 retl
525 350 stx %o1, [%g1]
526 351 SET_SIZE(hv_niu_vrrx_param_get)
527 352
528 353 /*
529 354 * hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx,
530 355 * uint64_t param, uint64_t value)
531 356 *
532 357 */
533 358 ENTRY(hv_niu_vrrx_param_set)
534 359 mov N2NIU_VRRX_PARAM_SET, %o5
535 360 ta FAST_TRAP
536 361 retl
537 362 nop
538 363 SET_SIZE(hv_niu_vrrx_param_set)
539 364
540 365 /*
541 366 * hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx,
542 367 * uint64_t param, uint64_t *value)
543 368 *
544 369 */
545 370 ENTRY(hv_niu_vrtx_param_get)
546 371 mov %o3, %g1
547 372 mov N2NIU_VRTX_PARAM_GET, %o5
548 373 ta FAST_TRAP
549 374 retl
550 375 stx %o1, [%g1]
551 376 SET_SIZE(hv_niu_vrtx_param_get)
552 377
553 378 /*
554 379 * hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx,
555 380 * uint64_t param, uint64_t value)
556 381 *
557 382 */
558 383 ENTRY(hv_niu_vrtx_param_set)
559 384 mov N2NIU_VRTX_PARAM_SET, %o5
560 385 ta FAST_TRAP
561 386 retl
562 387 nop
563 388 SET_SIZE(hv_niu_vrtx_param_set)
564 389
565 390 /*
566 391 * Interfaces functions which require the configuration handle.
567 392 */
568 393 /*
569 394 * hv_niu__cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
570 395 * uint64_t pgidx, uint64_t raddr, uint64_t size)
571 396 */
572 397 ENTRY(hv_niu_cfgh_rx_logical_page_conf)
573 398 mov N2NIU_RX_LP_CONF, %o5
574 399 ta FAST_TRAP
575 400 retl
576 401 nop
577 402 SET_SIZE(hv_niu_cfgh_rx_logical_page_conf)
578 403
579 404 /*
580 405 * hv_niu__cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx,
581 406 * uint64_t pgidx, uint64_t *raddr, uint64_t *size)
582 407 */
583 408 ENTRY(hv_niu_cfgh_rx_logical_page_info)
584 409 mov %o3, %g1
585 410 mov %o4, %g2
586 411 mov N2NIU_RX_LP_INFO, %o5
587 412 ta FAST_TRAP
588 413 stx %o1, [%g1]
589 414 retl
590 415 stx %o2, [%g2]
591 416 SET_SIZE(hv_niu_cfgh_rx_logical_page_info)
592 417
593 418 /*
594 419 * hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
595 420 * uint64_t pgidx, uint64_t raddr, uint64_t size)
596 421 */
597 422 ENTRY(hv_niu_cfgh_tx_logical_page_conf)
598 423 mov N2NIU_TX_LP_CONF, %o5
599 424 ta FAST_TRAP
600 425 retl
601 426 nop
602 427 SET_SIZE(hv_niu_cfgh_tx_logical_page_conf)
603 428
604 429 /*
605 430 * hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx,
606 431 * uint64_t pgidx, uint64_t *raddr, uint64_t *size)
607 432 */
608 433 ENTRY(hv_niu_cfgh_tx_logical_page_info)
609 434 mov %o3, %g1
610 435 mov %o4, %g2
611 436 mov N2NIU_TX_LP_INFO, %o5
612 437 ta FAST_TRAP
613 438 stx %o1, [%g1]
614 439 retl
615 440 stx %o2, [%g2]
616 441 SET_SIZE(hv_niu_cfgh_tx_logical_page_info)
617 442
618 443 /*
619 444 * hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id,
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620 445 * uint32_t *cookie)
621 446 */
622 447 ENTRY(hv_niu_cfgh_vr_assign)
623 448 mov %o3, %g1
624 449 mov N2NIU_VR_ASSIGN, %o5
625 450 ta FAST_TRAP
626 451 retl
627 452 stw %o1, [%g1]
628 453 SET_SIZE(hv_niu_cfgh_vr_assign)
629 454
630 -#endif /* lint || __lint */
631 -
632 455 #endif /*defined(sun4v)*/
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