70
71 #define N2NIU_VRRX_PARAM_GET 0x158
72 #define N2NIU_VRRX_PARAM_SET 0x159
73
74 #define N2NIU_VRTX_PARAM_GET 0x15a
75 #define N2NIU_VRTX_PARAM_SET 0x15b
76
77 /*
78 * The new set of HV APIs to provide the ability
79 * of a domain to manage multiple NIU resources at once to
80 * support the KT familty chip having up to 4 NIUs
81 * per system. The trap # will be the same as those defined
82 * before 2.0
83 */
84 #define N2NIU_CFGH_RX_LP_SET 0x142
85 #define N2NIU_CFGH_TX_LP_SET 0x143
86 #define N2NIU_CFGH_RX_LP_GET 0x144
87 #define N2NIU_CFGH_TX_LP_GET 0x145
88 #define N2NIU_CFGH_VR_ASSIGN 0x146
89
90 #if defined(lint) || defined(__lint)
91
92 /*ARGSUSED*/
93 uint64_t
94 hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
95 uint64_t raddr, uint64_t size)
96 { return (0); }
97
98 /*ARGSUSED*/
99 uint64_t
100 hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
101 uint64_t *raddr, uint64_t *size)
102 { return (0); }
103
104 /*ARGSUSED*/
105 uint64_t
106 hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
107 uint64_t raddr, uint64_t size)
108 { return (0); }
109
110 /*ARGSUSED*/
111 uint64_t
112 hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx,
113 uint64_t *raddr, uint64_t *size)
114 { return (0); }
115
116 /*ARGSUSED*/
117 uint64_t
118 hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie)
119 { return (0); }
120
121 /*
122 * KT: Interfaces functions which require the configuration handle
123 */
124 /*ARGSUSED*/
125 uint64_t
126 hv_niu_cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
127 uint64_t raddr, uint64_t size)
128 { return (0); }
129
130 /*ARGSUSED*/
131 uint64_t
132 hv_niu_cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
133 uint64_t *raddr, uint64_t *size)
134 { return (0); }
135
136 /*ARGSUSED*/
137 uint64_t
138 hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
139 uint64_t raddr, uint64_t size)
140 { return (0); }
141
142 /*ARGSUSED*/
143 uint64_t
144 hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
145 uint64_t *raddr, uint64_t *size)
146 { return (0); }
147
148 /*ARGSUSED*/
149 uint64_t
150 hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id, uint32_t *cookie)
151 { return (0); }
152
153 /*ARGSUSED*/
154 uint64_t
155 hv_niu_vr_unassign(uint32_t cookie)
156 { return (0); }
157
158 /*ARGSUSED*/
159 uint64_t
160 hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, uint64_t *size)
161 { return (0); }
162
163 /*ARGSUSED*/
164 uint64_t
165 hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
166 { return (0); }
167
168 /*ARGSUSED*/
169 uint64_t
170 hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
171 { return (0); }
172
173 /*ARGSUSED*/
174 uint64_t
175 hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx)
176 { return (0); }
177
178 /*ARGSUSED*/
179 uint64_t
180 hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx)
181 { return (0); }
182
183 /*ARGSUSED*/
184 uint64_t
185 hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx)
186 { return (0); }
187
188 /*ARGSUSED*/
189 uint64_t
190 hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx)
191 { return (0); }
192
193 /*ARGSUSED*/
194 uint64_t
195 hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
196 uint64_t raddr, uint64_t size)
197 { return (0); }
198
199 /*ARGSUSED*/
200 uint64_t
201 hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
202 uint64_t *raddr, uint64_t *size)
203 { return (0); }
204
205 /*ARGSUSED*/
206 uint64_t
207 hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
208 uint64_t raddr, uint64_t size)
209 { return (0); }
210
211 /*ARGSUSED*/
212 uint64_t
213 hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
214 uint64_t *raddr, uint64_t *size)
215 { return (0); }
216
217 /*ARGSUSED*/
218 uint64_t
219 hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param,
220 uint64_t *value)
221 { return (0); }
222
223 /*ARGSUSED*/
224 uint64_t
225 hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param,
226 uint64_t value)
227 { return (0); }
228
229 /*ARGSUSED*/
230 uint64_t
231 hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param,
232 uint64_t *value)
233 { return (0); }
234
235 /*ARGSUSED*/
236 uint64_t
237 hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param,
238 uint64_t value)
239 { return (0); }
240
241 /*ARGSUSED*/
242 uint64_t
243 hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx,
244 uint64_t *group, uint64_t *logdev)
245 { return (0); }
246
247 /*ARGSUSED*/
248 uint64_t
249 hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx,
250 uint64_t *group, uint64_t *logdev)
251 { return (0); }
252
253 /*ARGSUSED*/
254 uint64_t
255 hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
256 { return (0); }
257
258 /*ARGSUSED*/
259 uint64_t
260 hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
261 { return (0); }
262
263 #else /* lint || __lint */
264
265 /*
266 * hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
267 * uint64_t raddr, uint64_t size)
268 */
269 ENTRY(hv_niu_rx_logical_page_conf)
270 mov N2NIU_RX_LP_CONF, %o5
271 ta FAST_TRAP
272 retl
273 nop
274 SET_SIZE(hv_niu_rx_logical_page_conf)
275
276 /*
277 * hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
278 * uint64_t *raddr, uint64_t *size)
279 */
280 ENTRY(hv_niu_rx_logical_page_info)
281 mov %o2, %g1
282 mov %o3, %g2
283 mov N2NIU_RX_LP_INFO, %o5
284 ta FAST_TRAP
610 mov %o4, %g2
611 mov N2NIU_TX_LP_INFO, %o5
612 ta FAST_TRAP
613 stx %o1, [%g1]
614 retl
615 stx %o2, [%g2]
616 SET_SIZE(hv_niu_cfgh_tx_logical_page_info)
617
618 /*
619 * hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id,
620 * uint32_t *cookie)
621 */
622 ENTRY(hv_niu_cfgh_vr_assign)
623 mov %o3, %g1
624 mov N2NIU_VR_ASSIGN, %o5
625 ta FAST_TRAP
626 retl
627 stw %o1, [%g1]
628 SET_SIZE(hv_niu_cfgh_vr_assign)
629
630 #endif /* lint || __lint */
631
632 #endif /*defined(sun4v)*/
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70
71 #define N2NIU_VRRX_PARAM_GET 0x158
72 #define N2NIU_VRRX_PARAM_SET 0x159
73
74 #define N2NIU_VRTX_PARAM_GET 0x15a
75 #define N2NIU_VRTX_PARAM_SET 0x15b
76
77 /*
78 * The new set of HV APIs to provide the ability
79 * of a domain to manage multiple NIU resources at once to
80 * support the KT familty chip having up to 4 NIUs
81 * per system. The trap # will be the same as those defined
82 * before 2.0
83 */
84 #define N2NIU_CFGH_RX_LP_SET 0x142
85 #define N2NIU_CFGH_TX_LP_SET 0x143
86 #define N2NIU_CFGH_RX_LP_GET 0x144
87 #define N2NIU_CFGH_TX_LP_GET 0x145
88 #define N2NIU_CFGH_VR_ASSIGN 0x146
89
90 /*
91 * hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
92 * uint64_t raddr, uint64_t size)
93 */
94 ENTRY(hv_niu_rx_logical_page_conf)
95 mov N2NIU_RX_LP_CONF, %o5
96 ta FAST_TRAP
97 retl
98 nop
99 SET_SIZE(hv_niu_rx_logical_page_conf)
100
101 /*
102 * hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
103 * uint64_t *raddr, uint64_t *size)
104 */
105 ENTRY(hv_niu_rx_logical_page_info)
106 mov %o2, %g1
107 mov %o3, %g2
108 mov N2NIU_RX_LP_INFO, %o5
109 ta FAST_TRAP
435 mov %o4, %g2
436 mov N2NIU_TX_LP_INFO, %o5
437 ta FAST_TRAP
438 stx %o1, [%g1]
439 retl
440 stx %o2, [%g2]
441 SET_SIZE(hv_niu_cfgh_tx_logical_page_info)
442
443 /*
444 * hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id,
445 * uint32_t *cookie)
446 */
447 ENTRY(hv_niu_cfgh_vr_assign)
448 mov %o3, %g1
449 mov N2NIU_VR_ASSIGN, %o5
450 ta FAST_TRAP
451 retl
452 stw %o1, [%g1]
453 SET_SIZE(hv_niu_cfgh_vr_assign)
454
455 #endif /*defined(sun4v)*/
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