1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 
  22 /*
  23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26 
  27 /*
  28  * Hypervisor calls called by niu leaf driver.
  29  */
  30 
  31 #include <sys/asm_linkage.h>
  32 #include <sys/hypervisor_api.h>
  33 #include <sys/nxge/nxge_impl.h>
  34 
  35 #if defined(sun4v)
  36 
  37 /*
  38  * NIU HV API v1.0 definitions
  39  */
  40 #define N2NIU_RX_LP_SET         0x142
  41 #define N2NIU_RX_LP_GET         0x143
  42 #define N2NIU_TX_LP_SET         0x144
  43 #define N2NIU_TX_LP_GET         0x145
  44 
  45 /*
  46  * NIU HV API v1.1 definitions
  47  */
  48 #define N2NIU_VR_ASSIGN         0x146
  49 #define N2NIU_VR_UNASSIGN       0x147
  50 #define N2NIU_VR_GETINFO        0x148
  51 
  52 #define N2NIU_VR_RX_DMA_ASSIGN          0x149
  53 #define N2NIU_VR_RX_DMA_UNASSIGN        0x14a
  54 #define N2NIU_VR_TX_DMA_ASSIGN          0x14b
  55 #define N2NIU_VR_TX_DMA_UNASSIGN        0x14c
  56 
  57 #define N2NIU_VR_GET_RX_MAP     0x14d
  58 #define N2NIU_VR_GET_TX_MAP     0x14e
  59 
  60 #define N2NIU_VRRX_SET_INO      0x150
  61 #define N2NIU_VRTX_SET_INO      0x151
  62 
  63 #define N2NIU_VRRX_GET_INFO     0x152
  64 #define N2NIU_VRTX_GET_INFO     0x153
  65 
  66 #define N2NIU_VRRX_LP_SET       0x154
  67 #define N2NIU_VRRX_LP_GET       0x155
  68 #define N2NIU_VRTX_LP_SET       0x156
  69 #define N2NIU_VRTX_LP_GET       0x157
  70 
  71 #define N2NIU_VRRX_PARAM_GET    0x158
  72 #define N2NIU_VRRX_PARAM_SET    0x159
  73 
  74 #define N2NIU_VRTX_PARAM_GET    0x15a
  75 #define N2NIU_VRTX_PARAM_SET    0x15b
  76 
  77 /*
  78  * The new set of HV APIs to provide the ability
  79  * of a domain to manage multiple NIU resources at once to
  80  * support the KT familty chip having up to 4 NIUs
  81  * per system. The trap # will be the same as those defined
  82  * before 2.0
  83  */
  84 #define N2NIU_CFGH_RX_LP_SET    0x142
  85 #define N2NIU_CFGH_TX_LP_SET    0x143
  86 #define N2NIU_CFGH_RX_LP_GET    0x144
  87 #define N2NIU_CFGH_TX_LP_GET    0x145
  88 #define N2NIU_CFGH_VR_ASSIGN    0x146
  89 
  90 #if defined(lint) || defined(__lint)
  91 
  92 /*ARGSUSED*/
  93 uint64_t
  94 hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
  95         uint64_t raddr, uint64_t size)
  96 { return (0); }
  97 
  98 /*ARGSUSED*/
  99 uint64_t
 100 hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
 101         uint64_t *raddr, uint64_t *size)
 102 { return (0); }
 103 
 104 /*ARGSUSED*/
 105 uint64_t
 106 hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
 107         uint64_t raddr, uint64_t size)
 108 { return (0); }
 109 
 110 /*ARGSUSED*/
 111 uint64_t
 112 hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx,
 113         uint64_t *raddr, uint64_t *size)
 114 { return (0); }
 115 
 116 /*ARGSUSED*/
 117 uint64_t
 118 hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id, uint32_t *cookie)
 119 { return (0); }
 120 
 121 /*
 122  * KT: Interfaces functions which require the configuration handle
 123  */
 124 /*ARGSUSED*/
 125 uint64_t
 126 hv_niu_cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
 127         uint64_t raddr, uint64_t size)
 128 { return (0); }
 129 
 130 /*ARGSUSED*/
 131 uint64_t
 132 hv_niu_cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
 133         uint64_t *raddr, uint64_t *size)
 134 { return (0); }
 135 
 136 /*ARGSUSED*/
 137 uint64_t
 138 hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
 139         uint64_t raddr, uint64_t size)
 140 { return (0); }
 141 
 142 /*ARGSUSED*/
 143 uint64_t
 144 hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx, uint64_t pgidx,
 145         uint64_t *raddr, uint64_t *size)
 146 { return (0); }
 147 
 148 /*ARGSUSED*/
 149 uint64_t
 150 hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id, uint32_t *cookie)
 151 { return (0); }
 152 
 153 /*ARGSUSED*/
 154 uint64_t
 155 hv_niu_vr_unassign(uint32_t cookie)
 156 { return (0); }
 157 
 158 /*ARGSUSED*/
 159 uint64_t
 160 hv_niu_vr_getinfo(uint32_t cookie, uint64_t *real_start, uint64_t *size)
 161 { return (0); }
 162 
 163 /*ARGSUSED*/
 164 uint64_t
 165 hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
 166 { return (0); }
 167 
 168 /*ARGSUSED*/
 169 uint64_t
 170 hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
 171 { return (0); }
 172 
 173 /*ARGSUSED*/
 174 uint64_t
 175 hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx)
 176 { return (0); }
 177 
 178 /*ARGSUSED*/
 179 uint64_t
 180 hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx)
 181 { return (0); }
 182 
 183 /*ARGSUSED*/
 184 uint64_t
 185 hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx, uint64_t *vchidx)
 186 { return (0); }
 187 
 188 /*ARGSUSED*/
 189 uint64_t
 190 hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t chidx)
 191 { return (0); }
 192 
 193 /*ARGSUSED*/
 194 uint64_t
 195 hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
 196     uint64_t raddr, uint64_t size)
 197 { return (0); }
 198 
 199 /*ARGSUSED*/
 200 uint64_t
 201 hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
 202     uint64_t *raddr, uint64_t *size)
 203 { return (0); }
 204 
 205 /*ARGSUSED*/
 206 uint64_t
 207 hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
 208     uint64_t raddr, uint64_t size)
 209 { return (0); }
 210 
 211 /*ARGSUSED*/
 212 uint64_t
 213 hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx, uint64_t pgidx,
 214     uint64_t *raddr, uint64_t *size)
 215 { return (0); }
 216 
 217 /*ARGSUSED*/
 218 uint64_t
 219 hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param,
 220         uint64_t *value)
 221 { return (0); }
 222 
 223 /*ARGSUSED*/
 224 uint64_t
 225 hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param,
 226         uint64_t value)
 227 { return (0); }
 228 
 229 /*ARGSUSED*/
 230 uint64_t
 231 hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx, uint64_t param,
 232         uint64_t *value)
 233 { return (0); }
 234 
 235 /*ARGSUSED*/
 236 uint64_t
 237 hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx, uint64_t param,
 238         uint64_t value)
 239 { return (0); }
 240 
 241 /*ARGSUSED*/
 242 uint64_t
 243 hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx,
 244         uint64_t *group, uint64_t *logdev)
 245 { return (0); }
 246 
 247 /*ARGSUSED*/
 248 uint64_t
 249 hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx,
 250                 uint64_t *group, uint64_t *logdev)
 251 { return (0); }
 252 
 253 /*ARGSUSED*/
 254 uint64_t
 255 hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
 256 { return (0); }
 257 
 258 /*ARGSUSED*/
 259 uint64_t
 260 hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
 261 { return (0); }
 262 
 263 #else   /* lint || __lint */
 264 
 265         /*
 266          * hv_niu_rx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
 267          *      uint64_t raddr, uint64_t size)
 268          */
 269         ENTRY(hv_niu_rx_logical_page_conf)
 270         mov     N2NIU_RX_LP_CONF, %o5
 271         ta      FAST_TRAP
 272         retl
 273         nop
 274         SET_SIZE(hv_niu_rx_logical_page_conf)
 275 
 276         /*
 277          * hv_niu_rx_logical_page_info(uint64_t chidx, uint64_t pgidx,
 278          *      uint64_t *raddr, uint64_t *size)
 279          */
 280         ENTRY(hv_niu_rx_logical_page_info)
 281         mov     %o2, %g1
 282         mov     %o3, %g2
 283         mov     N2NIU_RX_LP_INFO, %o5
 284         ta      FAST_TRAP
 285         stx     %o1, [%g1]
 286         retl
 287         stx     %o2, [%g2]
 288         SET_SIZE(hv_niu_rx_logical_page_info)
 289 
 290         /*
 291          * hv_niu_tx_logical_page_conf(uint64_t chidx, uint64_t pgidx,
 292          *      uint64_t raddr, uint64_t size)
 293          */
 294         ENTRY(hv_niu_tx_logical_page_conf)
 295         mov     N2NIU_TX_LP_CONF, %o5
 296         ta      FAST_TRAP
 297         retl
 298         nop
 299         SET_SIZE(hv_niu_tx_logical_page_conf)
 300 
 301         /*
 302          * hv_niu_tx_logical_page_info(uint64_t chidx, uint64_t pgidx,
 303          *      uint64_t *raddr, uint64_t *size)
 304          */
 305         ENTRY(hv_niu_tx_logical_page_info)
 306         mov     %o2, %g1
 307         mov     %o3, %g2
 308         mov     N2NIU_TX_LP_INFO, %o5
 309         ta      FAST_TRAP
 310         stx     %o1, [%g1]
 311         retl
 312         stx     %o2, [%g2]
 313         SET_SIZE(hv_niu_tx_logical_page_info)
 314 
 315         /*
 316          * hv_niu_vr_assign(uint64_t vridx, uint64_t ldc_id,
 317          *      uint32_t *cookie)
 318          */
 319         ENTRY(hv_niu_vr_assign)
 320         mov     %o2, %g1
 321         mov     N2NIU_VR_ASSIGN, %o5
 322         ta      FAST_TRAP
 323         retl
 324         stw     %o1, [%g1]
 325         SET_SIZE(hv_niu_vr_assign)
 326 
 327         /*
 328          * hv_niu_vr_unassign(uint32_t cookie)
 329          */
 330         ENTRY(hv_niu_vr_unassign)
 331         mov     N2NIU_VR_UNASSIGN, %o5
 332         ta      FAST_TRAP
 333         retl
 334         nop
 335         SET_SIZE(hv_niu_vr_unassign)
 336 
 337         /*
 338          * hv_niu_vr_getinfo(uint32_t cookie, uint64_t &real_start,
 339          *      uint64_t &size)
 340          */
 341         ENTRY(hv_niu_vr_getinfo)
 342         mov     %o1, %g1
 343         mov     %o2, %g2
 344         mov     N2NIU_VR_GETINFO, %o5
 345         ta      FAST_TRAP
 346         stx     %o1, [%g1]
 347         retl
 348         stx     %o2, [%g2]
 349         SET_SIZE(hv_niu_vr_getinfo)
 350 
 351         /*
 352          * hv_niu_vr_get_rxmap(uint32_t cookie, uint64_t *dma_map)
 353          */
 354         ENTRY(hv_niu_vr_get_rxmap)
 355         mov     %o1, %g1
 356         mov     N2NIU_VR_GET_RX_MAP, %o5
 357         ta      FAST_TRAP
 358         retl
 359         stx     %o1, [%g1]
 360         SET_SIZE(hv_niu_vr_get_rxmap)
 361 
 362         /*
 363          * hv_niu_vr_get_txmap(uint32_t cookie, uint64_t *dma_map)
 364          */
 365         ENTRY(hv_niu_vr_get_txmap)
 366         mov     %o1, %g1
 367         mov     N2NIU_VR_GET_TX_MAP, %o5
 368         ta      FAST_TRAP
 369         retl
 370         stx     %o1, [%g1]
 371         SET_SIZE(hv_niu_vr_get_txmap)
 372 
 373         /*
 374          * hv_niu_rx_dma_assign(uint32_t cookie, uint64_t chidx,
 375          *      uint64_t *vchidx)
 376          */
 377         ENTRY(hv_niu_rx_dma_assign)
 378         mov     %o2, %g1
 379         mov     N2NIU_VR_RX_DMA_ASSIGN, %o5
 380         ta      FAST_TRAP
 381         retl
 382         stx     %o1, [%g1]
 383         SET_SIZE(hv_niu_rx_dma_assign)
 384 
 385         /*
 386          * hv_niu_rx_dma_unassign(uint32_t cookie, uint64_t vchidx)
 387          */
 388         ENTRY(hv_niu_rx_dma_unassign)
 389         mov     N2NIU_VR_RX_DMA_UNASSIGN, %o5
 390         ta      FAST_TRAP
 391         retl
 392         nop
 393         SET_SIZE(hv_niu_rx_dma_unassign)
 394 
 395         /*
 396          * hv_niu_tx_dma_assign(uint32_t cookie, uint64_t chidx,
 397          *      uint64_t *vchidx)
 398          */
 399         ENTRY(hv_niu_tx_dma_assign)
 400         mov     %o2, %g1
 401         mov     N2NIU_VR_TX_DMA_ASSIGN, %o5
 402         ta      FAST_TRAP
 403         retl
 404         stx     %o1, [%g1]
 405         SET_SIZE(hv_niu_tx_dma_assign)
 406 
 407         /*
 408          * hv_niu_tx_dma_unassign(uint32_t cookie, uint64_t vchidx)
 409          */
 410         ENTRY(hv_niu_tx_dma_unassign)
 411         mov     N2NIU_VR_TX_DMA_UNASSIGN, %o5
 412         ta      FAST_TRAP
 413         retl
 414         nop
 415         SET_SIZE(hv_niu_tx_dma_unassign)
 416 
 417         /*
 418          * hv_niu_vrrx_logical_page_conf(uint32_t cookie, uint64_t chidx,
 419          *      uint64_t pgidx, uint64_t raddr, uint64_t size)
 420          */
 421         ENTRY(hv_niu_vrrx_logical_page_conf)
 422         mov     N2NIU_VRRX_LP_SET, %o5
 423         ta      FAST_TRAP
 424         retl
 425         nop
 426         SET_SIZE(hv_niu_vrrx_logical_page_conf)
 427 
 428         /*
 429          * hv_niu_vrrx_logical_page_info(uint32_t cookie, uint64_t chidx,
 430          *      uint64_t pgidx, uint64_t *raddr, uint64_t *size)
 431          */
 432         ENTRY(hv_niu_vrrx_logical_page_info)
 433         mov     %o3, %g1
 434         mov     %o4, %g2
 435         mov     N2NIU_VRRX_LP_GET, %o5
 436         ta      FAST_TRAP
 437         stx     %o1, [%g1]
 438         retl
 439         stx     %o2, [%g2]
 440         SET_SIZE(hv_niu_vrrx_logical_page_info)
 441 
 442         /*
 443          * hv_niu_vrtx_logical_page_conf(uint32_t cookie, uint64_t chidx,
 444          *      uint64_t pgidx, uint64_t raddr, uint64_t size)
 445          */
 446         ENTRY(hv_niu_vrtx_logical_page_conf)
 447         mov     N2NIU_VRTX_LP_SET, %o5
 448         ta      FAST_TRAP
 449         retl
 450         nop
 451         SET_SIZE(hv_niu_vrtx_logical_page_conf)
 452 
 453         /*
 454          * hv_niu_vrtx_logical_page_info(uint32_t cookie, uint64_t chidx,
 455          *      uint64_t pgidx, uint64_t *raddr, uint64_t *size)
 456          */
 457         ENTRY(hv_niu_vrtx_logical_page_info)
 458         mov     %o3, %g1
 459         mov     %o4, %g2
 460         mov     N2NIU_VRTX_LP_GET, %o5
 461         ta      FAST_TRAP
 462         stx     %o1, [%g1]
 463         retl
 464         stx     %o2, [%g2]
 465         SET_SIZE(hv_niu_vrtx_logical_page_info)
 466 
 467         /*
 468          * hv_niu_vrrx_getinfo(uint32_t cookie, uint64_t vridx,
 469          *      uint64_t *group, uint64_t *logdev)
 470          */
 471         ENTRY(hv_niu_vrrx_getinfo)
 472         mov     %o2, %g1
 473         mov     %o3, %g2
 474         mov     N2NIU_VRRX_GET_INFO, %o5
 475         ta      FAST_TRAP
 476         stx     %o2, [%g2]
 477         retl
 478         stx     %o1, [%g1]
 479         SET_SIZE(hv_niu_vrrx_getinfo)
 480 
 481         /*
 482          * hv_niu_vrtx_getinfo(uint32_t cookie, uint64_t vridx,
 483          *      uint64_t *group, uint64_t *logdev)
 484          */
 485         ENTRY(hv_niu_vrtx_getinfo)
 486         mov     %o2, %g1
 487         mov     %o3, %g2
 488         mov     N2NIU_VRTX_GET_INFO, %o5
 489         ta      FAST_TRAP
 490         stx     %o2, [%g2]
 491         retl
 492         stx     %o1, [%g1]
 493         SET_SIZE(hv_niu_vrtx_getinfo)
 494 
 495         /*
 496          * hv_niu_vrrx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
 497          */
 498         ENTRY(hv_niu_vrrx_set_ino)
 499         mov     N2NIU_VRRX_SET_INO, %o5
 500         ta      FAST_TRAP
 501         retl
 502         nop
 503         SET_SIZE(hv_niu_vrrx_set_ino)
 504 
 505         /*
 506          * hv_niu_vrtx_set_ino(uint32_t cookie, uint64_t vridx, uint32_t ino)
 507          */
 508         ENTRY(hv_niu_vrtx_set_ino)
 509         mov     N2NIU_VRTX_SET_INO, %o5
 510         ta      FAST_TRAP
 511         retl
 512         nop
 513         SET_SIZE(hv_niu_vrtx_set_ino)
 514 
 515         /*
 516          * hv_niu_vrrx_param_get(uint32_t cookie, uint64_t vridx,
 517          *      uint64_t param, uint64_t *value)
 518          *
 519          */
 520         ENTRY(hv_niu_vrrx_param_get)
 521         mov     %o3, %g1
 522         mov     N2NIU_VRRX_PARAM_GET, %o5
 523         ta      FAST_TRAP
 524         retl
 525         stx     %o1, [%g1]
 526         SET_SIZE(hv_niu_vrrx_param_get)
 527 
 528         /*
 529          * hv_niu_vrrx_param_set(uint32_t cookie, uint64_t vridx,
 530          *      uint64_t param, uint64_t value)
 531          *
 532          */
 533         ENTRY(hv_niu_vrrx_param_set)
 534         mov     N2NIU_VRRX_PARAM_SET, %o5
 535         ta      FAST_TRAP
 536         retl
 537         nop
 538         SET_SIZE(hv_niu_vrrx_param_set)
 539 
 540         /*
 541          * hv_niu_vrtx_param_get(uint32_t cookie, uint64_t vridx,
 542          *      uint64_t param, uint64_t *value)
 543          *
 544          */
 545         ENTRY(hv_niu_vrtx_param_get)
 546         mov     %o3, %g1
 547         mov     N2NIU_VRTX_PARAM_GET, %o5
 548         ta      FAST_TRAP
 549         retl
 550         stx     %o1, [%g1]
 551         SET_SIZE(hv_niu_vrtx_param_get)
 552 
 553         /*
 554          * hv_niu_vrtx_param_set(uint32_t cookie, uint64_t vridx,
 555          *      uint64_t param, uint64_t value)
 556          *
 557          */
 558         ENTRY(hv_niu_vrtx_param_set)
 559         mov     N2NIU_VRTX_PARAM_SET, %o5
 560         ta      FAST_TRAP
 561         retl
 562         nop
 563         SET_SIZE(hv_niu_vrtx_param_set)
 564 
 565         /*
 566          * Interfaces functions which require the configuration handle.
 567          */
 568         /*
 569          * hv_niu__cfgh_rx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
 570          *    uint64_t pgidx, uint64_t raddr, uint64_t size)
 571          */
 572         ENTRY(hv_niu_cfgh_rx_logical_page_conf)
 573         mov     N2NIU_RX_LP_CONF, %o5
 574         ta      FAST_TRAP
 575         retl
 576         nop
 577         SET_SIZE(hv_niu_cfgh_rx_logical_page_conf)
 578 
 579         /*
 580          * hv_niu__cfgh_rx_logical_page_info(uint64_t cfgh, uint64_t chidx,
 581          *    uint64_t pgidx, uint64_t *raddr, uint64_t *size)
 582          */
 583         ENTRY(hv_niu_cfgh_rx_logical_page_info)
 584         mov     %o3, %g1
 585         mov     %o4, %g2
 586         mov     N2NIU_RX_LP_INFO, %o5
 587         ta      FAST_TRAP
 588         stx     %o1, [%g1]
 589         retl
 590         stx     %o2, [%g2]
 591         SET_SIZE(hv_niu_cfgh_rx_logical_page_info)
 592 
 593         /*
 594          * hv_niu_cfgh_tx_logical_page_conf(uint64_t cfgh, uint64_t chidx,
 595          *    uint64_t pgidx, uint64_t raddr, uint64_t size)
 596          */
 597         ENTRY(hv_niu_cfgh_tx_logical_page_conf)
 598         mov     N2NIU_TX_LP_CONF, %o5
 599         ta      FAST_TRAP
 600         retl
 601         nop
 602         SET_SIZE(hv_niu_cfgh_tx_logical_page_conf)
 603 
 604         /*
 605          * hv_niu_cfgh_tx_logical_page_info(uint64_t cfgh, uint64_t chidx,
 606          *    uint64_t pgidx, uint64_t *raddr, uint64_t *size)
 607          */
 608         ENTRY(hv_niu_cfgh_tx_logical_page_info)
 609         mov     %o3, %g1
 610         mov     %o4, %g2
 611         mov     N2NIU_TX_LP_INFO, %o5
 612         ta      FAST_TRAP
 613         stx     %o1, [%g1]
 614         retl
 615         stx     %o2, [%g2]
 616         SET_SIZE(hv_niu_cfgh_tx_logical_page_info)
 617 
 618         /*
 619          * hv_niu_cfgh_vr_assign(uint64_t cfgh, uint64_t vridx, uint64_t ldc_id,
 620          *     uint32_t *cookie)
 621          */
 622         ENTRY(hv_niu_cfgh_vr_assign)
 623         mov     %o3, %g1
 624         mov     N2NIU_VR_ASSIGN, %o5
 625         ta      FAST_TRAP
 626         retl
 627         stw     %o1, [%g1]
 628         SET_SIZE(hv_niu_cfgh_vr_assign)
 629 
 630 #endif  /* lint || __lint */
 631 
 632 #endif /*defined(sun4v)*/