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11967 need TAA mitigation
Portions contributed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Dan McDonald <danmcd@joyent.com>
@@ -25,11 +25,11 @@
/*
* Copyright (c) 2010, Intel Corporation.
* All rights reserved.
*/
/*
- * Copyright 2019 Joyent, Inc.
+ * Copyright 2020 Joyent, Inc.
* Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
* Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
* Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
* Copyright 2018 Nexenta Systems, Inc.
*/
@@ -462,10 +462,13 @@
#define IA32_ARCH_CAP_IBRS_ALL 0x0002
#define IA32_ARCH_CAP_RSBA 0x0004
#define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008
#define IA32_ARCH_CAP_SSB_NO 0x0010
#define IA32_ARCH_CAP_MDS_NO 0x0020
+#define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x0040
+#define IA32_ARCH_CAP_TSX_CTRL 0x0080
+#define IA32_ARCH_CAP_TAA_NO 0x0100
/*
* Intel Speculation related MSRs
*/
#define MSR_IA32_SPEC_CTRL 0x48
@@ -478,10 +481,17 @@
#define MSR_IA32_FLUSH_CMD 0x10b
#define IA32_FLUSH_CMD_L1D 0x01
/*
+ * Intel TSX Control MSRs
+ */
+#define MSR_IA32_TSX_CTRL 0x122
+#define IA32_TSX_CTRL_RTM_DISABLE 0x01
+#define IA32_TSX_CTRL_CPUID_CLEAR 0x02
+
+/*
* Intel Thermal MSRs
*/
#define MSR_IA32_THERM_INTERRUPT 0x19b
#define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001
#define IA32_THERM_INTERRUPT_LOW_IE 0x00000002
@@ -681,10 +691,12 @@
#define X86FSET_AMD_PCEC 92
#define X86FSET_MD_CLEAR 93
#define X86FSET_MDS_NO 94
#define X86FSET_CORE_THERMAL 95
#define X86FSET_PKG_THERMAL 96
+#define X86FSET_TSX_CTRL 97
+#define X86FSET_TAA_NO 98
/*
* Intel Deep C-State invariant TSC in leaf 0x80000007.
*/
#define CPUID_TSC_CSTATE_INVARIANCE (0x100)
@@ -1042,11 +1054,11 @@
#if !defined(_ASM)
#if defined(_KERNEL) || defined(_KMEMUSER)
-#define NUM_X86_FEATURES 97
+#define NUM_X86_FEATURES 99
extern uchar_t x86_featureset[];
extern void free_x86_featureset(void *featureset);
extern boolean_t is_x86_feature(void *featureset, uint_t feature);
extern void add_x86_feature(void *featureset, uint_t feature);