10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2019 Joyent, Inc.
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 * Copyright 2018 Nexenta Systems, Inc.
35 */
36
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define _SYS_X86_ARCHEXT_H
39
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif /* _ASM */
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
447 */
448 #define MSR_PPIN_CTL 0x04e
449 #define MSR_PPIN 0x04f
450 #define MSR_PLATFORM_INFO 0x0ce
451
452 #define MSR_PLATFORM_INFO_PPIN (1 << 23)
453 #define MSR_PPIN_CTL_MASK 0x03
454 #define MSR_PPIN_CTL_LOCKED 0x01
455 #define MSR_PPIN_CTL_ENABLED 0x02
456
457 /*
458 * Intel IA32_ARCH_CAPABILITIES MSR.
459 */
460 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
461 #define IA32_ARCH_CAP_RDCL_NO 0x0001
462 #define IA32_ARCH_CAP_IBRS_ALL 0x0002
463 #define IA32_ARCH_CAP_RSBA 0x0004
464 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008
465 #define IA32_ARCH_CAP_SSB_NO 0x0010
466 #define IA32_ARCH_CAP_MDS_NO 0x0020
467
468 /*
469 * Intel Speculation related MSRs
470 */
471 #define MSR_IA32_SPEC_CTRL 0x48
472 #define IA32_SPEC_CTRL_IBRS 0x01
473 #define IA32_SPEC_CTRL_STIBP 0x02
474 #define IA32_SPEC_CTRL_SSBD 0x04
475
476 #define MSR_IA32_PRED_CMD 0x49
477 #define IA32_PRED_CMD_IBPB 0x01
478
479 #define MSR_IA32_FLUSH_CMD 0x10b
480 #define IA32_FLUSH_CMD_L1D 0x01
481
482 /*
483 * Intel Thermal MSRs
484 */
485 #define MSR_IA32_THERM_INTERRUPT 0x19b
486 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001
487 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002
488 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004
489 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008
490 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010
491 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
492 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000
493 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
494 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000
495 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000
496
497 #define MSR_IA32_THERM_STATUS 0x19c
498 #define IA32_THERM_STATUS_STATUS 0x00000001
499 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002
500 #define IA32_THERM_STATUS_PROCHOT 0x00000004
501 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008
502 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010
666 #define X86FSET_IBRS_ALL 77
667 #define X86FSET_RSBA 78
668 #define X86FSET_SSB_NO 79
669 #define X86FSET_STIBP_ALL 80
670 #define X86FSET_FLUSH_CMD 81
671 #define X86FSET_L1D_VM_NO 82
672 #define X86FSET_FSGSBASE 83
673 #define X86FSET_CLFLUSHOPT 84
674 #define X86FSET_CLWB 85
675 #define X86FSET_MONITORX 86
676 #define X86FSET_CLZERO 87
677 #define X86FSET_XOP 88
678 #define X86FSET_FMA4 89
679 #define X86FSET_TBM 90
680 #define X86FSET_AVX512VNNI 91
681 #define X86FSET_AMD_PCEC 92
682 #define X86FSET_MD_CLEAR 93
683 #define X86FSET_MDS_NO 94
684 #define X86FSET_CORE_THERMAL 95
685 #define X86FSET_PKG_THERMAL 96
686
687 /*
688 * Intel Deep C-State invariant TSC in leaf 0x80000007.
689 */
690 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
691
692 /*
693 * Intel TSC deadline timer
694 */
695 #define CPUID_DEADLINE_TSC (1 << 24)
696
697 /*
698 * x86_type is a legacy concept; this is supplanted
699 * for most purposes by x86_featureset; modern CPUs
700 * should be X86_TYPE_OTHER
701 */
702 #define X86_TYPE_OTHER 0
703 #define X86_TYPE_486 1
704 #define X86_TYPE_P5 2
705 #define X86_TYPE_P6 3
1027 #define XFEATURE_PKRU 0x200
1028 #define XFEATURE_FP_ALL \
1029 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
1030 XFEATURE_AVX512 | XFEATURE_PKRU)
1031
1032 /*
1033 * Define the set of xfeature flags that should be considered valid in the xsave
1034 * state vector when we initialize an lwp. This is distinct from the full set so
1035 * that all of the processor's normal logic and tracking of the xsave state is
1036 * usable. This should correspond to the state that's been initialized by the
1037 * ABI to hold meaningful values. Adding additional bits here can have serious
1038 * performance implications and cause performance degradations when using the
1039 * FPU vector (xmm) registers.
1040 */
1041 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
1042
1043 #if !defined(_ASM)
1044
1045 #if defined(_KERNEL) || defined(_KMEMUSER)
1046
1047 #define NUM_X86_FEATURES 97
1048 extern uchar_t x86_featureset[];
1049
1050 extern void free_x86_featureset(void *featureset);
1051 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
1052 extern void add_x86_feature(void *featureset, uint_t feature);
1053 extern void remove_x86_feature(void *featureset, uint_t feature);
1054 extern boolean_t compare_x86_featureset(void *setA, void *setB);
1055 extern void print_x86_featureset(void *featureset);
1056
1057
1058 extern uint_t x86_type;
1059 extern uint_t x86_vendor;
1060 extern uint_t x86_clflush_size;
1061
1062 extern uint_t pentiumpro_bug4046376;
1063
1064 extern const char CyrixInstead[];
1065
1066 /*
1067 * These functions are all used to perform various side-channel mitigations.
|
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2020 Joyent, Inc.
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 * Copyright 2018 Nexenta Systems, Inc.
35 */
36
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define _SYS_X86_ARCHEXT_H
39
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif /* _ASM */
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
447 */
448 #define MSR_PPIN_CTL 0x04e
449 #define MSR_PPIN 0x04f
450 #define MSR_PLATFORM_INFO 0x0ce
451
452 #define MSR_PLATFORM_INFO_PPIN (1 << 23)
453 #define MSR_PPIN_CTL_MASK 0x03
454 #define MSR_PPIN_CTL_LOCKED 0x01
455 #define MSR_PPIN_CTL_ENABLED 0x02
456
457 /*
458 * Intel IA32_ARCH_CAPABILITIES MSR.
459 */
460 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
461 #define IA32_ARCH_CAP_RDCL_NO 0x0001
462 #define IA32_ARCH_CAP_IBRS_ALL 0x0002
463 #define IA32_ARCH_CAP_RSBA 0x0004
464 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008
465 #define IA32_ARCH_CAP_SSB_NO 0x0010
466 #define IA32_ARCH_CAP_MDS_NO 0x0020
467 #define IA32_ARCH_CAP_IF_PSCHANGE_MC_NO 0x0040
468 #define IA32_ARCH_CAP_TSX_CTRL 0x0080
469 #define IA32_ARCH_CAP_TAA_NO 0x0100
470
471 /*
472 * Intel Speculation related MSRs
473 */
474 #define MSR_IA32_SPEC_CTRL 0x48
475 #define IA32_SPEC_CTRL_IBRS 0x01
476 #define IA32_SPEC_CTRL_STIBP 0x02
477 #define IA32_SPEC_CTRL_SSBD 0x04
478
479 #define MSR_IA32_PRED_CMD 0x49
480 #define IA32_PRED_CMD_IBPB 0x01
481
482 #define MSR_IA32_FLUSH_CMD 0x10b
483 #define IA32_FLUSH_CMD_L1D 0x01
484
485 /*
486 * Intel TSX Control MSRs
487 */
488 #define MSR_IA32_TSX_CTRL 0x122
489 #define IA32_TSX_CTRL_RTM_DISABLE 0x01
490 #define IA32_TSX_CTRL_CPUID_CLEAR 0x02
491
492 /*
493 * Intel Thermal MSRs
494 */
495 #define MSR_IA32_THERM_INTERRUPT 0x19b
496 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001
497 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002
498 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004
499 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008
500 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010
501 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
502 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000
503 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
504 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000
505 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000
506
507 #define MSR_IA32_THERM_STATUS 0x19c
508 #define IA32_THERM_STATUS_STATUS 0x00000001
509 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002
510 #define IA32_THERM_STATUS_PROCHOT 0x00000004
511 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008
512 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010
676 #define X86FSET_IBRS_ALL 77
677 #define X86FSET_RSBA 78
678 #define X86FSET_SSB_NO 79
679 #define X86FSET_STIBP_ALL 80
680 #define X86FSET_FLUSH_CMD 81
681 #define X86FSET_L1D_VM_NO 82
682 #define X86FSET_FSGSBASE 83
683 #define X86FSET_CLFLUSHOPT 84
684 #define X86FSET_CLWB 85
685 #define X86FSET_MONITORX 86
686 #define X86FSET_CLZERO 87
687 #define X86FSET_XOP 88
688 #define X86FSET_FMA4 89
689 #define X86FSET_TBM 90
690 #define X86FSET_AVX512VNNI 91
691 #define X86FSET_AMD_PCEC 92
692 #define X86FSET_MD_CLEAR 93
693 #define X86FSET_MDS_NO 94
694 #define X86FSET_CORE_THERMAL 95
695 #define X86FSET_PKG_THERMAL 96
696 #define X86FSET_TSX_CTRL 97
697 #define X86FSET_TAA_NO 98
698
699 /*
700 * Intel Deep C-State invariant TSC in leaf 0x80000007.
701 */
702 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
703
704 /*
705 * Intel TSC deadline timer
706 */
707 #define CPUID_DEADLINE_TSC (1 << 24)
708
709 /*
710 * x86_type is a legacy concept; this is supplanted
711 * for most purposes by x86_featureset; modern CPUs
712 * should be X86_TYPE_OTHER
713 */
714 #define X86_TYPE_OTHER 0
715 #define X86_TYPE_486 1
716 #define X86_TYPE_P5 2
717 #define X86_TYPE_P6 3
1039 #define XFEATURE_PKRU 0x200
1040 #define XFEATURE_FP_ALL \
1041 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
1042 XFEATURE_AVX512 | XFEATURE_PKRU)
1043
1044 /*
1045 * Define the set of xfeature flags that should be considered valid in the xsave
1046 * state vector when we initialize an lwp. This is distinct from the full set so
1047 * that all of the processor's normal logic and tracking of the xsave state is
1048 * usable. This should correspond to the state that's been initialized by the
1049 * ABI to hold meaningful values. Adding additional bits here can have serious
1050 * performance implications and cause performance degradations when using the
1051 * FPU vector (xmm) registers.
1052 */
1053 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
1054
1055 #if !defined(_ASM)
1056
1057 #if defined(_KERNEL) || defined(_KMEMUSER)
1058
1059 #define NUM_X86_FEATURES 99
1060 extern uchar_t x86_featureset[];
1061
1062 extern void free_x86_featureset(void *featureset);
1063 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
1064 extern void add_x86_feature(void *featureset, uint_t feature);
1065 extern void remove_x86_feature(void *featureset, uint_t feature);
1066 extern boolean_t compare_x86_featureset(void *setA, void *setB);
1067 extern void print_x86_featureset(void *featureset);
1068
1069
1070 extern uint_t x86_type;
1071 extern uint_t x86_vendor;
1072 extern uint_t x86_clflush_size;
1073
1074 extern uint_t pentiumpro_bug4046376;
1075
1076 extern const char CyrixInstead[];
1077
1078 /*
1079 * These functions are all used to perform various side-channel mitigations.
|