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11859 need swapgs mitigation
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
Reviewed by: Dan McDonald <danmcd@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: Robert Mustacchi <rm@fingolfin.org>
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--- old/usr/src/uts/intel/amd64/ml/amd64.il
+++ new/usr/src/uts/intel/amd64/ml/amd64.il
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
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16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 23 * Use is subject to license terms.
24 24 */
25 25
26 +/*
27 + * Copyright 2019 Joyent, Inc.
28 + */
29 +
26 30 /
27 31 / In-line functions for amd64 kernels.
28 32 /
29 33
30 34 /
31 35 / return current thread pointer
32 36 /
33 37 / NOTE: the "0x18" should be replaced by the computed value of the
34 38 / offset of "cpu_thread" from the beginning of the struct cpu.
35 39 / Including "assym.h" does not work, however, since that stuff
36 40 / is PSM-specific and is only visible to the 'unix' build anyway.
37 41 / Same with current cpu pointer, where "0xc" should be replaced
38 42 / by the computed value of the offset of "cpu_self".
39 43 / Ugh -- what a disaster.
40 44 /
41 45 .inline threadp,0
42 46 movq %gs:0x18, %rax
43 47 .end
44 48
45 49 /
46 50 / return current cpu pointer
47 51 /
48 52 .inline curcpup,0
49 53 movq %gs:0x10, %rax
50 54 .end
51 55
52 56 /
53 57 / return caller
54 58 /
55 59 .inline caller,0
56 60 movq 8(%rbp), %rax
57 61 .end
58 62
59 63 /
60 64 / convert ipl to spl. This is the identity function for i86
61 65 /
62 66 .inline ipltospl,0
63 67 movq %rdi, %rax
64 68 .end
65 69
66 70 /
67 71 / Networking byte order functions (too bad, Intel has the wrong byte order)
68 72 /
69 73
70 74 .inline htonll,4
71 75 movq %rdi, %rax
72 76 bswapq %rax
73 77 .end
74 78
75 79 .inline ntohll,4
76 80 movq %rdi, %rax
77 81 bswapq %rax
78 82 .end
79 83
80 84 .inline htonl,4
81 85 movl %edi, %eax
82 86 bswap %eax
83 87 .end
84 88
85 89 .inline ntohl,4
86 90 movl %edi, %eax
87 91 bswap %eax
88 92 .end
89 93
90 94 .inline htons,4
91 95 movl %edi, %eax
92 96 bswap %eax
93 97 shrl $16, %eax
94 98 .end
95 99
96 100 .inline ntohs,4
97 101 movl %edi, %eax
98 102 bswap %eax
99 103 shrl $16, %eax
100 104 .end
101 105
102 106 /*
103 107 * multiply two long numbers and yield a u_lonlong_t result
104 108 * Provided to manipulate hrtime_t values.
105 109 */
106 110 /* XX64 These don't work correctly with SOS9 build 13.0 yet
107 111 .inline mul32, 8
108 112 xorl %edx, %edx
109 113 movl %edi, %eax
110 114 mull %esi
111 115 shlq $32, %rdx
112 116 orq %rdx, %rax
113 117 ret
114 118 .end
115 119 */
116 120 /*
117 121 * Unlock hres_lock and increment the count value. (See clock.h)
118 122 */
119 123 .inline unlock_hres_lock, 0
120 124 lock
121 125 incl hres_lock
122 126 .end
123 127
124 128 .inline atomic_orb,8
125 129 movl %esi, %eax
126 130 lock
127 131 orb %al,(%rdi)
128 132 .end
129 133
130 134 .inline atomic_andb,8
131 135 movl %esi, %eax
132 136 lock
133 137 andb %al,(%rdi)
134 138 .end
135 139
136 140 /*
137 141 * atomic inc/dec operations.
138 142 * void atomic_inc16(uint16_t *addr) { ++*addr; }
139 143 * void atomic_dec16(uint16_t *addr) { --*addr; }
140 144 */
141 145 .inline atomic_inc16,4
142 146 lock
143 147 incw (%rdi)
144 148 .end
145 149
146 150 .inline atomic_dec16,4
147 151 lock
148 152 decw (%rdi)
149 153 .end
150 154
151 155 /*
152 156 * atomic bit clear
153 157 */
154 158 .inline atomic_btr32,8
155 159 lock
156 160 btrl %esi, (%rdi)
157 161 setc %al
158 162 .end
159 163
160 164 /*
161 165 * Call the pause instruction. To the Pentium 4 Xeon processor, it acts as
162 166 * a hint that the code sequence is a busy spin-wait loop. Without a pause
163 167 * instruction in these loops, the P4 Xeon processor may suffer a severe
164 168 * penalty when exiting the loop because the processor detects a possible
165 169 * memory violation. Inserting the pause instruction significantly reduces
166 170 * the likelihood of a memory order violation, improving performance.
167 171 * The pause instruction is a NOP on all other IA-32 processors.
168 172 */
169 173 .inline ht_pause, 0
170 174 pause
171 175 .end
172 176
173 177 /*
174 178 * inlines for update_sregs().
175 179 */
176 180 .inline __set_ds, 0
177 181 movw %di, %ds
178 182 .end
179 183
180 184 .inline __set_es, 0
181 185 movw %di, %es
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182 186 .end
183 187
184 188 .inline __set_fs, 0
185 189 movw %di, %fs
186 190 .end
187 191
188 192 .inline __set_gs, 0
189 193 movw %di, %gs
190 194 .end
191 195
192 - /*
193 - * OPTERON_ERRATUM_88 requires mfence
194 - */
195 - .inline __swapgs, 0
196 - mfence
197 - swapgs
198 - .end
199 -
200 196 /*
201 197 * prefetch 64 bytes
202 198 */
203 199
204 - .inline prefetch_read_many,8
200 + .inline prefetch_read_many,8
205 201 prefetcht0 (%rdi)
206 202 prefetcht0 32(%rdi)
207 203 .end
208 204
209 - .inline prefetch_read_once,8
205 + .inline prefetch_read_once,8
210 206 prefetchnta (%rdi)
211 207 prefetchnta 32(%rdi)
212 208 .end
213 209
214 - .inline prefetch_write_many,8
210 + .inline prefetch_write_many,8
215 211 prefetcht0 (%rdi)
216 212 prefetcht0 32(%rdi)
217 213 .end
218 214
219 - .inline prefetch_write_once,8
215 + .inline prefetch_write_once,8
220 216 prefetcht0 (%rdi)
221 217 prefetcht0 32(%rdi)
222 218 .end
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