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11787 Kernel needs to be built with retpolines
11788 Kernel needs to generally use RSB stuffing
Reviewed by: Jerry Jelinek <jerry.jelinek@joyent.com>
Reviewed by: John Levon <john.levon@joyent.com>
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--- old/usr/src/uts/intel/sys/x86_archext.h
+++ new/usr/src/uts/intel/sys/x86_archext.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License (the "License").
6 6 * You may not use this file except in compliance with the License.
7 7 *
8 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 9 * or http://www.opensolaris.org/os/licensing.
10 10 * See the License for the specific language governing permissions
11 11 * and limitations under the License.
12 12 *
13 13 * When distributing Covered Code, include this CDDL HEADER in each
14 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 15 * If applicable, add the following below this CDDL HEADER, with the
16 16 * fields enclosed by brackets "[]" replaced with your own identifying
17 17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 18 *
19 19 * CDDL HEADER END
20 20 */
21 21 /*
22 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 24 */
25 25 /*
26 26 * Copyright (c) 2010, Intel Corporation.
27 27 * All rights reserved.
28 28 */
29 29 /*
30 30 * Copyright 2019 Joyent, Inc.
31 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 34 * Copyright 2018 Nexenta Systems, Inc.
35 35 */
36 36
37 37 #ifndef _SYS_X86_ARCHEXT_H
38 38 #define _SYS_X86_ARCHEXT_H
39 39
40 40 #if !defined(_ASM)
41 41 #include <sys/regset.h>
42 42 #include <sys/processor.h>
43 43 #include <vm/seg_enum.h>
44 44 #include <vm/page.h>
45 45 #endif /* _ASM */
46 46
47 47 #ifdef __cplusplus
48 48 extern "C" {
49 49 #endif
50 50
51 51 /*
52 52 * cpuid instruction feature flags in %edx (standard function 1)
53 53 */
54 54
55 55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
56 56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
57 57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
58 58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
59 59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
60 60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
61 61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
62 62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
63 63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
64 64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
65 65 /* 0x400 - reserved */
66 66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
67 67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
68 68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 75 /* 0x100000 - reserved */
76 76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87 87
88 88 /*
89 89 * cpuid instruction feature flags in %ecx (standard function 1)
90 90 */
91 91
92 92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 103 /* 0x00000800 - reserved */
104 104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 108 /* 0x00010000 - reserved */
109 109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
117 117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
118 118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
119 119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
120 120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
121 121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
122 122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
123 123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
124 124
125 125 /*
126 126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
127 127 */
128 128
129 129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
130 130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
131 131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
132 132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
133 133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
134 134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
135 135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
136 136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
137 137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
138 138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
139 139 /* 0x00000400 - sysc on K6m6 */
140 140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
141 141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
142 142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
143 143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
144 144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
145 145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
146 146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
147 147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
148 148 /* 0x00040000 - reserved */
149 149 /* 0x00080000 - reserved */
150 150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
151 151 /* 0x00200000 - reserved */
152 152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
153 153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
154 154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
155 155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
156 156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
157 157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
158 158 /* 0x10000000 - reserved */
159 159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
160 160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
161 161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
162 162
163 163 /*
164 164 * AMD extended function 0x80000001 %ecx
165 165 */
166 166
167 167 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
168 168 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
169 169 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
170 170 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
171 171 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
172 172 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
173 173 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
174 174 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
175 175 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
176 176 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
177 177 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
178 178 #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */
179 179 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
180 180 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
181 181 /* 0x00004000 - reserved */
182 182 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
183 183 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
184 184 /* 0x00020000 - reserved */
185 185 /* 0x00040000 - reserved */
186 186 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
187 187 /* 0x00100000 - reserved */
188 188 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
189 189 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
190 190 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */
191 191 #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */
192 192 /* 0x02000000 - reserved */
193 193 #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */
194 194 #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */
195 195 #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */
196 196 #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */
197 197 /* 0x40000000 - reserved */
198 198 /* 0x80000000 - reserved */
199 199
200 200 /*
201 201 * AMD uses %ebx for some of their features (extended function 0x80000008).
202 202 */
203 203 #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */
204 204 #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */
205 205 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */
206 206 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */
207 207 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */
208 208 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */
209 209 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */
210 210 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */
211 211 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */
212 212 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */
213 213 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */
214 214 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */
215 215
216 216 /*
217 217 * Intel now seems to have claimed part of the "extended" function
218 218 * space that we previously for non-Intel implementors to use.
219 219 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
220 220 * is available in long mode i.e. what AMD indicate using bit 0.
221 221 * On the other hand, everything else is labelled as reserved.
222 222 */
223 223 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
224 224
225 225 /*
226 226 * Intel uses cpuid leaf 6 to cover various thermal and power control
227 227 * operations.
228 228 */
229 229 #define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */
230 230 #define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */
231 231 #define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */
232 232 /* bit 3 is reserved */
233 233 #define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */
234 234 #define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */
235 235 #define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */
236 236 #define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */
237 237 #define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */
238 238 #define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */
239 239 #define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */
240 240 #define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */
241 241 /* bit 12 is reserved */
242 242 #define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */
243 243 #define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */
244 244 #define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */
245 245 #define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */
246 246 #define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */
247 247 #define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */
248 248 /* bit 19 is reserved */
249 249 #define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */
250 250
251 251 #define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf)
252 252
253 253 #define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */
254 254 /* bits 1-2 are reserved */
255 255 #define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */
256 256
257 257 /*
258 258 * Intel also uses cpuid leaf 7 to have additional instructions and features.
259 259 * Like some other leaves, but unlike the current ones we care about, it
260 260 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
261 261 * with the potential use of additional sub-leaves in the future, we now
262 262 * specifically label the EBX features with their leaf and sub-leaf.
263 263 */
264 264 #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */
265 265 #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */
266 266 #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */
267 267 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
268 268 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
269 269 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
270 270 /* Bit 6 is reserved */
271 271 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
272 272 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
273 273 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */
274 274 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */
275 275 #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */
276 276 #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */
277 277 #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */
278 278 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
279 279 #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */
280 280 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
281 281 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
282 282 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
283 283 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
284 284 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
285 285 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
286 286 /* Bit 22 is reserved */
287 287 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */
288 288 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
289 289 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */
290 290 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
291 291 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
292 292 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
293 293 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
294 294 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
295 295 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
296 296
297 297 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
298 298 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
299 299 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
300 300 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
301 301 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
302 302
303 303 #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */
304 304 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
305 305 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
306 306 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
307 307 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
308 308 #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */
309 309 #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */
310 310 /* bit 7 is reserved */
311 311 #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */
312 312 #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */
313 313 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */
314 314 #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */
315 315 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */
316 316 /* bit 13 is reserved */
317 317 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
318 318 /* bits 15-16 are reserved */
319 319 /* bits 17-21 are the value of MAWAU */
320 320 #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */
321 321 /* bits 23-24 are reserved */
322 322 #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */
323 323 /* bit 26 is resrved */
324 324 #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */
325 325 #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */
326 326 /* bit 29 is reserved */
327 327 #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */
328 328 /* bit 31 is reserved */
329 329
330 330 /*
331 331 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and
332 332 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still
333 333 * valid when AVX512 is not. However, the following flags all are only valid
334 334 * when AVX512 is present.
335 335 */
336 336 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
337 337 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \
338 338 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
339 339
340 340 /* bits 0-1 are reserved */
341 341 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
342 342 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
343 343 #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */
344 344 /* bits 5-9 are reserved */
345 345 #define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */
346 346 /* bits 11-17 are reserved */
347 347 #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */
348 348 /* bits 19-26 are reserved */
349 349 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */
350 350 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */
351 351 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */
352 352 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */
353 353 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */
354 354
355 355 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
356 356 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
357 357
358 358 /*
359 359 * Intel also uses cpuid leaf 0xd to report additional instructions and features
360 360 * when the sub-leaf in %ecx == 1. We label these using the same convention as
361 361 * with leaf 7.
362 362 */
363 363 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
364 364 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
365 365 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
366 366
367 367 #define REG_PAT 0x277
368 368 #define REG_TSC 0x10 /* timestamp counter */
369 369 #define REG_APIC_BASE_MSR 0x1b
370 370 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
371 371
372 372 #if !defined(__xpv)
373 373 /*
374 374 * AMD C1E
375 375 */
376 376 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
377 377 #define AMD_ACTONCMPHALT_SHIFT 27
378 378 #define AMD_ACTONCMPHALT_MASK 3
379 379 #endif
380 380
381 381 #define MSR_DEBUGCTL 0x1d9
382 382
383 383 #define DEBUGCTL_LBR 0x01
384 384 #define DEBUGCTL_BTF 0x02
385 385
386 386 /* Intel P6, AMD */
387 387 #define MSR_LBR_FROM 0x1db
388 388 #define MSR_LBR_TO 0x1dc
389 389 #define MSR_LEX_FROM 0x1dd
390 390 #define MSR_LEX_TO 0x1de
391 391
392 392 /* Intel P4 (pre-Prescott, non P4 M) */
393 393 #define MSR_P4_LBSTK_TOS 0x1da
394 394 #define MSR_P4_LBSTK_0 0x1db
395 395 #define MSR_P4_LBSTK_1 0x1dc
396 396 #define MSR_P4_LBSTK_2 0x1dd
397 397 #define MSR_P4_LBSTK_3 0x1de
398 398
399 399 /* Intel Pentium M */
400 400 #define MSR_P6M_LBSTK_TOS 0x1c9
401 401 #define MSR_P6M_LBSTK_0 0x040
402 402 #define MSR_P6M_LBSTK_1 0x041
403 403 #define MSR_P6M_LBSTK_2 0x042
404 404 #define MSR_P6M_LBSTK_3 0x043
405 405 #define MSR_P6M_LBSTK_4 0x044
406 406 #define MSR_P6M_LBSTK_5 0x045
407 407 #define MSR_P6M_LBSTK_6 0x046
408 408 #define MSR_P6M_LBSTK_7 0x047
409 409
410 410 /* Intel P4 (Prescott) */
411 411 #define MSR_PRP4_LBSTK_TOS 0x1da
412 412 #define MSR_PRP4_LBSTK_FROM_0 0x680
413 413 #define MSR_PRP4_LBSTK_FROM_1 0x681
414 414 #define MSR_PRP4_LBSTK_FROM_2 0x682
415 415 #define MSR_PRP4_LBSTK_FROM_3 0x683
416 416 #define MSR_PRP4_LBSTK_FROM_4 0x684
417 417 #define MSR_PRP4_LBSTK_FROM_5 0x685
418 418 #define MSR_PRP4_LBSTK_FROM_6 0x686
419 419 #define MSR_PRP4_LBSTK_FROM_7 0x687
420 420 #define MSR_PRP4_LBSTK_FROM_8 0x688
421 421 #define MSR_PRP4_LBSTK_FROM_9 0x689
422 422 #define MSR_PRP4_LBSTK_FROM_10 0x68a
423 423 #define MSR_PRP4_LBSTK_FROM_11 0x68b
424 424 #define MSR_PRP4_LBSTK_FROM_12 0x68c
425 425 #define MSR_PRP4_LBSTK_FROM_13 0x68d
426 426 #define MSR_PRP4_LBSTK_FROM_14 0x68e
427 427 #define MSR_PRP4_LBSTK_FROM_15 0x68f
428 428 #define MSR_PRP4_LBSTK_TO_0 0x6c0
429 429 #define MSR_PRP4_LBSTK_TO_1 0x6c1
430 430 #define MSR_PRP4_LBSTK_TO_2 0x6c2
431 431 #define MSR_PRP4_LBSTK_TO_3 0x6c3
432 432 #define MSR_PRP4_LBSTK_TO_4 0x6c4
433 433 #define MSR_PRP4_LBSTK_TO_5 0x6c5
434 434 #define MSR_PRP4_LBSTK_TO_6 0x6c6
435 435 #define MSR_PRP4_LBSTK_TO_7 0x6c7
436 436 #define MSR_PRP4_LBSTK_TO_8 0x6c8
437 437 #define MSR_PRP4_LBSTK_TO_9 0x6c9
438 438 #define MSR_PRP4_LBSTK_TO_10 0x6ca
439 439 #define MSR_PRP4_LBSTK_TO_11 0x6cb
440 440 #define MSR_PRP4_LBSTK_TO_12 0x6cc
441 441 #define MSR_PRP4_LBSTK_TO_13 0x6cd
442 442 #define MSR_PRP4_LBSTK_TO_14 0x6ce
443 443 #define MSR_PRP4_LBSTK_TO_15 0x6cf
444 444
445 445 /*
446 446 * General Xeon based MSRs
447 447 */
448 448 #define MSR_PPIN_CTL 0x04e
449 449 #define MSR_PPIN 0x04f
450 450 #define MSR_PLATFORM_INFO 0x0ce
451 451
452 452 #define MSR_PLATFORM_INFO_PPIN (1 << 23)
453 453 #define MSR_PPIN_CTL_MASK 0x03
454 454 #define MSR_PPIN_CTL_LOCKED 0x01
455 455 #define MSR_PPIN_CTL_ENABLED 0x02
456 456
457 457 /*
458 458 * Intel IA32_ARCH_CAPABILITIES MSR.
459 459 */
460 460 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
461 461 #define IA32_ARCH_CAP_RDCL_NO 0x0001
462 462 #define IA32_ARCH_CAP_IBRS_ALL 0x0002
463 463 #define IA32_ARCH_CAP_RSBA 0x0004
464 464 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008
465 465 #define IA32_ARCH_CAP_SSB_NO 0x0010
466 466 #define IA32_ARCH_CAP_MDS_NO 0x0020
467 467
468 468 /*
469 469 * Intel Speculation related MSRs
470 470 */
471 471 #define MSR_IA32_SPEC_CTRL 0x48
472 472 #define IA32_SPEC_CTRL_IBRS 0x01
473 473 #define IA32_SPEC_CTRL_STIBP 0x02
474 474 #define IA32_SPEC_CTRL_SSBD 0x04
475 475
476 476 #define MSR_IA32_PRED_CMD 0x49
477 477 #define IA32_PRED_CMD_IBPB 0x01
478 478
479 479 #define MSR_IA32_FLUSH_CMD 0x10b
480 480 #define IA32_FLUSH_CMD_L1D 0x01
481 481
482 482 /*
483 483 * Intel Thermal MSRs
484 484 */
485 485 #define MSR_IA32_THERM_INTERRUPT 0x19b
486 486 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001
487 487 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002
488 488 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004
489 489 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008
490 490 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010
491 491 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
492 492 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000
493 493 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
494 494 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000
495 495 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000
496 496
497 497 #define MSR_IA32_THERM_STATUS 0x19c
498 498 #define IA32_THERM_STATUS_STATUS 0x00000001
499 499 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002
500 500 #define IA32_THERM_STATUS_PROCHOT 0x00000004
501 501 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008
502 502 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010
503 503 #define IA32_THERM_STATUS_CRIT_LOG 0x00000020
504 504 #define IA32_THERM_STATUS_TR1_STATUS 0x00000040
505 505 #define IA32_THERM_STATUS_TR1_LOG 0x00000080
506 506 #define IA32_THERM_STATUS_TR2_STATUS 0x00000100
507 507 #define IA32_THERM_STATUS_TR2_LOG 0x00000200
508 508 #define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400
509 509 #define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800
510 510 #define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000
511 511 #define IA32_THERM_STATUS_CURRENT_LOG 0x00002000
512 512 #define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000
513 513 #define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000
514 514 #define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f)
515 515 #define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f)
516 516 #define IA32_THERM_STATUS_READ_VALID 0x80000000
517 517
518 518 #define MSR_TEMPERATURE_TARGET 0x1a2
519 519 #define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff)
520 520 /*
521 521 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list
522 522 * of which models have support for which bits.
523 523 */
524 524 #define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f)
525 525
526 526 #define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1
527 527 #define IA32_PKG_THERM_STATUS_STATUS 0x00000001
528 528 #define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002
529 529 #define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004
530 530 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008
531 531 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010
532 532 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020
533 533 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040
534 534 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080
535 535 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100
536 536 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200
537 537 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f)
538 538
539 539 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2
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540 540 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001
541 541 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002
542 542 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004
543 543 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010
544 544 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
545 545 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000
546 546 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
547 547 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000
548 548 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000
549 549
550 +/*
551 + * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction
552 + * decoding. Most notably, for the AMD variant of retpolines, we must improve
553 + * the serializability of lfence for the lfence based method to work.
554 + */
555 +#define MSR_AMD_DECODE_CONFIG 0xc0011029
556 +#define AMD_DECODE_CONFIG_LFENCE_DISPATCH 0x02
557 +
550 558 #define MCI_CTL_VALUE 0xffffffff
551 559
552 560 #define MTRR_TYPE_UC 0
553 561 #define MTRR_TYPE_WC 1
554 562 #define MTRR_TYPE_WT 4
555 563 #define MTRR_TYPE_WP 5
556 564 #define MTRR_TYPE_WB 6
557 565 #define MTRR_TYPE_UC_ 7
558 566
559 567 /*
560 568 * For Solaris we set up the page attritubute table in the following way:
561 569 * PAT0 Write-Back
562 570 * PAT1 Write-Through
563 571 * PAT2 Unchacheable-
564 572 * PAT3 Uncacheable
565 573 * PAT4 Write-Back
566 574 * PAT5 Write-Through
567 575 * PAT6 Write-Combine
568 576 * PAT7 Uncacheable
569 577 * The only difference from h/w default is entry 6.
570 578 */
571 579 #define PAT_DEFAULT_ATTRIBUTE \
572 580 ((uint64_t)MTRR_TYPE_WB | \
573 581 ((uint64_t)MTRR_TYPE_WT << 8) | \
574 582 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
575 583 ((uint64_t)MTRR_TYPE_UC << 24) | \
576 584 ((uint64_t)MTRR_TYPE_WB << 32) | \
577 585 ((uint64_t)MTRR_TYPE_WT << 40) | \
578 586 ((uint64_t)MTRR_TYPE_WC << 48) | \
579 587 ((uint64_t)MTRR_TYPE_UC << 56))
580 588
581 589 #define X86FSET_LARGEPAGE 0
582 590 #define X86FSET_TSC 1
583 591 #define X86FSET_MSR 2
584 592 #define X86FSET_MTRR 3
585 593 #define X86FSET_PGE 4
586 594 #define X86FSET_DE 5
587 595 #define X86FSET_CMOV 6
588 596 #define X86FSET_MMX 7
589 597 #define X86FSET_MCA 8
590 598 #define X86FSET_PAE 9
591 599 #define X86FSET_CX8 10
592 600 #define X86FSET_PAT 11
593 601 #define X86FSET_SEP 12
594 602 #define X86FSET_SSE 13
595 603 #define X86FSET_SSE2 14
596 604 #define X86FSET_HTT 15
597 605 #define X86FSET_ASYSC 16
598 606 #define X86FSET_NX 17
599 607 #define X86FSET_SSE3 18
600 608 #define X86FSET_CX16 19
601 609 #define X86FSET_CMP 20
602 610 #define X86FSET_TSCP 21
603 611 #define X86FSET_MWAIT 22
604 612 #define X86FSET_SSE4A 23
605 613 #define X86FSET_CPUID 24
606 614 #define X86FSET_SSSE3 25
607 615 #define X86FSET_SSE4_1 26
608 616 #define X86FSET_SSE4_2 27
609 617 #define X86FSET_1GPG 28
610 618 #define X86FSET_CLFSH 29
611 619 #define X86FSET_64 30
612 620 #define X86FSET_AES 31
613 621 #define X86FSET_PCLMULQDQ 32
614 622 #define X86FSET_XSAVE 33
615 623 #define X86FSET_AVX 34
616 624 #define X86FSET_VMX 35
617 625 #define X86FSET_SVM 36
618 626 #define X86FSET_TOPOEXT 37
619 627 #define X86FSET_F16C 38
620 628 #define X86FSET_RDRAND 39
621 629 #define X86FSET_X2APIC 40
622 630 #define X86FSET_AVX2 41
623 631 #define X86FSET_BMI1 42
624 632 #define X86FSET_BMI2 43
625 633 #define X86FSET_FMA 44
626 634 #define X86FSET_SMEP 45
627 635 #define X86FSET_SMAP 46
628 636 #define X86FSET_ADX 47
629 637 #define X86FSET_RDSEED 48
630 638 #define X86FSET_MPX 49
631 639 #define X86FSET_AVX512F 50
632 640 #define X86FSET_AVX512DQ 51
633 641 #define X86FSET_AVX512PF 52
634 642 #define X86FSET_AVX512ER 53
635 643 #define X86FSET_AVX512CD 54
636 644 #define X86FSET_AVX512BW 55
637 645 #define X86FSET_AVX512VL 56
638 646 #define X86FSET_AVX512FMA 57
639 647 #define X86FSET_AVX512VBMI 58
640 648 #define X86FSET_AVX512VPOPCDQ 59
641 649 #define X86FSET_AVX512NNIW 60
642 650 #define X86FSET_AVX512FMAPS 61
643 651 #define X86FSET_XSAVEOPT 62
644 652 #define X86FSET_XSAVEC 63
645 653 #define X86FSET_XSAVES 64
646 654 #define X86FSET_SHA 65
647 655 #define X86FSET_UMIP 66
648 656 #define X86FSET_PKU 67
649 657 #define X86FSET_OSPKE 68
650 658 #define X86FSET_PCID 69
651 659 #define X86FSET_INVPCID 70
652 660 #define X86FSET_IBRS 71
653 661 #define X86FSET_IBPB 72
654 662 #define X86FSET_STIBP 73
655 663 #define X86FSET_SSBD 74
656 664 #define X86FSET_SSBD_VIRT 75
657 665 #define X86FSET_RDCL_NO 76
658 666 #define X86FSET_IBRS_ALL 77
659 667 #define X86FSET_RSBA 78
660 668 #define X86FSET_SSB_NO 79
661 669 #define X86FSET_STIBP_ALL 80
662 670 #define X86FSET_FLUSH_CMD 81
663 671 #define X86FSET_L1D_VM_NO 82
664 672 #define X86FSET_FSGSBASE 83
665 673 #define X86FSET_CLFLUSHOPT 84
666 674 #define X86FSET_CLWB 85
667 675 #define X86FSET_MONITORX 86
668 676 #define X86FSET_CLZERO 87
669 677 #define X86FSET_XOP 88
670 678 #define X86FSET_FMA4 89
671 679 #define X86FSET_TBM 90
672 680 #define X86FSET_AVX512VNNI 91
673 681 #define X86FSET_AMD_PCEC 92
674 682 #define X86FSET_MD_CLEAR 93
675 683 #define X86FSET_MDS_NO 94
676 684 #define X86FSET_CORE_THERMAL 95
677 685 #define X86FSET_PKG_THERMAL 96
678 686
679 687 /*
680 688 * Intel Deep C-State invariant TSC in leaf 0x80000007.
681 689 */
682 690 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
683 691
684 692 /*
685 693 * Intel TSC deadline timer
686 694 */
687 695 #define CPUID_DEADLINE_TSC (1 << 24)
688 696
689 697 /*
690 698 * x86_type is a legacy concept; this is supplanted
691 699 * for most purposes by x86_featureset; modern CPUs
692 700 * should be X86_TYPE_OTHER
693 701 */
694 702 #define X86_TYPE_OTHER 0
695 703 #define X86_TYPE_486 1
696 704 #define X86_TYPE_P5 2
697 705 #define X86_TYPE_P6 3
698 706 #define X86_TYPE_CYRIX_486 4
699 707 #define X86_TYPE_CYRIX_6x86L 5
700 708 #define X86_TYPE_CYRIX_6x86 6
701 709 #define X86_TYPE_CYRIX_GXm 7
702 710 #define X86_TYPE_CYRIX_6x86MX 8
703 711 #define X86_TYPE_CYRIX_MediaGX 9
704 712 #define X86_TYPE_CYRIX_MII 10
705 713 #define X86_TYPE_VIA_CYRIX_III 11
706 714 #define X86_TYPE_P4 12
707 715
708 716 /*
709 717 * x86_vendor allows us to select between
710 718 * implementation features and helps guide
711 719 * the interpretation of the cpuid instruction.
712 720 */
713 721 #define X86_VENDOR_Intel 0
714 722 #define X86_VENDORSTR_Intel "GenuineIntel"
715 723
716 724 #define X86_VENDOR_IntelClone 1
717 725
718 726 #define X86_VENDOR_AMD 2
719 727 #define X86_VENDORSTR_AMD "AuthenticAMD"
720 728
721 729 #define X86_VENDOR_Cyrix 3
722 730 #define X86_VENDORSTR_CYRIX "CyrixInstead"
723 731
724 732 #define X86_VENDOR_UMC 4
725 733 #define X86_VENDORSTR_UMC "UMC UMC UMC "
726 734
727 735 #define X86_VENDOR_NexGen 5
728 736 #define X86_VENDORSTR_NexGen "NexGenDriven"
729 737
730 738 #define X86_VENDOR_Centaur 6
731 739 #define X86_VENDORSTR_Centaur "CentaurHauls"
732 740
733 741 #define X86_VENDOR_Rise 7
734 742 #define X86_VENDORSTR_Rise "RiseRiseRise"
735 743
736 744 #define X86_VENDOR_SiS 8
737 745 #define X86_VENDORSTR_SiS "SiS SiS SiS "
738 746
739 747 #define X86_VENDOR_TM 9
740 748 #define X86_VENDORSTR_TM "GenuineTMx86"
741 749
742 750 #define X86_VENDOR_NSC 10
743 751 #define X86_VENDORSTR_NSC "Geode by NSC"
744 752
745 753 /*
746 754 * Vendor string max len + \0
747 755 */
748 756 #define X86_VENDOR_STRLEN 13
749 757
750 758 /*
751 759 * Some vendor/family/model/stepping ranges are commonly grouped under
752 760 * a single identifying banner by the vendor. The following encode
753 761 * that "revision" in a uint32_t with the 8 most significant bits
754 762 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
755 763 * family, and the remaining 16 typically forming a bitmask of revisions
756 764 * within that family with more significant bits indicating "later" revisions.
757 765 */
758 766
759 767 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
760 768 #define _X86_CHIPREV_VENDOR_SHIFT 24
761 769 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
762 770 #define _X86_CHIPREV_FAMILY_SHIFT 16
763 771 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
764 772
765 773 #define _X86_CHIPREV_VENDOR(x) \
766 774 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
767 775 #define _X86_CHIPREV_FAMILY(x) \
768 776 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
769 777 #define _X86_CHIPREV_REV(x) \
770 778 ((x) & _X86_CHIPREV_REV_MASK)
771 779
772 780 /* True if x matches in vendor and family and if x matches the given rev mask */
773 781 #define X86_CHIPREV_MATCH(x, mask) \
774 782 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
775 783 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
776 784 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
777 785
778 786 /* True if x matches in vendor and family, and rev is at least minx */
779 787 #define X86_CHIPREV_ATLEAST(x, minx) \
780 788 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
781 789 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
782 790 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
783 791
784 792 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
785 793 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
786 794 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
787 795
788 796 /* True if x matches in vendor, and family is at least minx */
789 797 #define X86_CHIPFAM_ATLEAST(x, minx) \
790 798 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
791 799 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
792 800
793 801 /* Revision default */
794 802 #define X86_CHIPREV_UNKNOWN 0x0
795 803
796 804 /*
797 805 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
798 806 * sufficiently different that we will distinguish them; in all other
799 807 * case we will identify the major revision.
800 808 */
801 809 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
802 810 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
803 811 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
804 812 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
805 813 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
806 814 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
807 815 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
808 816
809 817 /*
810 818 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
811 819 */
812 820 #define X86_CHIPREV_AMD_10_REV_A \
813 821 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
814 822 #define X86_CHIPREV_AMD_10_REV_B \
815 823 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
816 824 #define X86_CHIPREV_AMD_10_REV_C2 \
817 825 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
818 826 #define X86_CHIPREV_AMD_10_REV_C3 \
819 827 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
820 828 #define X86_CHIPREV_AMD_10_REV_D0 \
821 829 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
822 830 #define X86_CHIPREV_AMD_10_REV_D1 \
823 831 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
824 832 #define X86_CHIPREV_AMD_10_REV_E \
825 833 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
826 834
827 835 /*
828 836 * Definitions for AMD Family 0x11.
829 837 */
830 838 #define X86_CHIPREV_AMD_11_REV_B \
831 839 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
832 840
833 841 /*
834 842 * Definitions for AMD Family 0x12.
835 843 */
836 844 #define X86_CHIPREV_AMD_12_REV_B \
837 845 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
838 846
839 847 /*
840 848 * Definitions for AMD Family 0x14.
841 849 */
842 850 #define X86_CHIPREV_AMD_14_REV_B \
843 851 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
844 852 #define X86_CHIPREV_AMD_14_REV_C \
845 853 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
846 854
847 855 /*
848 856 * Definitions for AMD Family 0x15
849 857 */
850 858 #define X86_CHIPREV_AMD_15OR_REV_B2 \
851 859 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
852 860
853 861 #define X86_CHIPREV_AMD_15TN_REV_A1 \
854 862 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
855 863
856 864 #define X86_CHIPREV_AMD_150R_REV_C0 \
857 865 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0003)
858 866
859 867 #define X86_CHIPREV_AMD_15KV_REV_A1 \
860 868 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0004)
861 869
862 870 #define X86_CHIPREV_AMD_15F60 \
863 871 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0005)
864 872
865 873 #define X86_CHIPREV_AMD_15ST_REV_A0 \
866 874 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0006)
867 875
868 876 /*
869 877 * Definitions for AMD Family 0x16
870 878 */
871 879 #define X86_CHIPREV_AMD_16_KB_A1 \
872 880 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0001)
873 881
874 882 #define X86_CHIPREV_AMD_16_ML_A1 \
875 883 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0002)
876 884
877 885 /*
878 886 * Definitions for AMD Family 0x17
879 887 */
880 888
881 889 #define X86_CHIPREV_AMD_17_ZP_B1 \
882 890 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0001)
883 891
884 892 #define X86_CHIPREV_AMD_17_ZP_B2 \
885 893 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0002)
886 894
887 895 #define X86_CHIPREV_AMD_17_PiR_B2 \
888 896 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0003)
889 897
890 898 /*
891 899 * Various socket/package types, extended as the need to distinguish
892 900 * a new type arises. The top 8 byte identfies the vendor and the
893 901 * remaining 24 bits describe 24 socket types.
894 902 */
895 903
896 904 #define _X86_SOCKET_VENDOR_SHIFT 24
897 905 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
898 906 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
899 907 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
900 908
901 909 #define _X86_SOCKET_MKVAL(vendor, bitval) \
902 910 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
903 911
904 912 #define X86_SOCKET_MATCH(s, mask) \
905 913 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
906 914 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
907 915
908 916 #define X86_SOCKET_UNKNOWN 0x0
909 917 /*
910 918 * AMD socket types
911 919 */
912 920 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01)
913 921 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02)
914 922 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03)
915 923 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04)
916 924 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05)
917 925 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06)
918 926 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07)
919 927 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08)
920 928 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09)
921 929 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a)
922 930 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b)
923 931 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c)
924 932 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d)
925 933 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e)
926 934 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f)
927 935 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10)
928 936 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11)
929 937 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12)
930 938 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13)
931 939 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14)
932 940 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15)
933 941 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16)
934 942 #define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17)
935 943 #define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18)
936 944 #define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19)
937 945 #define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a)
938 946 #define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b)
939 947 #define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c)
940 948 #define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d)
941 949 #define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e)
942 950 #define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f)
943 951 #define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20)
944 952 #define X86_NUM_SOCKETS_AMD 0x21
945 953
946 954
947 955 /*
948 956 * Definitions for Intel processor models. These are all for Family 6
949 957 * processors. This list and the Atom set below it are not exhuastive.
950 958 */
951 959 #define INTC_MODEL_YONAH 0x0e
952 960 #define INTC_MODEL_MEROM 0x0f
953 961 #define INTC_MODEL_MEROM_L 0x16
954 962 #define INTC_MODEL_PENRYN 0x17
955 963 #define INTC_MODEL_DUNNINGTON 0x1d
956 964
957 965 #define INTC_MODEL_NEHALEM 0x1e
958 966 #define INTC_MODEL_NEHALEM2 0x1f
959 967 #define INTC_MODEL_NEHALEM_EP 0x1a
960 968 #define INTC_MODEL_NEHALEM_EX 0x2e
961 969
962 970 #define INTC_MODEL_WESTMERE 0x25
963 971 #define INTC_MODEL_WESTMERE_EP 0x2c
964 972 #define INTC_MODEL_WESTMERE_EX 0x2f
965 973
966 974 #define INTC_MODEL_SANDYBRIDGE 0x2a
967 975 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d
968 976 #define INTC_MODEL_IVYBRIDGE 0x3a
969 977 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e
970 978
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971 979 #define INTC_MODEL_HASWELL 0x3c
972 980 #define INTC_MODEL_HASWELL_ULT 0x45
973 981 #define INTC_MODEL_HASWELL_GT3E 0x46
974 982 #define INTC_MODEL_HASWELL_XEON 0x3f
975 983
976 984 #define INTC_MODEL_BROADWELL 0x3d
977 985 #define INTC_MODEL_BROADELL_2 0x47
978 986 #define INTC_MODEL_BROADWELL_XEON 0x4f
979 987 #define INTC_MODEL_BROADWELL_XEON_D 0x56
980 988
981 -#define INCC_MODEL_SKYLAKE_MOBILE 0x4e
989 +#define INTC_MODEL_SKYLAKE_MOBILE 0x4e
982 990 #define INTC_MODEL_SKYLAKE_XEON 0x55
983 991 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e
984 992
985 993 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e
986 994 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e
987 995
988 996 /*
989 997 * Atom Processors
990 998 */
991 999 #define INTC_MODEL_SILVERTHORNE 0x1c
992 1000 #define INTC_MODEL_LINCROFT 0x26
993 1001 #define INTC_MODEL_PENWELL 0x27
994 1002 #define INTC_MODEL_CLOVERVIEW 0x35
995 1003 #define INTC_MODEL_CEDARVIEW 0x36
996 1004 #define INTC_MODEL_BAY_TRAIL 0x37
997 1005 #define INTC_MODEL_AVATON 0x4d
998 1006 #define INTC_MODEL_AIRMONT 0x4c
999 1007 #define INTC_MODEL_GOLDMONT 0x5c
1000 1008 #define INTC_MODEL_DENVERTON 0x5f
1001 1009 #define INTC_MODEL_GEMINI_LAKE 0x7a
1002 1010
1003 1011 /*
1004 1012 * xgetbv/xsetbv support
1005 1013 * See section 13.3 in vol. 1 of the Intel devlopers manual.
1006 1014 */
1007 1015
1008 1016 #define XFEATURE_ENABLED_MASK 0x0
1009 1017 /*
1010 1018 * XFEATURE_ENABLED_MASK values (eax)
1011 1019 * See setup_xfem().
1012 1020 */
1013 1021 #define XFEATURE_LEGACY_FP 0x1
1014 1022 #define XFEATURE_SSE 0x2
1015 1023 #define XFEATURE_AVX 0x4
1016 1024 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */
1017 1025 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */
1018 1026 /* bit 8 unused */
1019 1027 #define XFEATURE_PKRU 0x200
1020 1028 #define XFEATURE_FP_ALL \
1021 1029 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
1022 1030 XFEATURE_AVX512 | XFEATURE_PKRU)
1023 1031
1024 1032 /*
1025 1033 * Define the set of xfeature flags that should be considered valid in the xsave
1026 1034 * state vector when we initialize an lwp. This is distinct from the full set so
1027 1035 * that all of the processor's normal logic and tracking of the xsave state is
1028 1036 * usable. This should correspond to the state that's been initialized by the
1029 1037 * ABI to hold meaningful values. Adding additional bits here can have serious
1030 1038 * performance implications and cause performance degradations when using the
1031 1039 * FPU vector (xmm) registers.
1032 1040 */
1033 1041 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
1034 1042
1035 1043 #if !defined(_ASM)
1036 1044
1037 1045 #if defined(_KERNEL) || defined(_KMEMUSER)
1038 1046
1039 1047 #define NUM_X86_FEATURES 97
1040 1048 extern uchar_t x86_featureset[];
1041 1049
1042 1050 extern void free_x86_featureset(void *featureset);
1043 1051 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
1044 1052 extern void add_x86_feature(void *featureset, uint_t feature);
1045 1053 extern void remove_x86_feature(void *featureset, uint_t feature);
1046 1054 extern boolean_t compare_x86_featureset(void *setA, void *setB);
1047 1055 extern void print_x86_featureset(void *featureset);
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1048 1056
1049 1057
1050 1058 extern uint_t x86_type;
1051 1059 extern uint_t x86_vendor;
1052 1060 extern uint_t x86_clflush_size;
1053 1061
1054 1062 extern uint_t pentiumpro_bug4046376;
1055 1063
1056 1064 extern const char CyrixInstead[];
1057 1065
1066 +/*
1067 + * These functions are all used to perform various side-channel mitigations.
1068 + * Please see uts/i86pc/os/cpuid.c for more information.
1069 + */
1058 1070 extern void (*spec_uarch_flush)(void);
1071 +extern void x86_rsb_stuff(void);
1072 +extern void x86_md_clear(void);
1059 1073
1060 1074 #endif
1061 1075
1062 1076 #if defined(_KERNEL)
1063 1077
1064 1078 /*
1065 - * x86_md_clear is the main entry point that should be called to deal with
1066 - * clearing u-arch buffers. Implementations are below because they're
1067 - * implemented in ASM. They shouldn't be used.
1068 - */
1069 -extern void (*x86_md_clear)(void);
1070 -extern void x86_md_clear_noop(void);
1071 -extern void x86_md_clear_verw(void);
1072 -
1073 -/*
1074 1079 * This structure is used to pass arguments and get return values back
1075 1080 * from the CPUID instruction in __cpuid_insn() routine.
1076 1081 */
1077 1082 struct cpuid_regs {
1078 1083 uint32_t cp_eax;
1079 1084 uint32_t cp_ebx;
1080 1085 uint32_t cp_ecx;
1081 1086 uint32_t cp_edx;
1082 1087 };
1083 1088
1084 1089 extern int x86_use_pcid;
1085 1090 extern int x86_use_invpcid;
1086 1091
1087 1092 /*
1088 1093 * Utility functions to get/set extended control registers (XCR)
1089 1094 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
1090 1095 */
1091 1096 extern uint64_t get_xcr(uint_t);
1092 1097 extern void set_xcr(uint_t, uint64_t);
1093 1098
1094 1099 extern uint64_t rdmsr(uint_t);
1095 1100 extern void wrmsr(uint_t, const uint64_t);
1096 1101 extern uint64_t xrdmsr(uint_t);
1097 1102 extern void xwrmsr(uint_t, const uint64_t);
1098 1103 extern int checked_rdmsr(uint_t, uint64_t *);
1099 1104 extern int checked_wrmsr(uint_t, uint64_t);
1100 1105
1101 1106 extern void invalidate_cache(void);
1102 1107 extern ulong_t getcr4(void);
1103 1108 extern void setcr4(ulong_t);
1104 1109
1105 1110 extern void mtrr_sync(void);
1106 1111
1107 1112 extern void cpu_fast_syscall_enable(void);
1108 1113 extern void cpu_fast_syscall_disable(void);
1109 1114
1110 1115 struct cpu;
1111 1116
1112 1117 extern int cpuid_checkpass(struct cpu *, int);
1113 1118 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
1114 1119 extern uint32_t __cpuid_insn(struct cpuid_regs *);
1115 1120 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
1116 1121 extern int cpuid_getidstr(struct cpu *, char *, size_t);
1117 1122 extern const char *cpuid_getvendorstr(struct cpu *);
1118 1123 extern uint_t cpuid_getvendor(struct cpu *);
1119 1124 extern uint_t cpuid_getfamily(struct cpu *);
1120 1125 extern uint_t cpuid_getmodel(struct cpu *);
1121 1126 extern uint_t cpuid_getstep(struct cpu *);
1122 1127 extern uint_t cpuid_getsig(struct cpu *);
1123 1128 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
1124 1129 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
1125 1130 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
1126 1131 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
1127 1132 extern int cpuid_get_chipid(struct cpu *);
1128 1133 extern id_t cpuid_get_coreid(struct cpu *);
1129 1134 extern int cpuid_get_pkgcoreid(struct cpu *);
1130 1135 extern int cpuid_get_clogid(struct cpu *);
1131 1136 extern int cpuid_get_cacheid(struct cpu *);
1132 1137 extern uint32_t cpuid_get_apicid(struct cpu *);
1133 1138 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
1134 1139 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
1135 1140 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
1136 1141 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
1137 1142 extern size_t cpuid_get_xsave_size();
1138 1143 extern boolean_t cpuid_need_fp_excp_handling();
1139 1144 extern int cpuid_is_cmt(struct cpu *);
1140 1145 extern int cpuid_syscall32_insn(struct cpu *);
1141 1146 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
1142 1147
1143 1148 extern uint32_t cpuid_getchiprev(struct cpu *);
1144 1149 extern const char *cpuid_getchiprevstr(struct cpu *);
1145 1150 extern uint32_t cpuid_getsockettype(struct cpu *);
1146 1151 extern const char *cpuid_getsocketstr(struct cpu *);
1147 1152
1148 1153 extern int cpuid_have_cr8access(struct cpu *);
1149 1154
1150 1155 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
1151 1156
1152 1157 struct cpuid_info;
1153 1158
1154 1159 extern void setx86isalist(void);
1155 1160 extern void cpuid_alloc_space(struct cpu *);
1156 1161 extern void cpuid_free_space(struct cpu *);
1157 1162 extern void cpuid_pass1(struct cpu *, uchar_t *);
1158 1163 extern void cpuid_pass2(struct cpu *);
1159 1164 extern void cpuid_pass3(struct cpu *);
1160 1165 extern void cpuid_pass4(struct cpu *, uint_t *);
1161 1166 extern void cpuid_set_cpu_properties(void *, processorid_t,
1162 1167 struct cpuid_info *);
1163 1168 extern void cpuid_pass_ucode(struct cpu *, uchar_t *);
1164 1169 extern void cpuid_post_ucodeadm(void);
1165 1170
1166 1171 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
1167 1172 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
1168 1173
1169 1174 #if !defined(__xpv)
1170 1175 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
1171 1176 extern void cpuid_mwait_free(struct cpu *);
1172 1177 extern int cpuid_deep_cstates_supported(void);
1173 1178 extern int cpuid_arat_supported(void);
1174 1179 extern int cpuid_iepb_supported(struct cpu *);
1175 1180 extern int cpuid_deadline_tsc_supported(void);
1176 1181 extern void vmware_port(int, uint32_t *);
1177 1182 #endif
1178 1183
1179 1184 struct cpu_ucode_info;
1180 1185
1181 1186 extern void ucode_alloc_space(struct cpu *);
1182 1187 extern void ucode_free_space(struct cpu *);
1183 1188 extern void ucode_check(struct cpu *);
1184 1189 extern void ucode_cleanup();
1185 1190
1186 1191 #if !defined(__xpv)
1187 1192 extern char _tsc_mfence_start;
1188 1193 extern char _tsc_mfence_end;
1189 1194 extern char _tscp_start;
1190 1195 extern char _tscp_end;
1191 1196 extern char _no_rdtsc_start;
1192 1197 extern char _no_rdtsc_end;
1193 1198 extern char _tsc_lfence_start;
1194 1199 extern char _tsc_lfence_end;
1195 1200 #endif
1196 1201
1197 1202 #if !defined(__xpv)
1198 1203 extern char bcopy_patch_start;
1199 1204 extern char bcopy_patch_end;
1200 1205 extern char bcopy_ck_size;
1201 1206 #endif
1202 1207
1203 1208 extern void post_startup_cpu_fixups(void);
1204 1209
1205 1210 extern uint_t workaround_errata(struct cpu *);
1206 1211
1207 1212 #if defined(OPTERON_ERRATUM_93)
1208 1213 extern int opteron_erratum_93;
1209 1214 #endif
1210 1215
1211 1216 #if defined(OPTERON_ERRATUM_91)
1212 1217 extern int opteron_erratum_91;
1213 1218 #endif
1214 1219
1215 1220 #if defined(OPTERON_ERRATUM_100)
1216 1221 extern int opteron_erratum_100;
1217 1222 #endif
1218 1223
1219 1224 #if defined(OPTERON_ERRATUM_121)
1220 1225 extern int opteron_erratum_121;
1221 1226 #endif
1222 1227
1223 1228 #if defined(OPTERON_WORKAROUND_6323525)
1224 1229 extern int opteron_workaround_6323525;
1225 1230 extern void patch_workaround_6323525(void);
1226 1231 #endif
1227 1232
1228 1233 #if !defined(__xpv)
1229 1234 extern void determine_platform(void);
1230 1235 #endif
1231 1236 extern int get_hwenv(void);
1232 1237 extern int is_controldom(void);
1233 1238
1234 1239 extern void enable_pcid(void);
1235 1240
1236 1241 extern void xsave_setup_msr(struct cpu *);
1237 1242
1238 1243 #if !defined(__xpv)
1239 1244 extern void reset_gdtr_limit(void);
1240 1245 #endif
1241 1246
1242 1247 /*
1243 1248 * Hypervisor signatures
1244 1249 */
1245 1250 #define HVSIG_XEN_HVM "XenVMMXenVMM"
1246 1251 #define HVSIG_VMWARE "VMwareVMware"
1247 1252 #define HVSIG_KVM "KVMKVMKVM"
1248 1253 #define HVSIG_MICROSOFT "Microsoft Hv"
1249 1254 #define HVSIG_BHYVE "bhyve bhyve "
1250 1255
1251 1256 /*
1252 1257 * Defined hardware environments
1253 1258 */
1254 1259 #define HW_NATIVE (1 << 0) /* Running on bare metal */
1255 1260 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
1256 1261
1257 1262 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
1258 1263 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
1259 1264 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
1260 1265 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
1261 1266 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */
1262 1267
1263 1268 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \
1264 1269 HW_BHYVE)
1265 1270
1266 1271 #endif /* _KERNEL */
1267 1272
1268 1273 #endif /* !_ASM */
1269 1274
1270 1275 /*
1271 1276 * VMware hypervisor related defines
1272 1277 */
1273 1278 #define VMWARE_HVMAGIC 0x564d5868
1274 1279 #define VMWARE_HVPORT 0x5658
1275 1280 #define VMWARE_HVCMD_GETVERSION 0x0a
1276 1281 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
1277 1282
1278 1283 #ifdef __cplusplus
1279 1284 }
1280 1285 #endif
1281 1286
1282 1287 #endif /* _SYS_X86_ARCHEXT_H */
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