530 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008
531 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010
532 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020
533 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040
534 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080
535 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100
536 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200
537 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f)
538
539 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2
540 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001
541 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002
542 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004
543 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010
544 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
545 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000
546 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
547 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000
548 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000
549
550 #define MCI_CTL_VALUE 0xffffffff
551
552 #define MTRR_TYPE_UC 0
553 #define MTRR_TYPE_WC 1
554 #define MTRR_TYPE_WT 4
555 #define MTRR_TYPE_WP 5
556 #define MTRR_TYPE_WB 6
557 #define MTRR_TYPE_UC_ 7
558
559 /*
560 * For Solaris we set up the page attritubute table in the following way:
561 * PAT0 Write-Back
562 * PAT1 Write-Through
563 * PAT2 Unchacheable-
564 * PAT3 Uncacheable
565 * PAT4 Write-Back
566 * PAT5 Write-Through
567 * PAT6 Write-Combine
568 * PAT7 Uncacheable
569 * The only difference from h/w default is entry 6.
961
962 #define INTC_MODEL_WESTMERE 0x25
963 #define INTC_MODEL_WESTMERE_EP 0x2c
964 #define INTC_MODEL_WESTMERE_EX 0x2f
965
966 #define INTC_MODEL_SANDYBRIDGE 0x2a
967 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d
968 #define INTC_MODEL_IVYBRIDGE 0x3a
969 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e
970
971 #define INTC_MODEL_HASWELL 0x3c
972 #define INTC_MODEL_HASWELL_ULT 0x45
973 #define INTC_MODEL_HASWELL_GT3E 0x46
974 #define INTC_MODEL_HASWELL_XEON 0x3f
975
976 #define INTC_MODEL_BROADWELL 0x3d
977 #define INTC_MODEL_BROADELL_2 0x47
978 #define INTC_MODEL_BROADWELL_XEON 0x4f
979 #define INTC_MODEL_BROADWELL_XEON_D 0x56
980
981 #define INCC_MODEL_SKYLAKE_MOBILE 0x4e
982 #define INTC_MODEL_SKYLAKE_XEON 0x55
983 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e
984
985 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e
986 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e
987
988 /*
989 * Atom Processors
990 */
991 #define INTC_MODEL_SILVERTHORNE 0x1c
992 #define INTC_MODEL_LINCROFT 0x26
993 #define INTC_MODEL_PENWELL 0x27
994 #define INTC_MODEL_CLOVERVIEW 0x35
995 #define INTC_MODEL_CEDARVIEW 0x36
996 #define INTC_MODEL_BAY_TRAIL 0x37
997 #define INTC_MODEL_AVATON 0x4d
998 #define INTC_MODEL_AIRMONT 0x4c
999 #define INTC_MODEL_GOLDMONT 0x5c
1000 #define INTC_MODEL_DENVERTON 0x5f
1001 #define INTC_MODEL_GEMINI_LAKE 0x7a
1038
1039 #define NUM_X86_FEATURES 97
1040 extern uchar_t x86_featureset[];
1041
1042 extern void free_x86_featureset(void *featureset);
1043 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
1044 extern void add_x86_feature(void *featureset, uint_t feature);
1045 extern void remove_x86_feature(void *featureset, uint_t feature);
1046 extern boolean_t compare_x86_featureset(void *setA, void *setB);
1047 extern void print_x86_featureset(void *featureset);
1048
1049
1050 extern uint_t x86_type;
1051 extern uint_t x86_vendor;
1052 extern uint_t x86_clflush_size;
1053
1054 extern uint_t pentiumpro_bug4046376;
1055
1056 extern const char CyrixInstead[];
1057
1058 extern void (*spec_uarch_flush)(void);
1059
1060 #endif
1061
1062 #if defined(_KERNEL)
1063
1064 /*
1065 * x86_md_clear is the main entry point that should be called to deal with
1066 * clearing u-arch buffers. Implementations are below because they're
1067 * implemented in ASM. They shouldn't be used.
1068 */
1069 extern void (*x86_md_clear)(void);
1070 extern void x86_md_clear_noop(void);
1071 extern void x86_md_clear_verw(void);
1072
1073 /*
1074 * This structure is used to pass arguments and get return values back
1075 * from the CPUID instruction in __cpuid_insn() routine.
1076 */
1077 struct cpuid_regs {
1078 uint32_t cp_eax;
1079 uint32_t cp_ebx;
1080 uint32_t cp_ecx;
1081 uint32_t cp_edx;
1082 };
1083
1084 extern int x86_use_pcid;
1085 extern int x86_use_invpcid;
1086
1087 /*
1088 * Utility functions to get/set extended control registers (XCR)
1089 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
1090 */
1091 extern uint64_t get_xcr(uint_t);
1092 extern void set_xcr(uint_t, uint64_t);
1093
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530 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008
531 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010
532 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020
533 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040
534 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080
535 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100
536 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200
537 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f)
538
539 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2
540 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001
541 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002
542 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004
543 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010
544 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
545 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000
546 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
547 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000
548 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000
549
550 /*
551 * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction
552 * decoding. Most notably, for the AMD variant of retpolines, we must improve
553 * the serializability of lfence for the lfence based method to work.
554 */
555 #define MSR_AMD_DECODE_CONFIG 0xc0011029
556 #define AMD_DECODE_CONFIG_LFENCE_DISPATCH 0x02
557
558 #define MCI_CTL_VALUE 0xffffffff
559
560 #define MTRR_TYPE_UC 0
561 #define MTRR_TYPE_WC 1
562 #define MTRR_TYPE_WT 4
563 #define MTRR_TYPE_WP 5
564 #define MTRR_TYPE_WB 6
565 #define MTRR_TYPE_UC_ 7
566
567 /*
568 * For Solaris we set up the page attritubute table in the following way:
569 * PAT0 Write-Back
570 * PAT1 Write-Through
571 * PAT2 Unchacheable-
572 * PAT3 Uncacheable
573 * PAT4 Write-Back
574 * PAT5 Write-Through
575 * PAT6 Write-Combine
576 * PAT7 Uncacheable
577 * The only difference from h/w default is entry 6.
969
970 #define INTC_MODEL_WESTMERE 0x25
971 #define INTC_MODEL_WESTMERE_EP 0x2c
972 #define INTC_MODEL_WESTMERE_EX 0x2f
973
974 #define INTC_MODEL_SANDYBRIDGE 0x2a
975 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d
976 #define INTC_MODEL_IVYBRIDGE 0x3a
977 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e
978
979 #define INTC_MODEL_HASWELL 0x3c
980 #define INTC_MODEL_HASWELL_ULT 0x45
981 #define INTC_MODEL_HASWELL_GT3E 0x46
982 #define INTC_MODEL_HASWELL_XEON 0x3f
983
984 #define INTC_MODEL_BROADWELL 0x3d
985 #define INTC_MODEL_BROADELL_2 0x47
986 #define INTC_MODEL_BROADWELL_XEON 0x4f
987 #define INTC_MODEL_BROADWELL_XEON_D 0x56
988
989 #define INTC_MODEL_SKYLAKE_MOBILE 0x4e
990 #define INTC_MODEL_SKYLAKE_XEON 0x55
991 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e
992
993 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e
994 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e
995
996 /*
997 * Atom Processors
998 */
999 #define INTC_MODEL_SILVERTHORNE 0x1c
1000 #define INTC_MODEL_LINCROFT 0x26
1001 #define INTC_MODEL_PENWELL 0x27
1002 #define INTC_MODEL_CLOVERVIEW 0x35
1003 #define INTC_MODEL_CEDARVIEW 0x36
1004 #define INTC_MODEL_BAY_TRAIL 0x37
1005 #define INTC_MODEL_AVATON 0x4d
1006 #define INTC_MODEL_AIRMONT 0x4c
1007 #define INTC_MODEL_GOLDMONT 0x5c
1008 #define INTC_MODEL_DENVERTON 0x5f
1009 #define INTC_MODEL_GEMINI_LAKE 0x7a
1046
1047 #define NUM_X86_FEATURES 97
1048 extern uchar_t x86_featureset[];
1049
1050 extern void free_x86_featureset(void *featureset);
1051 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
1052 extern void add_x86_feature(void *featureset, uint_t feature);
1053 extern void remove_x86_feature(void *featureset, uint_t feature);
1054 extern boolean_t compare_x86_featureset(void *setA, void *setB);
1055 extern void print_x86_featureset(void *featureset);
1056
1057
1058 extern uint_t x86_type;
1059 extern uint_t x86_vendor;
1060 extern uint_t x86_clflush_size;
1061
1062 extern uint_t pentiumpro_bug4046376;
1063
1064 extern const char CyrixInstead[];
1065
1066 /*
1067 * These functions are all used to perform various side-channel mitigations.
1068 * Please see uts/i86pc/os/cpuid.c for more information.
1069 */
1070 extern void (*spec_uarch_flush)(void);
1071 extern void x86_rsb_stuff(void);
1072 extern void x86_md_clear(void);
1073
1074 #endif
1075
1076 #if defined(_KERNEL)
1077
1078 /*
1079 * This structure is used to pass arguments and get return values back
1080 * from the CPUID instruction in __cpuid_insn() routine.
1081 */
1082 struct cpuid_regs {
1083 uint32_t cp_eax;
1084 uint32_t cp_ebx;
1085 uint32_t cp_ecx;
1086 uint32_t cp_edx;
1087 };
1088
1089 extern int x86_use_pcid;
1090 extern int x86_use_invpcid;
1091
1092 /*
1093 * Utility functions to get/set extended control registers (XCR)
1094 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
1095 */
1096 extern uint64_t get_xcr(uint_t);
1097 extern void set_xcr(uint_t, uint64_t);
1098
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