1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright (c) 2011 by Delphix. All rights reserved.
24 */
25 /*
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
28 */
29 /*
30 * Copyright 2019 Joyent, Inc.
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
33 * Copyright 2014 Josef 'Jeff' Sipek <jeffpc@josefsipek.net>
34 * Copyright 2018 Nexenta Systems, Inc.
35 */
36
37 #ifndef _SYS_X86_ARCHEXT_H
38 #define _SYS_X86_ARCHEXT_H
39
40 #if !defined(_ASM)
41 #include <sys/regset.h>
42 #include <sys/processor.h>
43 #include <vm/seg_enum.h>
44 #include <vm/page.h>
45 #endif /* _ASM */
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 /*
52 * cpuid instruction feature flags in %edx (standard function 1)
53 */
54
55 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */
56 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
57 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */
58 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */
59 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */
60 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
61 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */
62 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */
63 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
64 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */
65 /* 0x400 - reserved */
66 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */
67 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */
68 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */
69 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */
70 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */
71 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */
72 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
73 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
74 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */
75 /* 0x100000 - reserved */
76 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */
77 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */
78 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */
79 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
80 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */
81 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */
82 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
83 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */
84 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */
85 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */
86 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */
87
88 /*
89 * cpuid instruction feature flags in %ecx (standard function 1)
90 */
91
92 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */
93 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */
94 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
95 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */
96 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
97 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */
98 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */
99 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */
100 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */
101 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */
102 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */
103 /* 0x00000800 - reserved */
104 #define CPUID_INTC_ECX_FMA 0x00001000 /* Fused Multiply Add */
105 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */
106 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */
107 #define CPUID_INTC_ECX_PDCM 0x00008000 /* Perf/Debug Capability MSR */
108 /* 0x00010000 - reserved */
109 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
110 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */
111 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */
112 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */
113 #define CPUID_INTC_ECX_X2APIC 0x00200000 /* x2APIC */
114 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */
115 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */
116 #define CPUID_INTC_ECX_TSCDL 0x01000000 /* Deadline TSC */
117 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */
118 #define CPUID_INTC_ECX_XSAVE 0x04000000 /* XSAVE/XRESTOR insns */
119 #define CPUID_INTC_ECX_OSXSAVE 0x08000000 /* OS supports XSAVE insns */
120 #define CPUID_INTC_ECX_AVX 0x10000000 /* AVX supported */
121 #define CPUID_INTC_ECX_F16C 0x20000000 /* F16C supported */
122 #define CPUID_INTC_ECX_RDRAND 0x40000000 /* RDRAND supported */
123 #define CPUID_INTC_ECX_HV 0x80000000 /* Hypervisor */
124
125 /*
126 * cpuid instruction feature flags in %edx (extended function 0x80000001)
127 */
128
129 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */
130 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
131 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */
132 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */
133 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */
134 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */
135 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */
136 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */
137 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */
138 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */
139 /* 0x00000400 - sysc on K6m6 */
140 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */
141 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */
142 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */
143 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */
144 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */
145 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */
146 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */
147 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
148 /* 0x00040000 - reserved */
149 /* 0x00080000 - reserved */
150 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
151 /* 0x00200000 - reserved */
152 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */
153 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */
154 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */
155 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */
156 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */
157 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */
158 /* 0x10000000 - reserved */
159 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */
160 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */
161 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */
162
163 /*
164 * AMD extended function 0x80000001 %ecx
165 */
166
167 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */
168 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */
169 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */
170 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */
171 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
172 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */
173 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */
174 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */
175 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */
176 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */
177 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */
178 #define CPUID_AMD_ECX_XOP 0x00000800 /* AMD: Extended Operation */
179 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */
180 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */
181 /* 0x00004000 - reserved */
182 #define CPUID_AMD_ECX_LWP 0x00008000 /* AMD: Lightweight profiling */
183 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
184 /* 0x00020000 - reserved */
185 /* 0x00040000 - reserved */
186 #define CPUID_AMD_ECX_NIDMSR 0x00080000 /* AMD: Node ID MSR */
187 /* 0x00100000 - reserved */
188 #define CPUID_AMD_ECX_TBM 0x00200000 /* AMD: trailing bit manips. */
189 #define CPUID_AMD_ECX_TOPOEXT 0x00400000 /* AMD: Topology Extensions */
190 #define CPUID_AMD_ECX_PCEC 0x00800000 /* AMD: Core ext perf counter */
191 #define CUPID_AMD_ECX_PCENB 0x01000000 /* AMD: NB ext perf counter */
192 /* 0x02000000 - reserved */
193 #define CPUID_AMD_ECX_DBKP 0x40000000 /* AMD: Data breakpoint */
194 #define CPUID_AMD_ECX_PERFTSC 0x08000000 /* AMD: TSC Perf Counter */
195 #define CPUID_AMD_ECX_PERFL3 0x10000000 /* AMD: L3 Perf Counter */
196 #define CPUID_AMD_ECX_MONITORX 0x20000000 /* AMD: clzero */
197 /* 0x40000000 - reserved */
198 /* 0x80000000 - reserved */
199
200 /*
201 * AMD uses %ebx for some of their features (extended function 0x80000008).
202 */
203 #define CPUID_AMD_EBX_CLZERO 0x000000001 /* AMD: CLZERO instr */
204 #define CPUID_AMD_EBX_IRCMSR 0x000000002 /* AMD: Ret. instrs MSR */
205 #define CPUID_AMD_EBX_ERR_PTR_ZERO 0x000000004 /* AMD: FP Err. Ptr. Zero */
206 #define CPUID_AMD_EBX_IBPB 0x000001000 /* AMD: IBPB */
207 #define CPUID_AMD_EBX_IBRS 0x000004000 /* AMD: IBRS */
208 #define CPUID_AMD_EBX_STIBP 0x000008000 /* AMD: STIBP */
209 #define CPUID_AMD_EBX_IBRS_ALL 0x000010000 /* AMD: Enhanced IBRS */
210 #define CPUID_AMD_EBX_STIBP_ALL 0x000020000 /* AMD: STIBP ALL */
211 #define CPUID_AMD_EBX_PREFER_IBRS 0x000040000 /* AMD: Don't retpoline */
212 #define CPUID_AMD_EBX_SSBD 0x001000000 /* AMD: SSBD */
213 #define CPUID_AMD_EBX_VIRT_SSBD 0x002000000 /* AMD: VIRT SSBD */
214 #define CPUID_AMD_EBX_SSB_NO 0x004000000 /* AMD: SSB Fixed */
215
216 /*
217 * Intel now seems to have claimed part of the "extended" function
218 * space that we previously for non-Intel implementors to use.
219 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF
220 * is available in long mode i.e. what AMD indicate using bit 0.
221 * On the other hand, everything else is labelled as reserved.
222 */
223 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */
224
225 /*
226 * Intel uses cpuid leaf 6 to cover various thermal and power control
227 * operations.
228 */
229 #define CPUID_INTC_EAX_DTS 0x00000001 /* Digital Thermal Sensor */
230 #define CPUID_INTC_EAX_TURBO 0x00000002 /* Turboboost */
231 #define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */
232 /* bit 3 is reserved */
233 #define CPUID_INTC_EAX_PLN 0x00000010 /* Power limit notification */
234 #define CPUID_INTC_EAX_ECMD 0x00000020 /* Clock mod. duty cycle */
235 #define CPUID_INTC_EAX_PTM 0x00000040 /* Package thermal management */
236 #define CPUID_INTC_EAX_HWP 0x00000080 /* HWP base registers */
237 #define CPUID_INTC_EAX_HWP_NOT 0x00000100 /* HWP Notification */
238 #define CPUID_INTC_EAX_HWP_ACT 0x00000200 /* HWP Activity Window */
239 #define CPUID_INTC_EAX_HWP_EPR 0x00000400 /* HWP Energy Perf. Pref. */
240 #define CPUID_INTC_EAX_HWP_PLR 0x00000800 /* HWP Package Level Request */
241 /* bit 12 is reserved */
242 #define CPUID_INTC_EAX_HDC 0x00002000 /* HDC */
243 #define CPUID_INTC_EAX_TURBO3 0x00004000 /* Turbo Boost Max Tech 3.0 */
244 #define CPUID_INTC_EAX_HWP_CAP 0x00008000 /* HWP Capabilities */
245 #define CPUID_INTC_EAX_HWP_PECI 0x00010000 /* HWP PECI override */
246 #define CPUID_INTC_EAX_HWP_FLEX 0x00020000 /* Flexible HWP */
247 #define CPUID_INTC_EAX_HWP_FAST 0x00040000 /* Fast IA32_HWP_REQUEST */
248 /* bit 19 is reserved */
249 #define CPUID_INTC_EAX_HWP_IDLE 0x00100000 /* Ignore Idle Logical HWP */
250
251 #define CPUID_INTC_EBX_DTS_NTRESH(x) ((x) & 0xf)
252
253 #define CPUID_INTC_ECX_MAPERF 0x00000001 /* IA32_MPERF / IA32_APERF */
254 /* bits 1-2 are reserved */
255 #define CPUID_INTC_ECX_PERFBIAS 0x00000008 /* IA32_ENERGY_PERF_BIAS */
256
257 /*
258 * Intel also uses cpuid leaf 7 to have additional instructions and features.
259 * Like some other leaves, but unlike the current ones we care about, it
260 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
261 * with the potential use of additional sub-leaves in the future, we now
262 * specifically label the EBX features with their leaf and sub-leaf.
263 */
264 #define CPUID_INTC_EBX_7_0_FSGSBASE 0x00000001 /* FSGSBASE */
265 #define CPUID_INTC_EBX_7_0_TSC_ADJ 0x00000002 /* TSC adjust MSR */
266 #define CPUID_INTC_EBX_7_0_SGX 0x00000004 /* SGX */
267 #define CPUID_INTC_EBX_7_0_BMI1 0x00000008 /* BMI1 instrs */
268 #define CPUID_INTC_EBX_7_0_HLE 0x00000010 /* HLE */
269 #define CPUID_INTC_EBX_7_0_AVX2 0x00000020 /* AVX2 supported */
270 /* Bit 6 is reserved */
271 #define CPUID_INTC_EBX_7_0_SMEP 0x00000080 /* SMEP in CR4 */
272 #define CPUID_INTC_EBX_7_0_BMI2 0x00000100 /* BMI2 instrs */
273 #define CPUID_INTC_EBX_7_0_ENH_REP_MOV 0x00000200 /* Enhanced REP MOVSB */
274 #define CPUID_INTC_EBX_7_0_INVPCID 0x00000400 /* invpcid instr */
275 #define CPUID_INTC_EBX_7_0_RTM 0x00000800 /* RTM instrs */
276 #define CPUID_INTC_EBX_7_0_PQM 0x00001000 /* QoS Monitoring */
277 #define CPUID_INTC_EBX_7_0_DEP_CSDS 0x00002000 /* Deprecates CS/DS */
278 #define CPUID_INTC_EBX_7_0_MPX 0x00004000 /* Mem. Prot. Ext. */
279 #define CPUID_INTC_EBX_7_0_PQE 0x00080000 /* QoS Enforcement */
280 #define CPUID_INTC_EBX_7_0_AVX512F 0x00010000 /* AVX512 foundation */
281 #define CPUID_INTC_EBX_7_0_AVX512DQ 0x00020000 /* AVX512DQ */
282 #define CPUID_INTC_EBX_7_0_RDSEED 0x00040000 /* RDSEED instr */
283 #define CPUID_INTC_EBX_7_0_ADX 0x00080000 /* ADX instrs */
284 #define CPUID_INTC_EBX_7_0_SMAP 0x00100000 /* SMAP in CR 4 */
285 #define CPUID_INTC_EBX_7_0_AVX512IFMA 0x00200000 /* AVX512IFMA */
286 /* Bit 22 is reserved */
287 #define CPUID_INTC_EBX_7_0_CLFLUSHOPT 0x00800000 /* CLFLUSOPT */
288 #define CPUID_INTC_EBX_7_0_CLWB 0x01000000 /* CLWB */
289 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */
290 #define CPUID_INTC_EBX_7_0_AVX512PF 0x04000000 /* AVX512PF */
291 #define CPUID_INTC_EBX_7_0_AVX512ER 0x08000000 /* AVX512ER */
292 #define CPUID_INTC_EBX_7_0_AVX512CD 0x10000000 /* AVX512CD */
293 #define CPUID_INTC_EBX_7_0_SHA 0x20000000 /* SHA extensions */
294 #define CPUID_INTC_EBX_7_0_AVX512BW 0x40000000 /* AVX512BW */
295 #define CPUID_INTC_EBX_7_0_AVX512VL 0x80000000 /* AVX512VL */
296
297 #define CPUID_INTC_EBX_7_0_ALL_AVX512 \
298 (CPUID_INTC_EBX_7_0_AVX512F | CPUID_INTC_EBX_7_0_AVX512DQ | \
299 CPUID_INTC_EBX_7_0_AVX512IFMA | CPUID_INTC_EBX_7_0_AVX512PF | \
300 CPUID_INTC_EBX_7_0_AVX512ER | CPUID_INTC_EBX_7_0_AVX512CD | \
301 CPUID_INTC_EBX_7_0_AVX512BW | CPUID_INTC_EBX_7_0_AVX512VL)
302
303 #define CPUID_INTC_ECX_7_0_PREFETCHWT1 0x00000001 /* PREFETCHWT1 */
304 #define CPUID_INTC_ECX_7_0_AVX512VBMI 0x00000002 /* AVX512VBMI */
305 #define CPUID_INTC_ECX_7_0_UMIP 0x00000004 /* UMIP */
306 #define CPUID_INTC_ECX_7_0_PKU 0x00000008 /* umode prot. keys */
307 #define CPUID_INTC_ECX_7_0_OSPKE 0x00000010 /* OSPKE */
308 #define CPUID_INTC_ECX_7_0_WAITPKG 0x00000020 /* WAITPKG */
309 #define CPUID_INTC_ECX_7_0_AVX512VBMI2 0x00000040 /* AVX512 VBMI2 */
310 /* bit 7 is reserved */
311 #define CPUID_INTC_ECX_7_0_GFNI 0x00000100 /* GFNI */
312 #define CPUID_INTC_ECX_7_0_VAES 0x00000200 /* VAES */
313 #define CPUID_INTC_ECX_7_0_VPCLMULQDQ 0x00000400 /* VPCLMULQDQ */
314 #define CPUID_INTC_ECX_7_0_AVX512VNNI 0x00000800 /* AVX512 VNNI */
315 #define CPUID_INTC_ECX_7_0_AVX512BITALG 0x00001000 /* AVX512 BITALG */
316 /* bit 13 is reserved */
317 #define CPUID_INTC_ECX_7_0_AVX512VPOPCDQ 0x00004000 /* AVX512 VPOPCNTDQ */
318 /* bits 15-16 are reserved */
319 /* bits 17-21 are the value of MAWAU */
320 #define CPUID_INTC_ECX_7_0_RDPID 0x00400000 /* RPID, IA32_TSC_AUX */
321 /* bits 23-24 are reserved */
322 #define CPUID_INTC_ECX_7_0_CLDEMOTE 0x02000000 /* Cache line demote */
323 /* bit 26 is resrved */
324 #define CPUID_INTC_ECX_7_0_MOVDIRI 0x08000000 /* MOVDIRI insn */
325 #define CPUID_INTC_ECX_7_0_MOVDIR64B 0x10000000 /* MOVDIR64B insn */
326 /* bit 29 is reserved */
327 #define CPUID_INTC_ECX_7_0_SGXLC 0x40000000 /* SGX Launch config */
328 /* bit 31 is reserved */
329
330 /*
331 * While CPUID_INTC_ECX_7_0_GFNI, CPUID_INTC_ECX_7_0_VAES, and
332 * CPUID_INTC_ECX_7_0_VPCLMULQDQ all have AVX512 components, they are still
333 * valid when AVX512 is not. However, the following flags all are only valid
334 * when AVX512 is present.
335 */
336 #define CPUID_INTC_ECX_7_0_ALL_AVX512 \
337 (CPUID_INTC_ECX_7_0_AVX512VBMI | CPUID_INTC_ECX_7_0_AVX512VNNI | \
338 CPUID_INTC_ECX_7_0_AVX512BITALG | CPUID_INTC_ECX_7_0_AVX512VPOPCDQ)
339
340 /* bits 0-1 are reserved */
341 #define CPUID_INTC_EDX_7_0_AVX5124NNIW 0x00000004 /* AVX512 4NNIW */
342 #define CPUID_INTC_EDX_7_0_AVX5124FMAPS 0x00000008 /* AVX512 4FMAPS */
343 #define CPUID_INTC_EDX_7_0_FSREPMOV 0x00000010 /* fast short rep mov */
344 /* bits 5-9 are reserved */
345 #define CPUID_INTC_EDX_7_0_MD_CLEAR 0x00000400 /* MB VERW */
346 /* bits 11-17 are reserved */
347 #define CPUID_INTC_EDX_7_0_PCONFIG 0x00040000 /* PCONFIG */
348 /* bits 19-26 are reserved */
349 #define CPUID_INTC_EDX_7_0_SPEC_CTRL 0x04000000 /* Spec, IBPB, IBRS */
350 #define CPUID_INTC_EDX_7_0_STIBP 0x08000000 /* STIBP */
351 #define CPUID_INTC_EDX_7_0_FLUSH_CMD 0x10000000 /* IA32_FLUSH_CMD */
352 #define CPUID_INTC_EDX_7_0_ARCH_CAPS 0x20000000 /* IA32_ARCH_CAPS */
353 #define CPUID_INTC_EDX_7_0_SSBD 0x80000000 /* SSBD */
354
355 #define CPUID_INTC_EDX_7_0_ALL_AVX512 \
356 (CPUID_INTC_EDX_7_0_AVX5124NNIW | CPUID_INTC_EDX_7_0_AVX5124FMAPS)
357
358 /*
359 * Intel also uses cpuid leaf 0xd to report additional instructions and features
360 * when the sub-leaf in %ecx == 1. We label these using the same convention as
361 * with leaf 7.
362 */
363 #define CPUID_INTC_EAX_D_1_XSAVEOPT 0x00000001 /* xsaveopt inst. */
364 #define CPUID_INTC_EAX_D_1_XSAVEC 0x00000002 /* xsavec inst. */
365 #define CPUID_INTC_EAX_D_1_XSAVES 0x00000008 /* xsaves inst. */
366
367 #define REG_PAT 0x277
368 #define REG_TSC 0x10 /* timestamp counter */
369 #define REG_APIC_BASE_MSR 0x1b
370 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */
371
372 #if !defined(__xpv)
373 /*
374 * AMD C1E
375 */
376 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055
377 #define AMD_ACTONCMPHALT_SHIFT 27
378 #define AMD_ACTONCMPHALT_MASK 3
379 #endif
380
381 #define MSR_DEBUGCTL 0x1d9
382
383 #define DEBUGCTL_LBR 0x01
384 #define DEBUGCTL_BTF 0x02
385
386 /* Intel P6, AMD */
387 #define MSR_LBR_FROM 0x1db
388 #define MSR_LBR_TO 0x1dc
389 #define MSR_LEX_FROM 0x1dd
390 #define MSR_LEX_TO 0x1de
391
392 /* Intel P4 (pre-Prescott, non P4 M) */
393 #define MSR_P4_LBSTK_TOS 0x1da
394 #define MSR_P4_LBSTK_0 0x1db
395 #define MSR_P4_LBSTK_1 0x1dc
396 #define MSR_P4_LBSTK_2 0x1dd
397 #define MSR_P4_LBSTK_3 0x1de
398
399 /* Intel Pentium M */
400 #define MSR_P6M_LBSTK_TOS 0x1c9
401 #define MSR_P6M_LBSTK_0 0x040
402 #define MSR_P6M_LBSTK_1 0x041
403 #define MSR_P6M_LBSTK_2 0x042
404 #define MSR_P6M_LBSTK_3 0x043
405 #define MSR_P6M_LBSTK_4 0x044
406 #define MSR_P6M_LBSTK_5 0x045
407 #define MSR_P6M_LBSTK_6 0x046
408 #define MSR_P6M_LBSTK_7 0x047
409
410 /* Intel P4 (Prescott) */
411 #define MSR_PRP4_LBSTK_TOS 0x1da
412 #define MSR_PRP4_LBSTK_FROM_0 0x680
413 #define MSR_PRP4_LBSTK_FROM_1 0x681
414 #define MSR_PRP4_LBSTK_FROM_2 0x682
415 #define MSR_PRP4_LBSTK_FROM_3 0x683
416 #define MSR_PRP4_LBSTK_FROM_4 0x684
417 #define MSR_PRP4_LBSTK_FROM_5 0x685
418 #define MSR_PRP4_LBSTK_FROM_6 0x686
419 #define MSR_PRP4_LBSTK_FROM_7 0x687
420 #define MSR_PRP4_LBSTK_FROM_8 0x688
421 #define MSR_PRP4_LBSTK_FROM_9 0x689
422 #define MSR_PRP4_LBSTK_FROM_10 0x68a
423 #define MSR_PRP4_LBSTK_FROM_11 0x68b
424 #define MSR_PRP4_LBSTK_FROM_12 0x68c
425 #define MSR_PRP4_LBSTK_FROM_13 0x68d
426 #define MSR_PRP4_LBSTK_FROM_14 0x68e
427 #define MSR_PRP4_LBSTK_FROM_15 0x68f
428 #define MSR_PRP4_LBSTK_TO_0 0x6c0
429 #define MSR_PRP4_LBSTK_TO_1 0x6c1
430 #define MSR_PRP4_LBSTK_TO_2 0x6c2
431 #define MSR_PRP4_LBSTK_TO_3 0x6c3
432 #define MSR_PRP4_LBSTK_TO_4 0x6c4
433 #define MSR_PRP4_LBSTK_TO_5 0x6c5
434 #define MSR_PRP4_LBSTK_TO_6 0x6c6
435 #define MSR_PRP4_LBSTK_TO_7 0x6c7
436 #define MSR_PRP4_LBSTK_TO_8 0x6c8
437 #define MSR_PRP4_LBSTK_TO_9 0x6c9
438 #define MSR_PRP4_LBSTK_TO_10 0x6ca
439 #define MSR_PRP4_LBSTK_TO_11 0x6cb
440 #define MSR_PRP4_LBSTK_TO_12 0x6cc
441 #define MSR_PRP4_LBSTK_TO_13 0x6cd
442 #define MSR_PRP4_LBSTK_TO_14 0x6ce
443 #define MSR_PRP4_LBSTK_TO_15 0x6cf
444
445 /*
446 * General Xeon based MSRs
447 */
448 #define MSR_PPIN_CTL 0x04e
449 #define MSR_PPIN 0x04f
450 #define MSR_PLATFORM_INFO 0x0ce
451
452 #define MSR_PLATFORM_INFO_PPIN (1 << 23)
453 #define MSR_PPIN_CTL_MASK 0x03
454 #define MSR_PPIN_CTL_LOCKED 0x01
455 #define MSR_PPIN_CTL_ENABLED 0x02
456
457 /*
458 * Intel IA32_ARCH_CAPABILITIES MSR.
459 */
460 #define MSR_IA32_ARCH_CAPABILITIES 0x10a
461 #define IA32_ARCH_CAP_RDCL_NO 0x0001
462 #define IA32_ARCH_CAP_IBRS_ALL 0x0002
463 #define IA32_ARCH_CAP_RSBA 0x0004
464 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x0008
465 #define IA32_ARCH_CAP_SSB_NO 0x0010
466 #define IA32_ARCH_CAP_MDS_NO 0x0020
467
468 /*
469 * Intel Speculation related MSRs
470 */
471 #define MSR_IA32_SPEC_CTRL 0x48
472 #define IA32_SPEC_CTRL_IBRS 0x01
473 #define IA32_SPEC_CTRL_STIBP 0x02
474 #define IA32_SPEC_CTRL_SSBD 0x04
475
476 #define MSR_IA32_PRED_CMD 0x49
477 #define IA32_PRED_CMD_IBPB 0x01
478
479 #define MSR_IA32_FLUSH_CMD 0x10b
480 #define IA32_FLUSH_CMD_L1D 0x01
481
482 /*
483 * Intel Thermal MSRs
484 */
485 #define MSR_IA32_THERM_INTERRUPT 0x19b
486 #define IA32_THERM_INTERRUPT_HIGH_IE 0x00000001
487 #define IA32_THERM_INTERRUPT_LOW_IE 0x00000002
488 #define IA32_THERM_INTERRUPT_PROCHOT_IE 0x00000004
489 #define IA32_THERM_INTERRUPT_FORCEPR_IE 0x00000008
490 #define IA32_THERM_INTERRUPT_CRIT_IE 0x00000010
491 #define IA32_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
492 #define IA32_THERM_INTTERUPT_TR1_IE 0x00008000
493 #define IA32_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
494 #define IA32_THERM_INTERRUPT_TR2_IE 0x00800000
495 #define IA32_THERM_INTERRUPT_PL_NE 0x01000000
496
497 #define MSR_IA32_THERM_STATUS 0x19c
498 #define IA32_THERM_STATUS_STATUS 0x00000001
499 #define IA32_THERM_STATUS_STATUS_LOG 0x00000002
500 #define IA32_THERM_STATUS_PROCHOT 0x00000004
501 #define IA32_THERM_STATUS_PROCHOT_LOG 0x00000008
502 #define IA32_THERM_STATUS_CRIT_STATUS 0x00000010
503 #define IA32_THERM_STATUS_CRIT_LOG 0x00000020
504 #define IA32_THERM_STATUS_TR1_STATUS 0x00000040
505 #define IA32_THERM_STATUS_TR1_LOG 0x00000080
506 #define IA32_THERM_STATUS_TR2_STATUS 0x00000100
507 #define IA32_THERM_STATUS_TR2_LOG 0x00000200
508 #define IA32_THERM_STATUS_POWER_LIMIT_STATUS 0x00000400
509 #define IA32_THERM_STATUS_POWER_LIMIT_LOG 0x00000800
510 #define IA32_THERM_STATUS_CURRENT_STATUS 0x00001000
511 #define IA32_THERM_STATUS_CURRENT_LOG 0x00002000
512 #define IA32_THERM_STATUS_CROSS_DOMAIN_STATUS 0x00004000
513 #define IA32_THERM_STATUS_CROSS_DOMAIN_LOG 0x00008000
514 #define IA32_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f)
515 #define IA32_THERM_STATUS_RESOLUTION(x) (((x) >> 27) & 0x0f)
516 #define IA32_THERM_STATUS_READ_VALID 0x80000000
517
518 #define MSR_TEMPERATURE_TARGET 0x1a2
519 #define MSR_TEMPERATURE_TARGET_TARGET(x) (((x) >> 16) & 0xff)
520 /*
521 * Not all models support the offset. Refer to the Intel SDM Volume 4 for a list
522 * of which models have support for which bits.
523 */
524 #define MSR_TEMPERATURE_TARGET_OFFSET(x) (((x) >> 24) & 0x0f)
525
526 #define MSR_IA32_PACKAGE_THERM_STATUS 0x1b1
527 #define IA32_PKG_THERM_STATUS_STATUS 0x00000001
528 #define IA32_PKG_THERM_STATUS_STATUS_LOG 0x00000002
529 #define IA32_PKG_THERM_STATUS_PROCHOT 0x00000004
530 #define IA32_PKG_THERM_STATUS_PROCHOT_LOG 0x00000008
531 #define IA32_PKG_THERM_STATUS_CRIT_STATUS 0x00000010
532 #define IA32_PKG_THERM_STATUS_CRIT_LOG 0x00000020
533 #define IA32_PKG_THERM_STATUS_TR1_STATUS 0x00000040
534 #define IA32_PKG_THERM_STATUS_TR1_LOG 0x00000080
535 #define IA32_PKG_THERM_STATUS_TR2_STATUS 0x00000100
536 #define IA32_PKG_THERM_STATUS_TR2_LOG 0x00000200
537 #define IA32_PKG_THERM_STATUS_READING(x) (((x) >> 16) & 0x7f)
538
539 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x1b2
540 #define IA32_PKG_THERM_INTERRUPT_HIGH_IE 0x00000001
541 #define IA32_PKG_THERM_INTERRUPT_LOW_IE 0x00000002
542 #define IA32_PKG_THERM_INTERRUPT_PROCHOT_IE 0x00000004
543 #define IA32_PKG_THERM_INTERRUPT_OVERHEAT_IE 0x00000010
544 #define IA32_PKG_THERM_INTERRUPT_TR1_VAL(x) (((x) >> 8) & 0x7f)
545 #define IA32_PKG_THERM_INTTERUPT_TR1_IE 0x00008000
546 #define IA32_PKG_THERM_INTTERUPT_TR2_VAL(x) (((x) >> 16) & 0x7f)
547 #define IA32_PKG_THERM_INTERRUPT_TR2_IE 0x00800000
548 #define IA32_PKG_THERM_INTERRUPT_PL_NE 0x01000000
549
550 /*
551 * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction
552 * decoding. Most notably, for the AMD variant of retpolines, we must improve
553 * the serializability of lfence for the lfence based method to work.
554 */
555 #define MSR_AMD_DECODE_CONFIG 0xc0011029
556 #define AMD_DECODE_CONFIG_LFENCE_DISPATCH 0x02
557
558 #define MCI_CTL_VALUE 0xffffffff
559
560 #define MTRR_TYPE_UC 0
561 #define MTRR_TYPE_WC 1
562 #define MTRR_TYPE_WT 4
563 #define MTRR_TYPE_WP 5
564 #define MTRR_TYPE_WB 6
565 #define MTRR_TYPE_UC_ 7
566
567 /*
568 * For Solaris we set up the page attritubute table in the following way:
569 * PAT0 Write-Back
570 * PAT1 Write-Through
571 * PAT2 Unchacheable-
572 * PAT3 Uncacheable
573 * PAT4 Write-Back
574 * PAT5 Write-Through
575 * PAT6 Write-Combine
576 * PAT7 Uncacheable
577 * The only difference from h/w default is entry 6.
578 */
579 #define PAT_DEFAULT_ATTRIBUTE \
580 ((uint64_t)MTRR_TYPE_WB | \
581 ((uint64_t)MTRR_TYPE_WT << 8) | \
582 ((uint64_t)MTRR_TYPE_UC_ << 16) | \
583 ((uint64_t)MTRR_TYPE_UC << 24) | \
584 ((uint64_t)MTRR_TYPE_WB << 32) | \
585 ((uint64_t)MTRR_TYPE_WT << 40) | \
586 ((uint64_t)MTRR_TYPE_WC << 48) | \
587 ((uint64_t)MTRR_TYPE_UC << 56))
588
589 #define X86FSET_LARGEPAGE 0
590 #define X86FSET_TSC 1
591 #define X86FSET_MSR 2
592 #define X86FSET_MTRR 3
593 #define X86FSET_PGE 4
594 #define X86FSET_DE 5
595 #define X86FSET_CMOV 6
596 #define X86FSET_MMX 7
597 #define X86FSET_MCA 8
598 #define X86FSET_PAE 9
599 #define X86FSET_CX8 10
600 #define X86FSET_PAT 11
601 #define X86FSET_SEP 12
602 #define X86FSET_SSE 13
603 #define X86FSET_SSE2 14
604 #define X86FSET_HTT 15
605 #define X86FSET_ASYSC 16
606 #define X86FSET_NX 17
607 #define X86FSET_SSE3 18
608 #define X86FSET_CX16 19
609 #define X86FSET_CMP 20
610 #define X86FSET_TSCP 21
611 #define X86FSET_MWAIT 22
612 #define X86FSET_SSE4A 23
613 #define X86FSET_CPUID 24
614 #define X86FSET_SSSE3 25
615 #define X86FSET_SSE4_1 26
616 #define X86FSET_SSE4_2 27
617 #define X86FSET_1GPG 28
618 #define X86FSET_CLFSH 29
619 #define X86FSET_64 30
620 #define X86FSET_AES 31
621 #define X86FSET_PCLMULQDQ 32
622 #define X86FSET_XSAVE 33
623 #define X86FSET_AVX 34
624 #define X86FSET_VMX 35
625 #define X86FSET_SVM 36
626 #define X86FSET_TOPOEXT 37
627 #define X86FSET_F16C 38
628 #define X86FSET_RDRAND 39
629 #define X86FSET_X2APIC 40
630 #define X86FSET_AVX2 41
631 #define X86FSET_BMI1 42
632 #define X86FSET_BMI2 43
633 #define X86FSET_FMA 44
634 #define X86FSET_SMEP 45
635 #define X86FSET_SMAP 46
636 #define X86FSET_ADX 47
637 #define X86FSET_RDSEED 48
638 #define X86FSET_MPX 49
639 #define X86FSET_AVX512F 50
640 #define X86FSET_AVX512DQ 51
641 #define X86FSET_AVX512PF 52
642 #define X86FSET_AVX512ER 53
643 #define X86FSET_AVX512CD 54
644 #define X86FSET_AVX512BW 55
645 #define X86FSET_AVX512VL 56
646 #define X86FSET_AVX512FMA 57
647 #define X86FSET_AVX512VBMI 58
648 #define X86FSET_AVX512VPOPCDQ 59
649 #define X86FSET_AVX512NNIW 60
650 #define X86FSET_AVX512FMAPS 61
651 #define X86FSET_XSAVEOPT 62
652 #define X86FSET_XSAVEC 63
653 #define X86FSET_XSAVES 64
654 #define X86FSET_SHA 65
655 #define X86FSET_UMIP 66
656 #define X86FSET_PKU 67
657 #define X86FSET_OSPKE 68
658 #define X86FSET_PCID 69
659 #define X86FSET_INVPCID 70
660 #define X86FSET_IBRS 71
661 #define X86FSET_IBPB 72
662 #define X86FSET_STIBP 73
663 #define X86FSET_SSBD 74
664 #define X86FSET_SSBD_VIRT 75
665 #define X86FSET_RDCL_NO 76
666 #define X86FSET_IBRS_ALL 77
667 #define X86FSET_RSBA 78
668 #define X86FSET_SSB_NO 79
669 #define X86FSET_STIBP_ALL 80
670 #define X86FSET_FLUSH_CMD 81
671 #define X86FSET_L1D_VM_NO 82
672 #define X86FSET_FSGSBASE 83
673 #define X86FSET_CLFLUSHOPT 84
674 #define X86FSET_CLWB 85
675 #define X86FSET_MONITORX 86
676 #define X86FSET_CLZERO 87
677 #define X86FSET_XOP 88
678 #define X86FSET_FMA4 89
679 #define X86FSET_TBM 90
680 #define X86FSET_AVX512VNNI 91
681 #define X86FSET_AMD_PCEC 92
682 #define X86FSET_MD_CLEAR 93
683 #define X86FSET_MDS_NO 94
684 #define X86FSET_CORE_THERMAL 95
685 #define X86FSET_PKG_THERMAL 96
686
687 /*
688 * Intel Deep C-State invariant TSC in leaf 0x80000007.
689 */
690 #define CPUID_TSC_CSTATE_INVARIANCE (0x100)
691
692 /*
693 * Intel TSC deadline timer
694 */
695 #define CPUID_DEADLINE_TSC (1 << 24)
696
697 /*
698 * x86_type is a legacy concept; this is supplanted
699 * for most purposes by x86_featureset; modern CPUs
700 * should be X86_TYPE_OTHER
701 */
702 #define X86_TYPE_OTHER 0
703 #define X86_TYPE_486 1
704 #define X86_TYPE_P5 2
705 #define X86_TYPE_P6 3
706 #define X86_TYPE_CYRIX_486 4
707 #define X86_TYPE_CYRIX_6x86L 5
708 #define X86_TYPE_CYRIX_6x86 6
709 #define X86_TYPE_CYRIX_GXm 7
710 #define X86_TYPE_CYRIX_6x86MX 8
711 #define X86_TYPE_CYRIX_MediaGX 9
712 #define X86_TYPE_CYRIX_MII 10
713 #define X86_TYPE_VIA_CYRIX_III 11
714 #define X86_TYPE_P4 12
715
716 /*
717 * x86_vendor allows us to select between
718 * implementation features and helps guide
719 * the interpretation of the cpuid instruction.
720 */
721 #define X86_VENDOR_Intel 0
722 #define X86_VENDORSTR_Intel "GenuineIntel"
723
724 #define X86_VENDOR_IntelClone 1
725
726 #define X86_VENDOR_AMD 2
727 #define X86_VENDORSTR_AMD "AuthenticAMD"
728
729 #define X86_VENDOR_Cyrix 3
730 #define X86_VENDORSTR_CYRIX "CyrixInstead"
731
732 #define X86_VENDOR_UMC 4
733 #define X86_VENDORSTR_UMC "UMC UMC UMC "
734
735 #define X86_VENDOR_NexGen 5
736 #define X86_VENDORSTR_NexGen "NexGenDriven"
737
738 #define X86_VENDOR_Centaur 6
739 #define X86_VENDORSTR_Centaur "CentaurHauls"
740
741 #define X86_VENDOR_Rise 7
742 #define X86_VENDORSTR_Rise "RiseRiseRise"
743
744 #define X86_VENDOR_SiS 8
745 #define X86_VENDORSTR_SiS "SiS SiS SiS "
746
747 #define X86_VENDOR_TM 9
748 #define X86_VENDORSTR_TM "GenuineTMx86"
749
750 #define X86_VENDOR_NSC 10
751 #define X86_VENDORSTR_NSC "Geode by NSC"
752
753 /*
754 * Vendor string max len + \0
755 */
756 #define X86_VENDOR_STRLEN 13
757
758 /*
759 * Some vendor/family/model/stepping ranges are commonly grouped under
760 * a single identifying banner by the vendor. The following encode
761 * that "revision" in a uint32_t with the 8 most significant bits
762 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the
763 * family, and the remaining 16 typically forming a bitmask of revisions
764 * within that family with more significant bits indicating "later" revisions.
765 */
766
767 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u
768 #define _X86_CHIPREV_VENDOR_SHIFT 24
769 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u
770 #define _X86_CHIPREV_FAMILY_SHIFT 16
771 #define _X86_CHIPREV_REV_MASK 0x0000ffffu
772
773 #define _X86_CHIPREV_VENDOR(x) \
774 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT)
775 #define _X86_CHIPREV_FAMILY(x) \
776 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT)
777 #define _X86_CHIPREV_REV(x) \
778 ((x) & _X86_CHIPREV_REV_MASK)
779
780 /* True if x matches in vendor and family and if x matches the given rev mask */
781 #define X86_CHIPREV_MATCH(x, mask) \
782 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \
783 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \
784 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0))
785
786 /* True if x matches in vendor and family, and rev is at least minx */
787 #define X86_CHIPREV_ATLEAST(x, minx) \
788 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
789 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \
790 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx))
791
792 #define _X86_CHIPREV_MKREV(vendor, family, rev) \
793 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \
794 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev))
795
796 /* True if x matches in vendor, and family is at least minx */
797 #define X86_CHIPFAM_ATLEAST(x, minx) \
798 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \
799 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx))
800
801 /* Revision default */
802 #define X86_CHIPREV_UNKNOWN 0x0
803
804 /*
805 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are
806 * sufficiently different that we will distinguish them; in all other
807 * case we will identify the major revision.
808 */
809 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001)
810 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002)
811 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004)
812 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008)
813 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010)
814 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020)
815 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040)
816
817 /*
818 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only.
819 */
820 #define X86_CHIPREV_AMD_10_REV_A \
821 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001)
822 #define X86_CHIPREV_AMD_10_REV_B \
823 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002)
824 #define X86_CHIPREV_AMD_10_REV_C2 \
825 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004)
826 #define X86_CHIPREV_AMD_10_REV_C3 \
827 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008)
828 #define X86_CHIPREV_AMD_10_REV_D0 \
829 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0010)
830 #define X86_CHIPREV_AMD_10_REV_D1 \
831 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0020)
832 #define X86_CHIPREV_AMD_10_REV_E \
833 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0040)
834
835 /*
836 * Definitions for AMD Family 0x11.
837 */
838 #define X86_CHIPREV_AMD_11_REV_B \
839 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0002)
840
841 /*
842 * Definitions for AMD Family 0x12.
843 */
844 #define X86_CHIPREV_AMD_12_REV_B \
845 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x12, 0x0002)
846
847 /*
848 * Definitions for AMD Family 0x14.
849 */
850 #define X86_CHIPREV_AMD_14_REV_B \
851 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0002)
852 #define X86_CHIPREV_AMD_14_REV_C \
853 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x14, 0x0004)
854
855 /*
856 * Definitions for AMD Family 0x15
857 */
858 #define X86_CHIPREV_AMD_15OR_REV_B2 \
859 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0001)
860
861 #define X86_CHIPREV_AMD_15TN_REV_A1 \
862 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0002)
863
864 #define X86_CHIPREV_AMD_150R_REV_C0 \
865 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0003)
866
867 #define X86_CHIPREV_AMD_15KV_REV_A1 \
868 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0004)
869
870 #define X86_CHIPREV_AMD_15F60 \
871 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0005)
872
873 #define X86_CHIPREV_AMD_15ST_REV_A0 \
874 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x15, 0x0006)
875
876 /*
877 * Definitions for AMD Family 0x16
878 */
879 #define X86_CHIPREV_AMD_16_KB_A1 \
880 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0001)
881
882 #define X86_CHIPREV_AMD_16_ML_A1 \
883 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x16, 0x0002)
884
885 /*
886 * Definitions for AMD Family 0x17
887 */
888
889 #define X86_CHIPREV_AMD_17_ZP_B1 \
890 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0001)
891
892 #define X86_CHIPREV_AMD_17_ZP_B2 \
893 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0002)
894
895 #define X86_CHIPREV_AMD_17_PiR_B2 \
896 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x17, 0x0003)
897
898 /*
899 * Various socket/package types, extended as the need to distinguish
900 * a new type arises. The top 8 byte identfies the vendor and the
901 * remaining 24 bits describe 24 socket types.
902 */
903
904 #define _X86_SOCKET_VENDOR_SHIFT 24
905 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT)
906 #define _X86_SOCKET_TYPE_MASK 0x00ffffff
907 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK)
908
909 #define _X86_SOCKET_MKVAL(vendor, bitval) \
910 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval))
911
912 #define X86_SOCKET_MATCH(s, mask) \
913 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \
914 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0)
915
916 #define X86_SOCKET_UNKNOWN 0x0
917 /*
918 * AMD socket types
919 */
920 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x01)
921 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x02)
922 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x03)
923 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x04)
924 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x05)
925 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x06)
926 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x07)
927 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x08)
928 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x09)
929 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0a)
930 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0b)
931 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0c)
932 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0d)
933 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0e)
934 #define X86_SOCKET_S1g4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x0f)
935 #define X86_SOCKET_FT1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x10)
936 #define X86_SOCKET_FM1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x11)
937 #define X86_SOCKET_FS1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x12)
938 #define X86_SOCKET_AM3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x13)
939 #define X86_SOCKET_FP2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x14)
940 #define X86_SOCKET_FS1R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x15)
941 #define X86_SOCKET_FM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x16)
942 #define X86_SOCKET_FP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x17)
943 #define X86_SOCKET_FM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x18)
944 #define X86_SOCKET_FP4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x19)
945 #define X86_SOCKET_AM4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1a)
946 #define X86_SOCKET_FT3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1b)
947 #define X86_SOCKET_FT4 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1c)
948 #define X86_SOCKET_FS1B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1d)
949 #define X86_SOCKET_FT3B _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1e)
950 #define X86_SOCKET_SP3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x1f)
951 #define X86_SOCKET_SP3R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x20)
952 #define X86_NUM_SOCKETS_AMD 0x21
953
954
955 /*
956 * Definitions for Intel processor models. These are all for Family 6
957 * processors. This list and the Atom set below it are not exhuastive.
958 */
959 #define INTC_MODEL_YONAH 0x0e
960 #define INTC_MODEL_MEROM 0x0f
961 #define INTC_MODEL_MEROM_L 0x16
962 #define INTC_MODEL_PENRYN 0x17
963 #define INTC_MODEL_DUNNINGTON 0x1d
964
965 #define INTC_MODEL_NEHALEM 0x1e
966 #define INTC_MODEL_NEHALEM2 0x1f
967 #define INTC_MODEL_NEHALEM_EP 0x1a
968 #define INTC_MODEL_NEHALEM_EX 0x2e
969
970 #define INTC_MODEL_WESTMERE 0x25
971 #define INTC_MODEL_WESTMERE_EP 0x2c
972 #define INTC_MODEL_WESTMERE_EX 0x2f
973
974 #define INTC_MODEL_SANDYBRIDGE 0x2a
975 #define INTC_MODEL_SANDYBRIDGE_XEON 0x2d
976 #define INTC_MODEL_IVYBRIDGE 0x3a
977 #define INTC_MODEL_IVYBRIDGE_XEON 0x3e
978
979 #define INTC_MODEL_HASWELL 0x3c
980 #define INTC_MODEL_HASWELL_ULT 0x45
981 #define INTC_MODEL_HASWELL_GT3E 0x46
982 #define INTC_MODEL_HASWELL_XEON 0x3f
983
984 #define INTC_MODEL_BROADWELL 0x3d
985 #define INTC_MODEL_BROADELL_2 0x47
986 #define INTC_MODEL_BROADWELL_XEON 0x4f
987 #define INTC_MODEL_BROADWELL_XEON_D 0x56
988
989 #define INTC_MODEL_SKYLAKE_MOBILE 0x4e
990 #define INTC_MODEL_SKYLAKE_XEON 0x55
991 #define INTC_MODEL_SKYLAKE_DESKTOP 0x5e
992
993 #define INTC_MODEL_KABYLAKE_MOBILE 0x8e
994 #define INTC_MODEL_KABYLAKE_DESKTOP 0x9e
995
996 /*
997 * Atom Processors
998 */
999 #define INTC_MODEL_SILVERTHORNE 0x1c
1000 #define INTC_MODEL_LINCROFT 0x26
1001 #define INTC_MODEL_PENWELL 0x27
1002 #define INTC_MODEL_CLOVERVIEW 0x35
1003 #define INTC_MODEL_CEDARVIEW 0x36
1004 #define INTC_MODEL_BAY_TRAIL 0x37
1005 #define INTC_MODEL_AVATON 0x4d
1006 #define INTC_MODEL_AIRMONT 0x4c
1007 #define INTC_MODEL_GOLDMONT 0x5c
1008 #define INTC_MODEL_DENVERTON 0x5f
1009 #define INTC_MODEL_GEMINI_LAKE 0x7a
1010
1011 /*
1012 * xgetbv/xsetbv support
1013 * See section 13.3 in vol. 1 of the Intel devlopers manual.
1014 */
1015
1016 #define XFEATURE_ENABLED_MASK 0x0
1017 /*
1018 * XFEATURE_ENABLED_MASK values (eax)
1019 * See setup_xfem().
1020 */
1021 #define XFEATURE_LEGACY_FP 0x1
1022 #define XFEATURE_SSE 0x2
1023 #define XFEATURE_AVX 0x4
1024 #define XFEATURE_MPX 0x18 /* 2 bits, both 0 or 1 */
1025 #define XFEATURE_AVX512 0xe0 /* 3 bits, all 0 or 1 */
1026 /* bit 8 unused */
1027 #define XFEATURE_PKRU 0x200
1028 #define XFEATURE_FP_ALL \
1029 (XFEATURE_LEGACY_FP | XFEATURE_SSE | XFEATURE_AVX | XFEATURE_MPX | \
1030 XFEATURE_AVX512 | XFEATURE_PKRU)
1031
1032 /*
1033 * Define the set of xfeature flags that should be considered valid in the xsave
1034 * state vector when we initialize an lwp. This is distinct from the full set so
1035 * that all of the processor's normal logic and tracking of the xsave state is
1036 * usable. This should correspond to the state that's been initialized by the
1037 * ABI to hold meaningful values. Adding additional bits here can have serious
1038 * performance implications and cause performance degradations when using the
1039 * FPU vector (xmm) registers.
1040 */
1041 #define XFEATURE_FP_INITIAL (XFEATURE_LEGACY_FP | XFEATURE_SSE)
1042
1043 #if !defined(_ASM)
1044
1045 #if defined(_KERNEL) || defined(_KMEMUSER)
1046
1047 #define NUM_X86_FEATURES 97
1048 extern uchar_t x86_featureset[];
1049
1050 extern void free_x86_featureset(void *featureset);
1051 extern boolean_t is_x86_feature(void *featureset, uint_t feature);
1052 extern void add_x86_feature(void *featureset, uint_t feature);
1053 extern void remove_x86_feature(void *featureset, uint_t feature);
1054 extern boolean_t compare_x86_featureset(void *setA, void *setB);
1055 extern void print_x86_featureset(void *featureset);
1056
1057
1058 extern uint_t x86_type;
1059 extern uint_t x86_vendor;
1060 extern uint_t x86_clflush_size;
1061
1062 extern uint_t pentiumpro_bug4046376;
1063
1064 extern const char CyrixInstead[];
1065
1066 /*
1067 * These functions are all used to perform various side-channel mitigations.
1068 * Please see uts/i86pc/os/cpuid.c for more information.
1069 */
1070 extern void (*spec_uarch_flush)(void);
1071 extern void x86_rsb_stuff(void);
1072 extern void x86_md_clear(void);
1073
1074 #endif
1075
1076 #if defined(_KERNEL)
1077
1078 /*
1079 * This structure is used to pass arguments and get return values back
1080 * from the CPUID instruction in __cpuid_insn() routine.
1081 */
1082 struct cpuid_regs {
1083 uint32_t cp_eax;
1084 uint32_t cp_ebx;
1085 uint32_t cp_ecx;
1086 uint32_t cp_edx;
1087 };
1088
1089 extern int x86_use_pcid;
1090 extern int x86_use_invpcid;
1091
1092 /*
1093 * Utility functions to get/set extended control registers (XCR)
1094 * Initial use is to get/set the contents of the XFEATURE_ENABLED_MASK.
1095 */
1096 extern uint64_t get_xcr(uint_t);
1097 extern void set_xcr(uint_t, uint64_t);
1098
1099 extern uint64_t rdmsr(uint_t);
1100 extern void wrmsr(uint_t, const uint64_t);
1101 extern uint64_t xrdmsr(uint_t);
1102 extern void xwrmsr(uint_t, const uint64_t);
1103 extern int checked_rdmsr(uint_t, uint64_t *);
1104 extern int checked_wrmsr(uint_t, uint64_t);
1105
1106 extern void invalidate_cache(void);
1107 extern ulong_t getcr4(void);
1108 extern void setcr4(ulong_t);
1109
1110 extern void mtrr_sync(void);
1111
1112 extern void cpu_fast_syscall_enable(void);
1113 extern void cpu_fast_syscall_disable(void);
1114
1115 struct cpu;
1116
1117 extern int cpuid_checkpass(struct cpu *, int);
1118 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *);
1119 extern uint32_t __cpuid_insn(struct cpuid_regs *);
1120 extern int cpuid_getbrandstr(struct cpu *, char *, size_t);
1121 extern int cpuid_getidstr(struct cpu *, char *, size_t);
1122 extern const char *cpuid_getvendorstr(struct cpu *);
1123 extern uint_t cpuid_getvendor(struct cpu *);
1124 extern uint_t cpuid_getfamily(struct cpu *);
1125 extern uint_t cpuid_getmodel(struct cpu *);
1126 extern uint_t cpuid_getstep(struct cpu *);
1127 extern uint_t cpuid_getsig(struct cpu *);
1128 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *);
1129 extern uint_t cpuid_get_ncore_per_chip(struct cpu *);
1130 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *);
1131 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *);
1132 extern int cpuid_get_chipid(struct cpu *);
1133 extern id_t cpuid_get_coreid(struct cpu *);
1134 extern int cpuid_get_pkgcoreid(struct cpu *);
1135 extern int cpuid_get_clogid(struct cpu *);
1136 extern int cpuid_get_cacheid(struct cpu *);
1137 extern uint32_t cpuid_get_apicid(struct cpu *);
1138 extern uint_t cpuid_get_procnodeid(struct cpu *cpu);
1139 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu);
1140 extern uint_t cpuid_get_compunitid(struct cpu *cpu);
1141 extern uint_t cpuid_get_cores_per_compunit(struct cpu *cpu);
1142 extern size_t cpuid_get_xsave_size();
1143 extern boolean_t cpuid_need_fp_excp_handling();
1144 extern int cpuid_is_cmt(struct cpu *);
1145 extern int cpuid_syscall32_insn(struct cpu *);
1146 extern int getl2cacheinfo(struct cpu *, int *, int *, int *);
1147
1148 extern uint32_t cpuid_getchiprev(struct cpu *);
1149 extern const char *cpuid_getchiprevstr(struct cpu *);
1150 extern uint32_t cpuid_getsockettype(struct cpu *);
1151 extern const char *cpuid_getsocketstr(struct cpu *);
1152
1153 extern int cpuid_have_cr8access(struct cpu *);
1154
1155 extern int cpuid_opteron_erratum(struct cpu *, uint_t);
1156
1157 struct cpuid_info;
1158
1159 extern void setx86isalist(void);
1160 extern void cpuid_alloc_space(struct cpu *);
1161 extern void cpuid_free_space(struct cpu *);
1162 extern void cpuid_pass1(struct cpu *, uchar_t *);
1163 extern void cpuid_pass2(struct cpu *);
1164 extern void cpuid_pass3(struct cpu *);
1165 extern void cpuid_pass4(struct cpu *, uint_t *);
1166 extern void cpuid_set_cpu_properties(void *, processorid_t,
1167 struct cpuid_info *);
1168 extern void cpuid_pass_ucode(struct cpu *, uchar_t *);
1169 extern void cpuid_post_ucodeadm(void);
1170
1171 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *);
1172 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t);
1173
1174 #if !defined(__xpv)
1175 extern uint32_t *cpuid_mwait_alloc(struct cpu *);
1176 extern void cpuid_mwait_free(struct cpu *);
1177 extern int cpuid_deep_cstates_supported(void);
1178 extern int cpuid_arat_supported(void);
1179 extern int cpuid_iepb_supported(struct cpu *);
1180 extern int cpuid_deadline_tsc_supported(void);
1181 extern void vmware_port(int, uint32_t *);
1182 #endif
1183
1184 struct cpu_ucode_info;
1185
1186 extern void ucode_alloc_space(struct cpu *);
1187 extern void ucode_free_space(struct cpu *);
1188 extern void ucode_check(struct cpu *);
1189 extern void ucode_cleanup();
1190
1191 #if !defined(__xpv)
1192 extern char _tsc_mfence_start;
1193 extern char _tsc_mfence_end;
1194 extern char _tscp_start;
1195 extern char _tscp_end;
1196 extern char _no_rdtsc_start;
1197 extern char _no_rdtsc_end;
1198 extern char _tsc_lfence_start;
1199 extern char _tsc_lfence_end;
1200 #endif
1201
1202 #if !defined(__xpv)
1203 extern char bcopy_patch_start;
1204 extern char bcopy_patch_end;
1205 extern char bcopy_ck_size;
1206 #endif
1207
1208 extern void post_startup_cpu_fixups(void);
1209
1210 extern uint_t workaround_errata(struct cpu *);
1211
1212 #if defined(OPTERON_ERRATUM_93)
1213 extern int opteron_erratum_93;
1214 #endif
1215
1216 #if defined(OPTERON_ERRATUM_91)
1217 extern int opteron_erratum_91;
1218 #endif
1219
1220 #if defined(OPTERON_ERRATUM_100)
1221 extern int opteron_erratum_100;
1222 #endif
1223
1224 #if defined(OPTERON_ERRATUM_121)
1225 extern int opteron_erratum_121;
1226 #endif
1227
1228 #if defined(OPTERON_WORKAROUND_6323525)
1229 extern int opteron_workaround_6323525;
1230 extern void patch_workaround_6323525(void);
1231 #endif
1232
1233 #if !defined(__xpv)
1234 extern void determine_platform(void);
1235 #endif
1236 extern int get_hwenv(void);
1237 extern int is_controldom(void);
1238
1239 extern void enable_pcid(void);
1240
1241 extern void xsave_setup_msr(struct cpu *);
1242
1243 #if !defined(__xpv)
1244 extern void reset_gdtr_limit(void);
1245 #endif
1246
1247 /*
1248 * Hypervisor signatures
1249 */
1250 #define HVSIG_XEN_HVM "XenVMMXenVMM"
1251 #define HVSIG_VMWARE "VMwareVMware"
1252 #define HVSIG_KVM "KVMKVMKVM"
1253 #define HVSIG_MICROSOFT "Microsoft Hv"
1254 #define HVSIG_BHYVE "bhyve bhyve "
1255
1256 /*
1257 * Defined hardware environments
1258 */
1259 #define HW_NATIVE (1 << 0) /* Running on bare metal */
1260 #define HW_XEN_PV (1 << 1) /* Running on Xen PVM */
1261
1262 #define HW_XEN_HVM (1 << 2) /* Running on Xen HVM */
1263 #define HW_VMWARE (1 << 3) /* Running on VMware hypervisor */
1264 #define HW_KVM (1 << 4) /* Running on KVM hypervisor */
1265 #define HW_MICROSOFT (1 << 5) /* Running on Microsoft hypervisor */
1266 #define HW_BHYVE (1 << 6) /* Running on bhyve hypervisor */
1267
1268 #define HW_VIRTUAL (HW_XEN_HVM | HW_VMWARE | HW_KVM | HW_MICROSOFT | \
1269 HW_BHYVE)
1270
1271 #endif /* _KERNEL */
1272
1273 #endif /* !_ASM */
1274
1275 /*
1276 * VMware hypervisor related defines
1277 */
1278 #define VMWARE_HVMAGIC 0x564d5868
1279 #define VMWARE_HVPORT 0x5658
1280 #define VMWARE_HVCMD_GETVERSION 0x0a
1281 #define VMWARE_HVCMD_GETTSCFREQ 0x2d
1282
1283 #ifdef __cplusplus
1284 }
1285 #endif
1286
1287 #endif /* _SYS_X86_ARCHEXT_H */