8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24 /*
25 * Copyright (c) 2010, Intel Corporation.
26 * All rights reserved.
27 *
28 * Copyright 2018 Joyent, Inc.
29 */
30
31 #include <sys/asm_linkage.h>
32 #include <sys/asm_misc.h>
33 #include <sys/regset.h>
34 #include <sys/privregs.h>
35 #include <sys/x86_archext.h>
36
37 #if !defined(__lint)
38 #include <sys/segments.h>
39 #include "assym.h"
40 #endif
41
42 /*
43 * Our assumptions:
44 * - We are running in real mode.
45 * - Interrupts are disabled.
46 * - Selectors are equal (cs == ds == ss) for all real mode code
47 * - The GDT, IDT, ktss and page directory has been built for us
48 *
311 andq $~(CR0_TS|CR0_EM), %rax /* clear emulate math chip bit */
312 orq $(CR0_MP|CR0_NE), %rax
313 movq %rax, %cr0 /* set machine status word */
314
315 /*
316 * Before going any further, enable usage of page table NX bit if
317 * that's how our page tables are set up.
318 */
319 bt $X86FSET_NX, x86_featureset(%rip)
320 jnc 1f
321 movl $MSR_AMD_EFER, %ecx
322 rdmsr
323 orl $AMD_EFER_NXE, %eax
324 wrmsr
325 1:
326
327 /*
328 * Complete the rest of the setup and call mp_startup().
329 */
330 movq %gs:CPU_THREAD, %rax /* get thread ptr */
331 call *T_PC(%rax) /* call mp_startup_boot */
332 /* not reached */
333 int $20 /* whoops, returned somehow! */
334
335 SET_SIZE(real_mode_start_cpu)
336
337 #elif defined(__i386)
338
339 ENTRY_NP(real_mode_start_cpu)
340
341 #if !defined(__GNUC_AS__)
342
343 cli
344 D16 movw %cs, %eax
345 movw %eax, %ds /* load cs into ds */
346 movw %eax, %ss /* and into ss */
347
348 /*
349 * Helps in debugging by giving us the fault address.
350 *
351 * Remember to patch a hlt (0xf4) at cmntrap to get a good stack.
590 movw %eax, %ds /* load cs into ds */
591 movw %eax, %ss /* and into ss */
592
593 /*
594 * Jump to the stage 2 code in the rm_platter_va->rm_cpu_halt_code
595 */
596 movw $CPUHALTCODEOFF, %ax
597 .byte 0xff, 0xe0 /* jmp *%ax */
598
599 #else /* __GNUC_AS__ */
600
601 cli
602 mov %cs, %ax
603 mov %eax, %ds /* load cs into ds */
604 mov %eax, %ss /* and into ss */
605
606 /*
607 * Jump to the stage 2 code in the rm_platter_va->rm_cpu_halt_code
608 */
609 movw $CPUHALTCODEOFF, %ax
610 jmp *%ax
611
612 #endif /* !__GNUC_AS__ */
613
614 .globl real_mode_stop_cpu_stage1_end
615 real_mode_stop_cpu_stage1_end:
616 nop
617
618 SET_SIZE(real_mode_stop_cpu_stage1)
619
620 #endif /* __amd64 */
621
622 ENTRY_NP(real_mode_stop_cpu_stage2)
623
624 movw $0xdead, %ax
625 movw %ax, CPUHALTEDOFF
626
627 real_mode_stop_cpu_loop:
628 /*
629 * Put CPU into halted state.
|
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
23 */
24 /*
25 * Copyright (c) 2010, Intel Corporation.
26 * All rights reserved.
27 *
28 * Copyright 2019 Joyent, Inc.
29 */
30
31 #include <sys/asm_linkage.h>
32 #include <sys/asm_misc.h>
33 #include <sys/regset.h>
34 #include <sys/privregs.h>
35 #include <sys/x86_archext.h>
36
37 #if !defined(__lint)
38 #include <sys/segments.h>
39 #include "assym.h"
40 #endif
41
42 /*
43 * Our assumptions:
44 * - We are running in real mode.
45 * - Interrupts are disabled.
46 * - Selectors are equal (cs == ds == ss) for all real mode code
47 * - The GDT, IDT, ktss and page directory has been built for us
48 *
311 andq $~(CR0_TS|CR0_EM), %rax /* clear emulate math chip bit */
312 orq $(CR0_MP|CR0_NE), %rax
313 movq %rax, %cr0 /* set machine status word */
314
315 /*
316 * Before going any further, enable usage of page table NX bit if
317 * that's how our page tables are set up.
318 */
319 bt $X86FSET_NX, x86_featureset(%rip)
320 jnc 1f
321 movl $MSR_AMD_EFER, %ecx
322 rdmsr
323 orl $AMD_EFER_NXE, %eax
324 wrmsr
325 1:
326
327 /*
328 * Complete the rest of the setup and call mp_startup().
329 */
330 movq %gs:CPU_THREAD, %rax /* get thread ptr */
331 movq T_PC(%rax), %rax
332 INDIRECT_CALL_REG(rax) /* call mp_startup_boot */
333 /* not reached */
334 int $20 /* whoops, returned somehow! */
335
336 SET_SIZE(real_mode_start_cpu)
337
338 #elif defined(__i386)
339
340 ENTRY_NP(real_mode_start_cpu)
341
342 #if !defined(__GNUC_AS__)
343
344 cli
345 D16 movw %cs, %eax
346 movw %eax, %ds /* load cs into ds */
347 movw %eax, %ss /* and into ss */
348
349 /*
350 * Helps in debugging by giving us the fault address.
351 *
352 * Remember to patch a hlt (0xf4) at cmntrap to get a good stack.
591 movw %eax, %ds /* load cs into ds */
592 movw %eax, %ss /* and into ss */
593
594 /*
595 * Jump to the stage 2 code in the rm_platter_va->rm_cpu_halt_code
596 */
597 movw $CPUHALTCODEOFF, %ax
598 .byte 0xff, 0xe0 /* jmp *%ax */
599
600 #else /* __GNUC_AS__ */
601
602 cli
603 mov %cs, %ax
604 mov %eax, %ds /* load cs into ds */
605 mov %eax, %ss /* and into ss */
606
607 /*
608 * Jump to the stage 2 code in the rm_platter_va->rm_cpu_halt_code
609 */
610 movw $CPUHALTCODEOFF, %ax
611 /*
612 * The following indirect call is executed as part of starting up a CPU.
613 * As such nothing else should be running on it or executing in the
614 * system such that it is a viable Spectre v2 branch target injection
615 * location. At least, in theory.
616 */
617 jmp *%ax
618
619 #endif /* !__GNUC_AS__ */
620
621 .globl real_mode_stop_cpu_stage1_end
622 real_mode_stop_cpu_stage1_end:
623 nop
624
625 SET_SIZE(real_mode_stop_cpu_stage1)
626
627 #endif /* __amd64 */
628
629 ENTRY_NP(real_mode_stop_cpu_stage2)
630
631 movw $0xdead, %ax
632 movw %ax, CPUHALTEDOFF
633
634 real_mode_stop_cpu_loop:
635 /*
636 * Put CPU into halted state.
|